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fragment shader function call fix, gl_FragCoord fix
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_glsl.c
1 #include "macros.h"
2 #include "shader/prog_parameter.h"
3 #include "brw_context.h"
4 #include "brw_eu.h"
5 #include "brw_wm.h"
6
7 /* Only guess, need a flag in gl_fragment_program later */
8 GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp)
9 {
10 int i;
11 for (i = 0; i < fp->Base.NumInstructions; i++) {
12 struct prog_instruction *inst = &fp->Base.Instructions[i];
13 switch (inst->Opcode) {
14 case OPCODE_IF:
15 case OPCODE_INT:
16 case OPCODE_ENDIF:
17 case OPCODE_CAL:
18 case OPCODE_BRK:
19 case OPCODE_RET:
20 case OPCODE_DDX:
21 case OPCODE_DDY:
22 case OPCODE_BGNLOOP:
23 return GL_TRUE;
24 default:
25 break;
26 }
27 }
28 return GL_FALSE;
29 }
30
31 static void set_reg(struct brw_wm_compile *c, int file, int index,
32 int component, struct brw_reg reg)
33 {
34 c->wm_regs[file][index][component].reg = reg;
35 c->wm_regs[file][index][component].inited = GL_TRUE;
36 }
37
38 static int get_scalar_dst_index(struct prog_instruction *inst)
39 {
40 int i;
41 for (i = 0; i < 4; i++)
42 if (inst->DstReg.WriteMask & (1<<i))
43 break;
44 return i;
45 }
46
47 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
48 {
49 struct brw_reg reg;
50 reg = brw_vec8_grf(c->tmp_index--, 0);
51 return reg;
52 }
53
54 static void release_tmps(struct brw_wm_compile *c)
55 {
56 c->tmp_index = 127;
57 }
58
59 static struct brw_reg
60 get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs)
61 {
62 struct brw_reg reg;
63 switch (file) {
64 case PROGRAM_STATE_VAR:
65 case PROGRAM_CONSTANT:
66 case PROGRAM_UNIFORM:
67 file = PROGRAM_STATE_VAR;
68 break;
69 case PROGRAM_UNDEFINED:
70 return brw_null_reg();
71 default:
72 break;
73 }
74
75 if(c->wm_regs[file][index][component].inited)
76 reg = c->wm_regs[file][index][component].reg;
77 else
78 reg = brw_vec8_grf(c->reg_index, 0);
79
80 if(!c->wm_regs[file][index][component].inited) {
81 set_reg(c, file, index, component, reg);
82 c->reg_index++;
83 }
84
85 if (neg & (1<< component)) {
86 reg = negate(reg);
87 }
88 if (abs)
89 reg = brw_abs(reg);
90 return reg;
91 }
92
93 static void prealloc_reg(struct brw_wm_compile *c)
94 {
95 int i, j;
96 struct brw_reg reg;
97 int nr_interp_regs = 0;
98 GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
99
100 for (i = 0; i < 4; i++) {
101 reg = (i < c->key.nr_depth_regs)
102 ? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0);
103 set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
104 }
105 c->reg_index += 2*c->key.nr_depth_regs;
106 {
107 int nr_params = c->fp->program.Base.Parameters->NumParameters;
108 struct gl_program_parameter_list *plist =
109 c->fp->program.Base.Parameters;
110 int index = 0;
111 c->prog_data.nr_params = 4*nr_params;
112 for (i = 0; i < nr_params; i++) {
113 for (j = 0; j < 4; j++, index++) {
114 reg = brw_vec1_grf(c->reg_index + index/8,
115 index%8);
116 c->prog_data.param[index] =
117 &plist->ParameterValues[i][j];
118 set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
119 }
120 }
121 c->nr_creg = 2*((4*nr_params+15)/16);
122 c->reg_index += c->nr_creg;
123 }
124 for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
125 if (inputs & (1<<i)) {
126 nr_interp_regs++;
127 reg = brw_vec8_grf(c->reg_index, 0);
128 for (j = 0; j < 4; j++)
129 set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
130 c->reg_index += 2;
131
132 }
133 }
134 c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
135 c->prog_data.urb_read_length = nr_interp_regs * 2;
136 c->prog_data.curb_read_length = c->nr_creg;
137 c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
138 c->reg_index++;
139 c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
140 c->reg_index += 2;
141 }
142
143 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
144 struct prog_instruction *inst, int component, int nr)
145 {
146 return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
147 0, 0);
148 }
149
150 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
151 struct prog_src_register *src, int index, int nr)
152 {
153 int component = GET_SWZ(src->Swizzle, index);
154 return get_reg(c, src->File, src->Index, component, nr,
155 src->NegateBase, src->Abs);
156 }
157
158 static void emit_abs( struct brw_wm_compile *c,
159 struct prog_instruction *inst)
160 {
161 int i;
162 struct brw_compile *p = &c->func;
163 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
164 for (i = 0; i < 4; i++) {
165 if (inst->DstReg.WriteMask & (1<<i)) {
166 struct brw_reg src, dst;
167 dst = get_dst_reg(c, inst, i, 1);
168 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
169 brw_MOV(p, dst, brw_abs(src));
170 }
171 }
172 brw_set_saturate(p, 0);
173 }
174
175 static void emit_mov_int( struct brw_wm_compile *c,
176 struct prog_instruction *inst)
177 {
178 int i;
179 struct brw_compile *p = &c->func;
180 GLuint mask = inst->DstReg.WriteMask;
181 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
182 for (i = 0; i < 4; i++) {
183 if (mask & (1<<i)) {
184 struct brw_reg src, dst;
185 dst = retype(get_dst_reg(c, inst, i, 1), BRW_REGISTER_TYPE_D);
186 src = retype(get_src_reg(c, &inst->SrcReg[0], i, 1), BRW_REGISTER_TYPE_D);
187 brw_MOV(p, dst, src);
188 }
189 }
190 brw_set_saturate(p, 0);
191 }
192
193 static void emit_mov( struct brw_wm_compile *c,
194 struct prog_instruction *inst)
195 {
196 int i;
197 struct brw_compile *p = &c->func;
198 GLuint mask = inst->DstReg.WriteMask;
199 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
200 for (i = 0; i < 4; i++) {
201 if (mask & (1<<i)) {
202 struct brw_reg src, dst;
203 dst = get_dst_reg(c, inst, i, 1);
204 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
205 brw_MOV(p, dst, src);
206 }
207 }
208 brw_set_saturate(p, 0);
209 }
210
211 static void emit_pixel_xy(struct brw_wm_compile *c,
212 struct prog_instruction *inst)
213 {
214 struct brw_reg r1 = brw_vec1_grf(1, 0);
215 struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW);
216
217 struct brw_reg dst0, dst1;
218 struct brw_compile *p = &c->func;
219 GLuint mask = inst->DstReg.WriteMask;
220
221 dst0 = get_dst_reg(c, inst, 0, 1);
222 dst1 = get_dst_reg(c, inst, 1, 1);
223 /* Calculate pixel centers by adding 1 or 0 to each of the
224 * micro-tile coordinates passed in r1.
225 */
226 if (mask & WRITEMASK_X) {
227 brw_ADD(p,
228 vec8(retype(dst0, BRW_REGISTER_TYPE_UW)),
229 stride(suboffset(r1_uw, 4), 2, 4, 0),
230 brw_imm_v(0x10101010));
231 }
232
233 if (mask & WRITEMASK_Y) {
234 brw_ADD(p,
235 vec8(retype(dst1, BRW_REGISTER_TYPE_UW)),
236 stride(suboffset(r1_uw, 5), 2, 4, 0),
237 brw_imm_v(0x11001100));
238 }
239
240 }
241
242 static void emit_delta_xy(struct brw_wm_compile *c,
243 struct prog_instruction *inst)
244 {
245 struct brw_reg r1 = brw_vec1_grf(1, 0);
246 struct brw_reg dst0, dst1, src0, src1;
247 struct brw_compile *p = &c->func;
248 GLuint mask = inst->DstReg.WriteMask;
249
250 dst0 = get_dst_reg(c, inst, 0, 1);
251 dst1 = get_dst_reg(c, inst, 1, 1);
252 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
253 src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1);
254 /* Calc delta X,Y by subtracting origin in r1 from the pixel
255 * centers.
256 */
257 if (mask & WRITEMASK_X) {
258 brw_ADD(p,
259 dst0,
260 retype(src0, BRW_REGISTER_TYPE_UW),
261 negate(r1));
262 }
263
264 if (mask & WRITEMASK_Y) {
265 brw_ADD(p,
266 dst1,
267 retype(src1, BRW_REGISTER_TYPE_UW),
268 negate(suboffset(r1,1)));
269
270 }
271
272 }
273
274
275 static void fire_fb_write( struct brw_wm_compile *c,
276 GLuint base_reg,
277 GLuint nr )
278 {
279 struct brw_compile *p = &c->func;
280
281 /* Pass through control information:
282 */
283 /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */
284 {
285 brw_push_insn_state(p);
286 brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */
287 brw_MOV(p,
288 brw_message_reg(base_reg + 1),
289 brw_vec8_grf(1, 0));
290 brw_pop_insn_state(p);
291 }
292 /* Send framebuffer write message: */
293 brw_fb_WRITE(p,
294 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
295 base_reg,
296 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
297 0, /* render surface always 0 */
298 nr,
299 0,
300 1);
301 }
302
303 static void emit_fb_write(struct brw_wm_compile *c,
304 struct prog_instruction *inst)
305 {
306 struct brw_compile *p = &c->func;
307 int nr = 2;
308 int channel;
309 struct brw_reg src0;//, src1, src2, dst;
310
311 /* Reserve a space for AA - may not be needed:
312 */
313 if (c->key.aa_dest_stencil_reg)
314 nr += 1;
315 {
316 brw_push_insn_state(p);
317 for (channel = 0; channel < 4; channel++) {
318 src0 = get_src_reg(c, &inst->SrcReg[0], channel, 1);
319 /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */
320 /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */
321 brw_MOV(p, brw_message_reg(nr + channel), src0);
322 }
323 /* skip over the regs populated above: */
324 nr += 8;
325 brw_pop_insn_state(p);
326 }
327 fire_fb_write(c, 0, nr);
328 }
329
330 static void emit_pixel_w( struct brw_wm_compile *c,
331 struct prog_instruction *inst)
332 {
333 struct brw_compile *p = &c->func;
334 GLuint mask = inst->DstReg.WriteMask;
335 if (mask & WRITEMASK_W) {
336 struct brw_reg dst, src0, delta0, delta1;
337 struct brw_reg interp3;
338
339 dst = get_dst_reg(c, inst, 3, 1);
340 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
341 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
342 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
343
344 interp3 = brw_vec1_grf(src0.nr+1, 4);
345 /* Calc 1/w - just linterp wpos[3] optimized by putting the
346 * result straight into a message reg.
347 */
348 brw_LINE(p, brw_null_reg(), interp3, delta0);
349 brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1);
350
351 /* Calc w */
352 brw_math_16( p, dst,
353 BRW_MATH_FUNCTION_INV,
354 BRW_MATH_SATURATE_NONE,
355 2, brw_null_reg(),
356 BRW_MATH_PRECISION_FULL);
357 }
358 }
359
360 static void emit_linterp(struct brw_wm_compile *c,
361 struct prog_instruction *inst)
362 {
363 struct brw_compile *p = &c->func;
364 GLuint mask = inst->DstReg.WriteMask;
365 struct brw_reg interp[4];
366 struct brw_reg dst, delta0, delta1;
367 struct brw_reg src0;
368
369 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
370 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
371 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
372 GLuint nr = src0.nr;
373 int i;
374
375 interp[0] = brw_vec1_grf(nr, 0);
376 interp[1] = brw_vec1_grf(nr, 4);
377 interp[2] = brw_vec1_grf(nr+1, 0);
378 interp[3] = brw_vec1_grf(nr+1, 4);
379
380 for(i = 0; i < 4; i++ ) {
381 if (mask & (1<<i)) {
382 dst = get_dst_reg(c, inst, i, 1);
383 brw_LINE(p, brw_null_reg(), interp[i], delta0);
384 brw_MAC(p, dst, suboffset(interp[i],1), delta1);
385 }
386 }
387 }
388
389 static void emit_cinterp(struct brw_wm_compile *c,
390 struct prog_instruction *inst)
391 {
392 struct brw_compile *p = &c->func;
393 GLuint mask = inst->DstReg.WriteMask;
394
395 struct brw_reg interp[4];
396 struct brw_reg dst, src0;
397
398 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
399 GLuint nr = src0.nr;
400 int i;
401
402 interp[0] = brw_vec1_grf(nr, 0);
403 interp[1] = brw_vec1_grf(nr, 4);
404 interp[2] = brw_vec1_grf(nr+1, 0);
405 interp[3] = brw_vec1_grf(nr+1, 4);
406
407 for(i = 0; i < 4; i++ ) {
408 if (mask & (1<<i)) {
409 dst = get_dst_reg(c, inst, i, 1);
410 brw_MOV(p, dst, suboffset(interp[i],3));
411 }
412 }
413 }
414
415 static void emit_pinterp(struct brw_wm_compile *c,
416 struct prog_instruction *inst)
417 {
418 struct brw_compile *p = &c->func;
419 GLuint mask = inst->DstReg.WriteMask;
420
421 struct brw_reg interp[4];
422 struct brw_reg dst, delta0, delta1;
423 struct brw_reg src0, w;
424
425 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
426 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
427 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
428 w = get_src_reg(c, &inst->SrcReg[2], 3, 1);
429 GLuint nr = src0.nr;
430 int i;
431
432 interp[0] = brw_vec1_grf(nr, 0);
433 interp[1] = brw_vec1_grf(nr, 4);
434 interp[2] = brw_vec1_grf(nr+1, 0);
435 interp[3] = brw_vec1_grf(nr+1, 4);
436
437 for(i = 0; i < 4; i++ ) {
438 if (mask & (1<<i)) {
439 dst = get_dst_reg(c, inst, i, 1);
440 brw_LINE(p, brw_null_reg(), interp[i], delta0);
441 brw_MAC(p, dst, suboffset(interp[i],1),
442 delta1);
443 brw_MUL(p, dst, dst, w);
444 }
445 }
446 }
447
448 static void emit_xpd(struct brw_wm_compile *c,
449 struct prog_instruction *inst)
450 {
451 int i;
452 struct brw_compile *p = &c->func;
453 GLuint mask = inst->DstReg.WriteMask;
454 for (i = 0; i < 4; i++) {
455 GLuint i2 = (i+2)%3;
456 GLuint i1 = (i+1)%3;
457 if (mask & (1<<i)) {
458 struct brw_reg src0, src1, dst;
459 dst = get_dst_reg(c, inst, i, 1);
460 src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2, 1));
461 src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1);
462 brw_MUL(p, brw_null_reg(), src0, src1);
463 src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1);
464 src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1);
465 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
466 brw_MAC(p, dst, src0, src1);
467 brw_set_saturate(p, 0);
468 }
469 }
470 brw_set_saturate(p, 0);
471 }
472
473 static void emit_dp3(struct brw_wm_compile *c,
474 struct prog_instruction *inst)
475 {
476 struct brw_reg src0[3], src1[3], dst;
477 int i;
478 struct brw_compile *p = &c->func;
479 for (i = 0; i < 3; i++) {
480 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
481 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
482 }
483
484 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
485 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
486 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
487 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
488 brw_MAC(p, dst, src0[2], src1[2]);
489 brw_set_saturate(p, 0);
490 }
491
492 static void emit_dp4(struct brw_wm_compile *c,
493 struct prog_instruction *inst)
494 {
495 struct brw_reg src0[4], src1[4], dst;
496 int i;
497 struct brw_compile *p = &c->func;
498 for (i = 0; i < 4; i++) {
499 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
500 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
501 }
502 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
503 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
504 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
505 brw_MAC(p, brw_null_reg(), src0[2], src1[2]);
506 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
507 brw_MAC(p, dst, src0[3], src1[3]);
508 brw_set_saturate(p, 0);
509 }
510
511 static void emit_dph(struct brw_wm_compile *c,
512 struct prog_instruction *inst)
513 {
514 struct brw_reg src0[4], src1[4], dst;
515 int i;
516 struct brw_compile *p = &c->func;
517 for (i = 0; i < 4; i++) {
518 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
519 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
520 }
521 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
522 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
523 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
524 brw_MAC(p, dst, src0[2], src1[2]);
525 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
526 brw_ADD(p, dst, src0[3], src1[3]);
527 brw_set_saturate(p, 0);
528 }
529
530 static void emit_math1(struct brw_wm_compile *c,
531 struct prog_instruction *inst, GLuint func)
532 {
533 struct brw_compile *p = &c->func;
534 struct brw_reg src0, dst;
535
536 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
537 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
538 brw_MOV(p, brw_message_reg(2), src0);
539 brw_math(p,
540 dst,
541 func,
542 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
543 2,
544 brw_null_reg(),
545 BRW_MATH_DATA_VECTOR,
546 BRW_MATH_PRECISION_FULL);
547 }
548
549 static void emit_rcp(struct brw_wm_compile *c,
550 struct prog_instruction *inst)
551 {
552 emit_math1(c, inst, BRW_MATH_FUNCTION_INV);
553 }
554
555 static void emit_rsq(struct brw_wm_compile *c,
556 struct prog_instruction *inst)
557 {
558 emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ);
559 }
560
561 static void emit_sin(struct brw_wm_compile *c,
562 struct prog_instruction *inst)
563 {
564 emit_math1(c, inst, BRW_MATH_FUNCTION_SIN);
565 }
566
567 static void emit_cos(struct brw_wm_compile *c,
568 struct prog_instruction *inst)
569 {
570 emit_math1(c, inst, BRW_MATH_FUNCTION_COS);
571 }
572
573 static void emit_ex2(struct brw_wm_compile *c,
574 struct prog_instruction *inst)
575 {
576 emit_math1(c, inst, BRW_MATH_FUNCTION_EXP);
577 }
578
579 static void emit_lg2(struct brw_wm_compile *c,
580 struct prog_instruction *inst)
581 {
582 emit_math1(c, inst, BRW_MATH_FUNCTION_LOG);
583 }
584
585 static void emit_add(struct brw_wm_compile *c,
586 struct prog_instruction *inst)
587 {
588 struct brw_compile *p = &c->func;
589 struct brw_reg src0, src1, dst;
590 GLuint mask = inst->DstReg.WriteMask;
591 int i;
592 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
593 for (i = 0 ; i < 4; i++) {
594 if (mask & (1<<i)) {
595 dst = get_dst_reg(c, inst, i, 1);
596 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
597 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
598 brw_ADD(p, dst, src0, src1);
599 }
600 }
601 brw_set_saturate(p, 0);
602 }
603
604 static void emit_sub(struct brw_wm_compile *c,
605 struct prog_instruction *inst)
606 {
607 struct brw_compile *p = &c->func;
608 struct brw_reg src0, src1, dst;
609 GLuint mask = inst->DstReg.WriteMask;
610 int i;
611 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
612 for (i = 0 ; i < 4; i++) {
613 if (mask & (1<<i)) {
614 dst = get_dst_reg(c, inst, i, 1);
615 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
616 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
617 brw_ADD(p, dst, src0, negate(src1));
618 }
619 }
620 brw_set_saturate(p, 0);
621 }
622
623 static void emit_mul(struct brw_wm_compile *c,
624 struct prog_instruction *inst)
625 {
626 struct brw_compile *p = &c->func;
627 struct brw_reg src0, src1, dst;
628 GLuint mask = inst->DstReg.WriteMask;
629 int i;
630 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
631 for (i = 0 ; i < 4; i++) {
632 if (mask & (1<<i)) {
633 dst = get_dst_reg(c, inst, i, 1);
634 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
635 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
636 brw_MUL(p, dst, src0, src1);
637 }
638 }
639 brw_set_saturate(p, 0);
640 }
641
642 static void emit_frc(struct brw_wm_compile *c,
643 struct prog_instruction *inst)
644 {
645 struct brw_compile *p = &c->func;
646 struct brw_reg src0, dst;
647 GLuint mask = inst->DstReg.WriteMask;
648 int i;
649 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
650 for (i = 0 ; i < 4; i++) {
651 if (mask & (1<<i)) {
652 dst = get_dst_reg(c, inst, i, 1);
653 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
654 brw_FRC(p, dst, src0);
655 }
656 }
657 if (inst->SaturateMode != SATURATE_OFF)
658 brw_set_saturate(p, 0);
659 }
660
661 static void emit_flr(struct brw_wm_compile *c,
662 struct prog_instruction *inst)
663 {
664 struct brw_compile *p = &c->func;
665 struct brw_reg src0, dst;
666 GLuint mask = inst->DstReg.WriteMask;
667 int i;
668 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
669 for (i = 0 ; i < 4; i++) {
670 if (mask & (1<<i)) {
671 dst = get_dst_reg(c, inst, i, 1);
672 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
673 brw_RNDD(p, dst, src0);
674 }
675 }
676 brw_set_saturate(p, 0);
677 }
678
679 static void emit_max(struct brw_wm_compile *c,
680 struct prog_instruction *inst)
681 {
682 struct brw_compile *p = &c->func;
683 GLuint mask = inst->DstReg.WriteMask;
684 struct brw_reg src0, src1, dst;
685 int i;
686 brw_push_insn_state(p);
687 for (i = 0; i < 4; i++) {
688 if (mask & (1<<i)) {
689 dst = get_dst_reg(c, inst, i, 1);
690 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
691 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
692 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
693 brw_MOV(p, dst, src0);
694 brw_set_saturate(p, 0);
695
696 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1);
697 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
698 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
699 brw_MOV(p, dst, src1);
700 brw_set_saturate(p, 0);
701 brw_set_predicate_control_flag_value(p, 0xff);
702 }
703 }
704 brw_pop_insn_state(p);
705 }
706
707 static void emit_min(struct brw_wm_compile *c,
708 struct prog_instruction *inst)
709 {
710 struct brw_compile *p = &c->func;
711 GLuint mask = inst->DstReg.WriteMask;
712 struct brw_reg src0, src1, dst;
713 int i;
714 brw_push_insn_state(p);
715 for (i = 0; i < 4; i++) {
716 if (mask & (1<<i)) {
717 dst = get_dst_reg(c, inst, i, 1);
718 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
719 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
720 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
721 brw_MOV(p, dst, src0);
722 brw_set_saturate(p, 0);
723
724 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0);
725 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
726 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
727 brw_MOV(p, dst, src1);
728 brw_set_saturate(p, 0);
729 brw_set_predicate_control_flag_value(p, 0xff);
730 }
731 }
732 brw_pop_insn_state(p);
733 }
734
735 static void emit_pow(struct brw_wm_compile *c,
736 struct prog_instruction *inst)
737 {
738 struct brw_compile *p = &c->func;
739 struct brw_reg dst, src0, src1;
740 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
741 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
742 src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
743
744 brw_MOV(p, brw_message_reg(2), src0);
745 brw_MOV(p, brw_message_reg(3), src1);
746
747 brw_math(p,
748 dst,
749 BRW_MATH_FUNCTION_POW,
750 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
751 2,
752 brw_null_reg(),
753 BRW_MATH_DATA_VECTOR,
754 BRW_MATH_PRECISION_FULL);
755 }
756
757 static void emit_lrp(struct brw_wm_compile *c,
758 struct prog_instruction *inst)
759 {
760 struct brw_compile *p = &c->func;
761 GLuint mask = inst->DstReg.WriteMask;
762 struct brw_reg dst, tmp1, tmp2, src0, src1, src2;
763 int i;
764 for (i = 0; i < 4; i++) {
765 if (mask & (1<<i)) {
766 dst = get_dst_reg(c, inst, i, 1);
767 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
768
769 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
770
771 if (src1.nr == dst.nr) {
772 tmp1 = alloc_tmp(c);
773 brw_MOV(p, tmp1, src1);
774 } else
775 tmp1 = src1;
776
777 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
778 if (src2.nr == dst.nr) {
779 tmp2 = alloc_tmp(c);
780 brw_MOV(p, tmp2, src2);
781 } else
782 tmp2 = src2;
783
784 brw_ADD(p, dst, negate(src0), brw_imm_f(1.0));
785 brw_MUL(p, brw_null_reg(), dst, tmp2);
786 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
787 brw_MAC(p, dst, src0, tmp1);
788 brw_set_saturate(p, 0);
789 }
790 release_tmps(c);
791 }
792 }
793
794 static void emit_kil(struct brw_wm_compile *c)
795 {
796 struct brw_compile *p = &c->func;
797 struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
798 brw_push_insn_state(p);
799 brw_set_mask_control(p, BRW_MASK_DISABLE);
800 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK
801 brw_AND(p, depth, c->emit_mask_reg, depth);
802 brw_pop_insn_state(p);
803 }
804
805 static void emit_mad(struct brw_wm_compile *c,
806 struct prog_instruction *inst)
807 {
808 struct brw_compile *p = &c->func;
809 GLuint mask = inst->DstReg.WriteMask;
810 struct brw_reg dst, src0, src1, src2;
811 int i;
812
813 for (i = 0; i < 4; i++) {
814 if (mask & (1<<i)) {
815 dst = get_dst_reg(c, inst, i, 1);
816 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
817 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
818 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
819 brw_MUL(p, dst, src0, src1);
820
821 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
822 brw_ADD(p, dst, dst, src2);
823 brw_set_saturate(p, 0);
824 }
825 }
826 }
827
828 static void emit_sop(struct brw_wm_compile *c,
829 struct prog_instruction *inst, GLuint cond)
830 {
831 struct brw_compile *p = &c->func;
832 GLuint mask = inst->DstReg.WriteMask;
833 struct brw_reg dst, src0, src1;
834 int i;
835
836 brw_push_insn_state(p);
837 for (i = 0; i < 4; i++) {
838 if (mask & (1<<i)) {
839 dst = get_dst_reg(c, inst, i, 1);
840 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
841 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
842 brw_CMP(p, brw_null_reg(), cond, src0, src1);
843 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
844 brw_MOV(p, dst, brw_imm_f(0.0));
845 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
846 brw_MOV(p, dst, brw_imm_f(1.0));
847 }
848 }
849 brw_pop_insn_state(p);
850 }
851
852 static void emit_slt(struct brw_wm_compile *c,
853 struct prog_instruction *inst)
854 {
855 emit_sop(c, inst, BRW_CONDITIONAL_L);
856 }
857
858 static void emit_sle(struct brw_wm_compile *c,
859 struct prog_instruction *inst)
860 {
861 emit_sop(c, inst, BRW_CONDITIONAL_LE);
862 }
863
864 static void emit_sgt(struct brw_wm_compile *c,
865 struct prog_instruction *inst)
866 {
867 emit_sop(c, inst, BRW_CONDITIONAL_G);
868 }
869
870 static void emit_sge(struct brw_wm_compile *c,
871 struct prog_instruction *inst)
872 {
873 emit_sop(c, inst, BRW_CONDITIONAL_GE);
874 }
875
876 static void emit_seq(struct brw_wm_compile *c,
877 struct prog_instruction *inst)
878 {
879 emit_sop(c, inst, BRW_CONDITIONAL_EQ);
880 }
881
882 static void emit_sne(struct brw_wm_compile *c,
883 struct prog_instruction *inst)
884 {
885 emit_sop(c, inst, BRW_CONDITIONAL_NEQ);
886 }
887
888 static void emit_ddx(struct brw_wm_compile *c,
889 struct prog_instruction *inst)
890 {
891 struct brw_compile *p = &c->func;
892 GLuint mask = inst->DstReg.WriteMask;
893 struct brw_reg interp[4];
894 struct brw_reg dst;
895 struct brw_reg src0, w;
896 GLuint nr, i;
897 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
898 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
899 nr = src0.nr;
900 interp[0] = brw_vec1_grf(nr, 0);
901 interp[1] = brw_vec1_grf(nr, 4);
902 interp[2] = brw_vec1_grf(nr+1, 0);
903 interp[3] = brw_vec1_grf(nr+1, 4);
904 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
905 for(i = 0; i < 4; i++ ) {
906 if (mask & (1<<i)) {
907 dst = get_dst_reg(c, inst, i, 1);
908 brw_MOV(p, dst, interp[i]);
909 brw_MUL(p, dst, dst, w);
910 }
911 }
912 brw_set_saturate(p, 0);
913 }
914
915 static void emit_ddy(struct brw_wm_compile *c,
916 struct prog_instruction *inst)
917 {
918 struct brw_compile *p = &c->func;
919 GLuint mask = inst->DstReg.WriteMask;
920 struct brw_reg interp[4];
921 struct brw_reg dst;
922 struct brw_reg src0, w;
923 GLuint nr, i;
924
925 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
926 nr = src0.nr;
927 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
928 interp[0] = brw_vec1_grf(nr, 0);
929 interp[1] = brw_vec1_grf(nr, 4);
930 interp[2] = brw_vec1_grf(nr+1, 0);
931 interp[3] = brw_vec1_grf(nr+1, 4);
932 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
933 for(i = 0; i < 4; i++ ) {
934 if (mask & (1<<i)) {
935 dst = get_dst_reg(c, inst, i, 1);
936 brw_MOV(p, dst, suboffset(interp[i], 1));
937 brw_MUL(p, dst, dst, w);
938 }
939 }
940 brw_set_saturate(p, 0);
941 }
942
943 static void emit_wpos_xy(struct brw_wm_compile *c,
944 struct prog_instruction *inst)
945 {
946 struct brw_compile *p = &c->func;
947 GLuint mask = inst->DstReg.WriteMask;
948 struct brw_reg src0[2], dst[2];
949
950 dst[0] = get_dst_reg(c, inst, 0, 1);
951 dst[1] = get_dst_reg(c, inst, 1, 1);
952
953 src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1);
954 src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1);
955
956 /* Calc delta X,Y by subtracting origin in r1 from the pixel
957 * centers.
958 */
959 if (mask & WRITEMASK_X) {
960 brw_MOV(p,
961 dst[0],
962 retype(src0[0], BRW_REGISTER_TYPE_UW));
963 }
964
965 if (mask & WRITEMASK_Y) {
966 /* TODO -- window_height - Y */
967 brw_MOV(p,
968 dst[1],
969 retype(src0[1], BRW_REGISTER_TYPE_UW));
970
971 }
972 }
973
974 /* TODO
975 BIAS on SIMD8 not workind yet...
976 */
977 static void emit_txb(struct brw_wm_compile *c,
978 struct prog_instruction *inst)
979 {
980 struct brw_compile *p = &c->func;
981 struct brw_reg dst[4], src[4], payload_reg;
982 GLuint i;
983 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
984 for (i = 0; i < 4; i++)
985 dst[i] = get_dst_reg(c, inst, i, 1);
986 for (i = 0; i < 4; i++)
987 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
988
989 switch (inst->TexSrcTarget) {
990 case TEXTURE_1D_INDEX:
991 brw_MOV(p, brw_message_reg(2), src[0]);
992 brw_MOV(p, brw_message_reg(3), brw_imm_f(0));
993 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
994 break;
995 case TEXTURE_2D_INDEX:
996 case TEXTURE_RECT_INDEX:
997 brw_MOV(p, brw_message_reg(2), src[0]);
998 brw_MOV(p, brw_message_reg(3), src[1]);
999 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1000 break;
1001 default:
1002 brw_MOV(p, brw_message_reg(2), src[0]);
1003 brw_MOV(p, brw_message_reg(3), src[1]);
1004 brw_MOV(p, brw_message_reg(4), src[2]);
1005 break;
1006 }
1007 brw_MOV(p, brw_message_reg(5), src[3]);
1008 brw_MOV(p, brw_message_reg(6), brw_imm_f(0));
1009 brw_SAMPLE(p,
1010 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1011 1,
1012 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1013 inst->TexSrcUnit + 1, /* surface */
1014 inst->TexSrcUnit, /* sampler */
1015 inst->DstReg.WriteMask,
1016 BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS,
1017 4,
1018 4,
1019 0);
1020 }
1021
1022 static void emit_tex(struct brw_wm_compile *c,
1023 struct prog_instruction *inst)
1024 {
1025 struct brw_compile *p = &c->func;
1026 struct brw_reg dst[4], src[4], payload_reg;
1027 GLuint msg_len;
1028 GLuint i, nr;
1029 GLuint emit;
1030
1031 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1032 for (i = 0; i < 4; i++)
1033 dst[i] = get_dst_reg(c, inst, i, 1);
1034 for (i = 0; i < 4; i++)
1035 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1036
1037
1038 switch (inst->TexSrcTarget) {
1039 case TEXTURE_1D_INDEX:
1040 emit = WRITEMASK_X;
1041 nr = 1;
1042 break;
1043 case TEXTURE_2D_INDEX:
1044 case TEXTURE_RECT_INDEX:
1045 emit = WRITEMASK_XY;
1046 nr = 2;
1047 break;
1048 default:
1049 emit = WRITEMASK_XYZ;
1050 nr = 3;
1051 break;
1052 }
1053 msg_len = 1;
1054
1055 for (i = 0; i < nr; i++) {
1056 static const GLuint swz[4] = {0,1,2,2};
1057 if (emit & (1<<i))
1058 brw_MOV(p, brw_message_reg(msg_len+1), src[swz[i]]);
1059 else
1060 brw_MOV(p, brw_message_reg(msg_len+1), brw_imm_f(0));
1061 msg_len += 1;
1062 }
1063
1064 brw_SAMPLE(p,
1065 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1066 1,
1067 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1068 inst->TexSrcUnit + 1, /* surface */
1069 inst->TexSrcUnit, /* sampler */
1070 inst->DstReg.WriteMask,
1071 BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE,
1072 4,
1073 4,
1074 0);
1075 }
1076
1077 static void post_wm_emit( struct brw_wm_compile *c )
1078 {
1079 GLuint nr_insns = c->fp->program.Base.NumInstructions;
1080 GLuint insn, target_insn;
1081 struct prog_instruction *inst1, *inst2;
1082 struct brw_instruction *brw_inst1, *brw_inst2;
1083 int offset;
1084 for (insn = 0; insn < nr_insns; insn++) {
1085 inst1 = &c->fp->program.Base.Instructions[insn];
1086 brw_inst1 = inst1->Data;
1087 switch (inst1->Opcode) {
1088 case OPCODE_CAL:
1089 target_insn = inst1->BranchTarget;
1090 inst2 = &c->fp->program.Base.Instructions[target_insn];
1091 brw_inst2 = inst2->Data;
1092 offset = brw_inst2 - brw_inst1;
1093 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
1094 break;
1095 default:
1096 break;
1097 }
1098 }
1099 }
1100
1101 static void brw_wm_emit_glsl(struct brw_wm_compile *c)
1102
1103 {
1104 #define MAX_IFSN 32
1105 #define MAX_LOOP_DEPTH 32
1106 struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH];
1107 struct brw_instruction *inst0, *inst1;
1108 int i, if_insn = 0, loop_insn = 0;
1109 struct brw_compile *p = &c->func;
1110 struct brw_indirect stack_index = brw_indirect(0, 0);
1111
1112 brw_init_compile(&c->func);
1113 c->reg_index = 0;
1114 prealloc_reg(c);
1115 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1116 brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
1117
1118 for (i = 0; i < c->nr_fp_insns; i++) {
1119 struct prog_instruction *inst = &c->prog_instructions[i];
1120 struct prog_instruction *orig_inst;
1121
1122 if ((orig_inst = inst->Data) != 0)
1123 orig_inst->Data = current_insn(p);
1124
1125 if (inst->CondUpdate)
1126 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
1127 else
1128 brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
1129
1130 switch (inst->Opcode) {
1131 case WM_PIXELXY:
1132 emit_pixel_xy(c, inst);
1133 break;
1134 case WM_DELTAXY:
1135 emit_delta_xy(c, inst);
1136 break;
1137 case WM_PIXELW:
1138 emit_pixel_w(c, inst);
1139 break;
1140 case WM_LINTERP:
1141 emit_linterp(c, inst);
1142 break;
1143 case WM_PINTERP:
1144 emit_pinterp(c, inst);
1145 break;
1146 case WM_CINTERP:
1147 emit_cinterp(c, inst);
1148 break;
1149 case WM_WPOSXY:
1150 emit_wpos_xy(c, inst);
1151 break;
1152 case WM_FB_WRITE:
1153 emit_fb_write(c, inst);
1154 break;
1155 case OPCODE_ABS:
1156 emit_abs(c, inst);
1157 break;
1158 case OPCODE_ADD:
1159 emit_add(c, inst);
1160 break;
1161 case OPCODE_SUB:
1162 emit_sub(c, inst);
1163 break;
1164 case OPCODE_FRC:
1165 emit_frc(c, inst);
1166 break;
1167 case OPCODE_FLR:
1168 emit_flr(c, inst);
1169 break;
1170 case OPCODE_LRP:
1171 emit_lrp(c, inst);
1172 break;
1173 case OPCODE_INT:
1174 emit_mov_int(c, inst);
1175 break;
1176 case OPCODE_MOV:
1177 emit_mov(c, inst);
1178 break;
1179 case OPCODE_DP3:
1180 emit_dp3(c, inst);
1181 break;
1182 case OPCODE_DP4:
1183 emit_dp4(c, inst);
1184 break;
1185 case OPCODE_XPD:
1186 emit_xpd(c, inst);
1187 break;
1188 case OPCODE_DPH:
1189 emit_dph(c, inst);
1190 break;
1191 case OPCODE_RCP:
1192 emit_rcp(c, inst);
1193 break;
1194 case OPCODE_RSQ:
1195 emit_rsq(c, inst);
1196 break;
1197 case OPCODE_SIN:
1198 emit_sin(c, inst);
1199 break;
1200 case OPCODE_COS:
1201 emit_cos(c, inst);
1202 break;
1203 case OPCODE_EX2:
1204 emit_ex2(c, inst);
1205 break;
1206 case OPCODE_LG2:
1207 emit_lg2(c, inst);
1208 break;
1209 case OPCODE_MAX:
1210 emit_max(c, inst);
1211 break;
1212 case OPCODE_MIN:
1213 emit_min(c, inst);
1214 break;
1215 case OPCODE_DDX:
1216 emit_ddx(c, inst);
1217 break;
1218 case OPCODE_DDY:
1219 emit_ddy(c, inst);
1220 break;
1221 case OPCODE_SLT:
1222 emit_slt(c, inst);
1223 break;
1224 case OPCODE_SLE:
1225 emit_sle(c, inst);
1226 break;
1227 case OPCODE_SGT:
1228 emit_sgt(c, inst);
1229 break;
1230 case OPCODE_SGE:
1231 emit_sge(c, inst);
1232 break;
1233 case OPCODE_SEQ:
1234 emit_seq(c, inst);
1235 break;
1236 case OPCODE_SNE:
1237 emit_sne(c, inst);
1238 break;
1239 case OPCODE_MUL:
1240 emit_mul(c, inst);
1241 break;
1242 case OPCODE_POW:
1243 emit_pow(c, inst);
1244 break;
1245 case OPCODE_MAD:
1246 emit_mad(c, inst);
1247 break;
1248 case OPCODE_TEX:
1249 emit_tex(c, inst);
1250 break;
1251 case OPCODE_TXB:
1252 emit_txb(c, inst);
1253 break;
1254 case OPCODE_KIL_NV:
1255 emit_kil(c);
1256 break;
1257 case OPCODE_IF:
1258 assert(if_insn < MAX_IFSN);
1259 if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
1260 break;
1261 case OPCODE_ELSE:
1262 if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
1263 break;
1264 case OPCODE_ENDIF:
1265 assert(if_insn > 0);
1266 brw_ENDIF(p, if_inst[--if_insn]);
1267 break;
1268 case OPCODE_BGNSUB:
1269 case OPCODE_ENDSUB:
1270 break;
1271 case OPCODE_CAL:
1272 brw_push_insn_state(p);
1273 brw_set_mask_control(p, BRW_MASK_DISABLE);
1274 brw_set_access_mode(p, BRW_ALIGN_1);
1275 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
1276 brw_set_access_mode(p, BRW_ALIGN_16);
1277 brw_ADD(p, get_addr_reg(stack_index),
1278 get_addr_reg(stack_index), brw_imm_d(4));
1279 orig_inst = inst->Data;
1280 orig_inst->Data = &p->store[p->nr_insn];
1281 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1282 brw_pop_insn_state(p);
1283 break;
1284
1285 case OPCODE_RET:
1286 brw_push_insn_state(p);
1287 brw_set_mask_control(p, BRW_MASK_DISABLE);
1288 brw_ADD(p, get_addr_reg(stack_index),
1289 get_addr_reg(stack_index), brw_imm_d(-4));
1290 brw_set_access_mode(p, BRW_ALIGN_1);
1291 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
1292 brw_set_access_mode(p, BRW_ALIGN_16);
1293 brw_pop_insn_state(p);
1294
1295 break;
1296 case OPCODE_BGNLOOP:
1297 loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8);
1298 break;
1299 case OPCODE_BRK:
1300 brw_BREAK(p);
1301 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1302 break;
1303 case OPCODE_CONT:
1304 brw_CONT(p);
1305 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1306 break;
1307 case OPCODE_ENDLOOP:
1308 loop_insn--;
1309 inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]);
1310 /* patch all the BREAK instructions from
1311 last BEGINLOOP */
1312 while (inst0 > loop_inst[loop_insn]) {
1313 inst0--;
1314 if (inst0->header.opcode == BRW_OPCODE_BREAK) {
1315 inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
1316 inst0->bits3.if_else.pop_count = 0;
1317 } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
1318 inst0->bits3.if_else.jump_count = inst1 - inst0;
1319 inst0->bits3.if_else.pop_count = 0;
1320 }
1321 }
1322 break;
1323 default:
1324 _mesa_printf("unsupported IR in fragment shader %d\n",
1325 inst->Opcode);
1326 }
1327 if (inst->CondUpdate)
1328 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1329 else
1330 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1331 }
1332 post_wm_emit(c);
1333 for (i = 0; i < c->fp->program.Base.NumInstructions; i++)
1334 c->fp->program.Base.Instructions[i].Data = NULL;
1335 }
1336
1337 void brw_wm_glsl_emit(struct brw_wm_compile *c)
1338 {
1339 brw_wm_pass_fp(c);
1340 c->tmp_index = 127;
1341 brw_wm_emit_glsl(c);
1342 c->prog_data.total_grf = c->reg_index;
1343 c->prog_data.total_scratch = 0;
1344 }