src/mesa/drivers/dri/i965/brw_wm_glsl.c

   1 #include "main/macros.h"
   2 #include "program/prog_parameter.h"
   3 #include "program/prog_print.h"
   4 #include "program/prog_optimize.h"
   5 #include "brw_context.h"
   6 #include "brw_eu.h"
   7 #include "brw_wm.h"
   8
   9 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
  10                                   const struct prog_instruction *inst,
  11                                   GLuint component);
  12
  13 /**
  14  * Determine if the given fragment program uses GLSL features such
  15  * as flow conditionals, loops, subroutines.
  16  * Some GLSL shaders may use these features, others might not.
  17  */
  18 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
  19 {
  20     int i;
  21
  22     if (INTEL_DEBUG & DEBUG_GLSL_FORCE)
  23        return GL_TRUE;
  24
  25     for (i = 0; i < fp->Base.NumInstructions; i++) {
  26         const struct prog_instruction *inst = &fp->Base.Instructions[i];
  27         switch (inst->Opcode) {
  28             case OPCODE_ARL:
  29             case OPCODE_IF:
  30             case OPCODE_ENDIF:
  31             case OPCODE_CAL:
  32             case OPCODE_BRK:
  33             case OPCODE_RET:
  34             case OPCODE_BGNLOOP:
  35                 return GL_TRUE;
  36             default:
  37                 break;
  38         }
  39     }
  40     return GL_FALSE;
  41 }
  42
  43
  44
  45 static void
  46 reclaim_temps(struct brw_wm_compile *c);
  47
  48
  49 /** Mark GRF register as used. */
  50 static void
  51 prealloc_grf(struct brw_wm_compile *c, int r)
  52 {
  53    c->used_grf[r] = GL_TRUE;
  54 }
  55
  56
  57 /** Mark given GRF register as not in use. */
  58 static void
  59 release_grf(struct brw_wm_compile *c, int r)
  60 {
  61    /*assert(c->used_grf[r]);*/
  62    c->used_grf[r] = GL_FALSE;
  63    c->first_free_grf = MIN2(c->first_free_grf, r);
  64 }
  65
  66
  67 /** Return index of a free GRF, mark it as used. */
  68 static int
  69 alloc_grf(struct brw_wm_compile *c)
  70 {
  71    GLuint r;
  72    for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
  73       if (!c->used_grf[r]) {
  74          c->used_grf[r] = GL_TRUE;
  75          c->first_free_grf = r + 1;  /* a guess */
  76          return r;
  77       }
  78    }
  79
  80    /* no free temps, try to reclaim some */
  81    reclaim_temps(c);
  82    c->first_free_grf = 0;
  83
  84    /* try alloc again */
  85    for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
  86       if (!c->used_grf[r]) {
  87          c->used_grf[r] = GL_TRUE;
  88          c->first_free_grf = r + 1;  /* a guess */
  89          return r;
  90       }
  91    }
  92
  93    for (r = 0; r < BRW_WM_MAX_GRF; r++) {
  94       assert(c->used_grf[r]);
  95    }
  96
  97    /* really, no free GRF regs found */
  98    if (!c->out_of_regs) {
  99       /* print warning once per compilation */
 100       _mesa_warning(NULL, "i965: ran out of registers for fragment program");
 101       c->out_of_regs = GL_TRUE;
 102    }
 103
 104    return -1;
 105 }
 106
 107
 108 /** Return number of GRF registers used */
 109 static int
 110 num_grf_used(const struct brw_wm_compile *c)
 111 {
 112    int r;
 113    for (r = BRW_WM_MAX_GRF - 1; r >= 0; r--)
 114       if (c->used_grf[r])
 115          return r + 1;
 116    return 0;
 117 }
 118
 119
 120
 121 /**
 122  * Record the mapping of a Mesa register to a hardware register.
 123  */
 124 static void set_reg(struct brw_wm_compile *c, int file, int index,
 125         int component, struct brw_reg reg)
 126 {
 127     c->wm_regs[file][index][component].reg = reg;
 128     c->wm_regs[file][index][component].inited = GL_TRUE;
 129 }
 130
 131 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
 132 {
 133     struct brw_reg reg;
 134
 135     /* if we need to allocate another temp, grow the tmp_regs[] array */
 136     if (c->tmp_index == c->tmp_max) {
 137        int r = alloc_grf(c);
 138        if (r < 0) {
 139           /*printf("Out of temps in %s\n", __FUNCTION__);*/
 140           r = 50; /* XXX random register! */
 141        }
 142        c->tmp_regs[ c->tmp_max++ ] = r;
 143     }
 144
 145     /* form the GRF register */
 146     reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0);
 147     /*printf("alloc_temp %d\n", reg.nr);*/
 148     assert(reg.nr < BRW_WM_MAX_GRF);
 149     return reg;
 150
 151 }
 152
 153 /**
 154  * Save current temp register info.
 155  * There must be a matching call to release_tmps().
 156  */
 157 static int mark_tmps(struct brw_wm_compile *c)
 158 {
 159     return c->tmp_index;
 160 }
 161
 162 static void release_tmps(struct brw_wm_compile *c, int mark)
 163 {
 164     c->tmp_index = mark;
 165 }
 166
 167 /**
 168  * Convert Mesa src register to brw register.
 169  *
 170  * Since we're running in SOA mode each Mesa register corresponds to four
 171  * hardware registers.  We allocate the hardware registers as needed here.
 172  *
 173  * \param file  register file, one of PROGRAM_x
 174  * \param index  register number
 175  * \param component  src component (X=0, Y=1, Z=2, W=3)
 176  * \param nr  not used?!?
 177  * \param neg  negate value?
 178  * \param abs  take absolute value?
 179  */
 180 static struct brw_reg
 181 get_reg(struct brw_wm_compile *c, int file, int index, int component,
 182         int nr, GLuint neg, GLuint abs)
 183 {
 184     struct brw_reg reg;
 185     switch (file) {
 186         case PROGRAM_STATE_VAR:
 187         case PROGRAM_CONSTANT:
 188         case PROGRAM_UNIFORM:
 189             file = PROGRAM_STATE_VAR;
 190             break;
 191         case PROGRAM_UNDEFINED:
 192             return brw_null_reg();
 193         case PROGRAM_TEMPORARY:
 194         case PROGRAM_INPUT:
 195         case PROGRAM_OUTPUT:
 196         case PROGRAM_PAYLOAD:
 197             break;
 198         default:
 199             _mesa_problem(NULL, "Unexpected file in get_reg()");
 200             return brw_null_reg();
 201     }
 202
 203     assert(index < 256);
 204     assert(component < 4);
 205
 206     /* see if we've already allocated a HW register for this Mesa register */
 207     if (c->wm_regs[file][index][component].inited) {
 208        /* yes, re-use */
 209        reg = c->wm_regs[file][index][component].reg;
 210     }
 211     else {
 212         /* no, allocate new register */
 213        int grf = alloc_grf(c);
 214        /*printf("alloc grf %d for reg %d:%d.%d\n", grf, file, index, component);*/
 215        if (grf < 0) {
 216           /* totally out of temps */
 217           grf = 51; /* XXX random register! */
 218        }
 219
 220        reg = brw_vec8_grf(grf, 0);
 221        /*printf("Alloc new grf %d for %d.%d\n", reg.nr, index, component);*/
 222
 223        set_reg(c, file, index, component, reg);
 224     }
 225
 226     if (neg & (1 << component)) {
 227         reg = negate(reg);
 228     }
 229     if (abs)
 230         reg = brw_abs(reg);
 231     return reg;
 232 }
 233
 234
 235
 236 /**
 237  * This is called if we run out of GRF registers.  Examine the live intervals
 238  * of temp regs in the program and free those which won't be used again.
 239  */
 240 static void
 241 reclaim_temps(struct brw_wm_compile *c)
 242 {
 243    GLint intBegin[MAX_PROGRAM_TEMPS];
 244    GLint intEnd[MAX_PROGRAM_TEMPS];
 245    int index;
 246
 247    /*printf("Reclaim temps:\n");*/
 248
 249    _mesa_find_temp_intervals(c->prog_instructions, c->nr_fp_insns,
 250                              intBegin, intEnd);
 251
 252    for (index = 0; index < MAX_PROGRAM_TEMPS; index++) {
 253       if (intEnd[index] != -1 && intEnd[index] < c->cur_inst) {
 254          /* program temp[i] can be freed */
 255          int component;
 256          /*printf("  temp[%d] is dead\n", index);*/
 257          for (component = 0; component < 4; component++) {
 258             if (c->wm_regs[PROGRAM_TEMPORARY][index][component].inited) {
 259                int r = c->wm_regs[PROGRAM_TEMPORARY][index][component].reg.nr;
 260                release_grf(c, r);
 261                /*
 262                printf("  Reclaim temp %d, reg %d at inst %d\n",
 263                       index, r, c->cur_inst);
 264                */
 265                c->wm_regs[PROGRAM_TEMPORARY][index][component].inited = GL_FALSE;
 266             }
 267          }
 268       }
 269    }
 270 }
 271
 272
 273
 274
 275 /**
 276  * Preallocate registers.  This sets up the Mesa to hardware register
 277  * mapping for certain registers, such as constants (uniforms/state vars)
 278  * and shader inputs.
 279  */
 280 static void prealloc_reg(struct brw_wm_compile *c)
 281 {
 282     struct intel_context *intel = &c->func.brw->intel;
 283     int i, j;
 284     struct brw_reg reg;
 285     int urb_read_length = 0;
 286     GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted;
 287     GLuint reg_index = 0;
 288
 289     memset(c->used_grf, GL_FALSE, sizeof(c->used_grf));
 290     c->first_free_grf = 0;
 291
 292     for (i = 0; i < 4; i++) {
 293         if (i < (c->key.nr_payload_regs + 1) / 2)
 294             reg = brw_vec8_grf(i * 2, 0);
 295         else
 296             reg = brw_vec8_grf(0, 0);
 297         set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
 298     }
 299     set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_W, 0,
 300             brw_vec8_grf(c->key.source_w_reg, 0));
 301     reg_index += c->key.nr_payload_regs;
 302
 303     /* constants */
 304     {
 305         const GLuint nr_params = c->fp->program.Base.Parameters->NumParameters;
 306         const GLuint nr_temps = c->fp->program.Base.NumTemporaries;
 307
 308         /* use a real constant buffer, or just use a section of the GRF? */
 309         /* XXX this heuristic may need adjustment... */
 310         if ((nr_params + nr_temps) * 4 + reg_index > 80)
 311            c->fp->use_const_buffer = GL_TRUE;
 312         else
 313            c->fp->use_const_buffer = GL_FALSE;
 314         /*printf("WM use_const_buffer = %d\n", c->fp->use_const_buffer);*/
 315
 316         if (c->fp->use_const_buffer) {
 317            /* We'll use a real constant buffer and fetch constants from
 318             * it with a dataport read message.
 319             */
 320
 321            /* number of float constants in CURBE */
 322            c->prog_data.nr_params = 0;
 323         }
 324         else {
 325            const struct gl_program_parameter_list *plist =
 326               c->fp->program.Base.Parameters;
 327            int index = 0;
 328
 329            /* number of float constants in CURBE */
 330            c->prog_data.nr_params = 4 * nr_params;
 331
 332            /* loop over program constants (float[4]) */
 333            for (i = 0; i < nr_params; i++) {
 334               /* loop over XYZW channels */
 335               for (j = 0; j < 4; j++, index++) {
 336                  reg = brw_vec1_grf(reg_index + index / 8, index % 8);
 337                  /* Save pointer to parameter/constant value.
 338                   * Constants will be copied in prepare_constant_buffer()
 339                   */
 340                  c->prog_data.param[index] = &plist->ParameterValues[i][j];
 341                  set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
 342               }
 343            }
 344            /* number of constant regs used (each reg is float[8]) */
 345            c->nr_creg = 2 * ((4 * nr_params + 15) / 16);
 346            reg_index += c->nr_creg;
 347         }
 348     }
 349
 350     /* fragment shader inputs */
 351     for (i = 0; i < VERT_RESULT_MAX; i++) {
 352        int fp_input;
 353
 354        if (i >= VERT_RESULT_VAR0)
 355           fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
 356        else if (i <= VERT_RESULT_TEX7)
 357           fp_input = i;
 358        else
 359           fp_input = -1;
 360
 361        if (fp_input >= 0 && inputs & (1 << fp_input)) {
 362           urb_read_length = reg_index;
 363           reg = brw_vec8_grf(reg_index, 0);
 364           for (j = 0; j < 4; j++)
 365              set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
 366        }
 367        if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
 368           reg_index += 2;
 369        }
 370     }
 371
 372     c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
 373     c->prog_data.urb_read_length = urb_read_length;
 374     c->prog_data.curb_read_length = c->nr_creg;
 375     c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
 376     reg_index++;
 377     c->stack =  brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
 378     reg_index += 2;
 379
 380     /* mark GRF regs [0..reg_index-1] as in-use */
 381     for (i = 0; i < reg_index; i++)
 382        prealloc_grf(c, i);
 383
 384     /* Don't use GRF 126, 127.  Using them seems to lead to GPU lock-ups */
 385     prealloc_grf(c, 126);
 386     prealloc_grf(c, 127);
 387
 388     for (i = 0; i < c->nr_fp_insns; i++) {
 389         const struct prog_instruction *inst = &c->prog_instructions[i];
 390         struct brw_reg dst[4];
 391
 392         switch (inst->Opcode) {
 393         case OPCODE_TEX:
 394         case OPCODE_TXB:
 395             /* Allocate the channels of texture results contiguously,
 396              * since they are written out that way by the sampler unit.
 397              */
 398             for (j = 0; j < 4; j++) {
 399                 dst[j] = get_dst_reg(c, inst, j);
 400                 if (j != 0)
 401                     assert(dst[j].nr == dst[j - 1].nr + 1);
 402             }
 403             break;
 404         default:
 405             break;
 406         }
 407     }
 408
 409     for (i = 0; i < c->nr_fp_insns; i++) {
 410         const struct prog_instruction *inst = &c->prog_instructions[i];
 411
 412         switch (inst->Opcode) {
 413         case WM_DELTAXY:
 414             /* Allocate WM_DELTAXY destination on G45/GM45 to an
 415              * even-numbered GRF if possible so that we can use the PLN
 416              * instruction.
 417              */
 418             if (inst->DstReg.WriteMask == WRITEMASK_XY &&
 419                 !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
 420                 !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
 421                 (IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
 422                 int grf;
 423
 424                 for (grf = c->first_free_grf & ~1;
 425                      grf < BRW_WM_MAX_GRF;
 426                      grf += 2)
 427                 {
 428                     if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
 429                         c->used_grf[grf] = GL_TRUE;
 430                         c->used_grf[grf + 1] = GL_TRUE;
 431                         c->first_free_grf = grf + 2;  /* a guess */
 432
 433                         set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
 434                                 brw_vec8_grf(grf, 0));
 435                         set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
 436                                 brw_vec8_grf(grf + 1, 0));
 437                         break;
 438                     }
 439                 }
 440             }
 441         default:
 442             break;
 443         }
 444     }
 445
 446     /* An instruction may reference up to three constants.
 447      * They'll be found in these registers.
 448      * XXX alloc these on demand!
 449      */
 450     if (c->fp->use_const_buffer) {
 451        for (i = 0; i < 3; i++) {
 452           c->current_const[i].index = -1;
 453           c->current_const[i].reg = brw_vec8_grf(alloc_grf(c), 0);
 454        }
 455     }
 456 #if 0
 457     printf("USE CONST BUFFER? %d\n", c->fp->use_const_buffer);
 458     printf("AFTER PRE_ALLOC, reg_index = %d\n", reg_index);
 459 #endif
 460 }
 461
 462
 463 /**
 464  * Check if any of the instruction's src registers are constants, uniforms,
 465  * or statevars.  If so, fetch any constants that we don't already have in
 466  * the three GRF slots.
 467  */
 468 static void fetch_constants(struct brw_wm_compile *c,
 469                             const struct prog_instruction *inst)
 470 {
 471    struct brw_compile *p = &c->func;
 472    GLuint i;
 473
 474    /* loop over instruction src regs */
 475    for (i = 0; i < 3; i++) {
 476       const struct prog_src_register *src = &inst->SrcReg[i];
 477       if (src->File == PROGRAM_STATE_VAR ||
 478           src->File == PROGRAM_CONSTANT ||
 479           src->File == PROGRAM_UNIFORM) {
 480          c->current_const[i].index = src->Index;
 481
 482 #if 0
 483          printf("  fetch const[%d] for arg %d into reg %d\n",
 484                 src->Index, i, c->current_const[i].reg.nr);
 485 #endif
 486
 487          /* need to fetch the constant now */
 488          brw_dp_READ_4(p,
 489                        c->current_const[i].reg,  /* writeback dest */
 490                        src->RelAddr,             /* relative indexing? */
 491                        16 * src->Index,          /* byte offset */
 492                        SURF_INDEX_FRAG_CONST_BUFFER/* binding table index */
 493                        );
 494       }
 495    }
 496 }
 497
 498
 499 /**
 500  * Convert Mesa dst register to brw register.
 501  */
 502 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
 503                                   const struct prog_instruction *inst,
 504                                   GLuint component)
 505 {
 506     const int nr = 1;
 507     return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
 508             0, 0);
 509 }
 510
 511
 512 static struct brw_reg
 513 get_src_reg_const(struct brw_wm_compile *c,
 514                   const struct prog_instruction *inst,
 515                   GLuint srcRegIndex, GLuint component)
 516 {
 517    /* We should have already fetched the constant from the constant
 518     * buffer in fetch_constants().  Now we just have to return a
 519     * register description that extracts the needed component and
 520     * smears it across all eight vector components.
 521     */
 522    const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
 523    struct brw_reg const_reg;
 524
 525    assert(component < 4);
 526    assert(srcRegIndex < 3);
 527    assert(c->current_const[srcRegIndex].index != -1);
 528    const_reg = c->current_const[srcRegIndex].reg;
 529
 530    /* extract desired float from the const_reg, and smear */
 531    const_reg = stride(const_reg, 0, 1, 0);
 532    const_reg.subnr = component * 4;
 533
 534    if (src->Negate & (1 << component))
 535       const_reg = negate(const_reg);
 536    if (src->Abs)
 537       const_reg = brw_abs(const_reg);
 538
 539 #if 0
 540    printf("  form const[%d].%d for arg %d, reg %d\n",
 541           c->current_const[srcRegIndex].index,
 542           component,
 543           srcRegIndex,
 544           const_reg.nr);
 545 #endif
 546
 547    return const_reg;
 548 }
 549
 550
 551 /**
 552  * Convert Mesa src register to brw register.
 553  */
 554 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
 555                                   const struct prog_instruction *inst,
 556                                   GLuint srcRegIndex, GLuint channel)
 557 {
 558     const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
 559     const GLuint nr = 1;
 560     const GLuint component = GET_SWZ(src->Swizzle, channel);
 561
 562     /* Only one immediate value can be used per native opcode, and it
 563      * has be in the src1 slot, so not all Mesa instructions will get
 564      * to take advantage of immediate constants.
 565      */
 566     if (brw_wm_arg_can_be_immediate(inst->Opcode, srcRegIndex)) {
 567        const struct gl_program_parameter_list *params;
 568
 569        params = c->fp->program.Base.Parameters;
 570
 571        /* Extended swizzle terms */
 572        if (component == SWIZZLE_ZERO) {
 573           return brw_imm_f(0.0F);
 574        } else if (component == SWIZZLE_ONE) {
 575           if (src->Negate)
 576              return brw_imm_f(-1.0F);
 577           else
 578              return brw_imm_f(1.0F);
 579        }
 580
 581        if (src->File == PROGRAM_CONSTANT) {
 582           float f = params->ParameterValues[src->Index][component];
 583
 584           if (src->Abs)
 585              f = fabs(f);
 586           if (src->Negate)
 587              f = -f;
 588
 589           return brw_imm_f(f);
 590        }
 591     }
 592
 593     if (c->fp->use_const_buffer &&
 594         (src->File == PROGRAM_STATE_VAR ||
 595          src->File == PROGRAM_CONSTANT ||
 596          src->File == PROGRAM_UNIFORM)) {
 597        return get_src_reg_const(c, inst, srcRegIndex, component);
 598     }
 599     else {
 600        /* other type of source register */
 601        return get_reg(c, src->File, src->Index, component, nr,
 602                       src->Negate, src->Abs);
 603     }
 604 }
 605
 606 static void emit_arl(struct brw_wm_compile *c,
 607                      const struct prog_instruction *inst)
 608 {
 609     struct brw_compile *p = &c->func;
 610     struct brw_reg src0, addr_reg;
 611     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 612     addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 613                            BRW_ARF_ADDRESS, 0);
 614     src0 = get_src_reg(c, inst, 0, 0); /* channel 0 */
 615     brw_MOV(p, addr_reg, src0);
 616     brw_set_saturate(p, 0);
 617 }
 618
 619 static INLINE struct brw_reg high_words( struct brw_reg reg )
 620 {
 621     return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_W ), 1 ),
 622                    0, 8, 2 );
 623 }
 624
 625 static INLINE struct brw_reg low_words( struct brw_reg reg )
 626 {
 627     return stride( retype( reg, BRW_REGISTER_TYPE_W ), 0, 8, 2 );
 628 }
 629
 630 static INLINE struct brw_reg even_bytes( struct brw_reg reg )
 631 {
 632     return stride( retype( reg, BRW_REGISTER_TYPE_B ), 0, 16, 2 );
 633 }
 634
 635 static INLINE struct brw_reg odd_bytes( struct brw_reg reg )
 636 {
 637     return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_B ), 1 ),
 638                    0, 16, 2 );
 639 }
 640
 641 /**
 642  * Resolve subroutine calls after code emit is done.
 643  */
 644 static void post_wm_emit( struct brw_wm_compile *c )
 645 {
 646     brw_resolve_cals(&c->func);
 647 }
 648
 649 static void
 650 get_argument_regs(struct brw_wm_compile *c,
 651                   const struct prog_instruction *inst,
 652                   int index,
 653                   struct brw_reg *dst,
 654                   struct brw_reg *regs,
 655                   int mask)
 656 {
 657     struct brw_compile *p = &c->func;
 658     int i, j;
 659
 660     for (i = 0; i < 4; i++) {
 661         if (mask & (1 << i)) {
 662             regs[i] = get_src_reg(c, inst, index, i);
 663
 664             /* Unalias destination registers from our sources. */
 665             if (regs[i].file == BRW_GENERAL_REGISTER_FILE) {
 666                for (j = 0; j < 4; j++) {
 667                    if (memcmp(&regs[i], &dst[j], sizeof(regs[0])) == 0) {
 668                        struct brw_reg tmp = alloc_tmp(c);
 669                        brw_MOV(p, tmp, regs[i]);
 670                        regs[i] = tmp;
 671                        break;
 672                    }
 673                }
 674             }
 675         }
 676     }
 677 }
 678
 679 static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 680 {
 681    struct intel_context *intel = &brw->intel;
 682 #define MAX_IF_DEPTH 32
 683 #define MAX_LOOP_DEPTH 32
 684     struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH];
 685     int if_depth_in_loop[MAX_LOOP_DEPTH];
 686     GLuint i, if_depth = 0, loop_depth = 0;
 687     struct brw_compile *p = &c->func;
 688     struct brw_indirect stack_index = brw_indirect(0, 0);
 689
 690     c->out_of_regs = GL_FALSE;
 691
 692     if_depth_in_loop[loop_depth] = 0;
 693
 694     prealloc_reg(c);
 695     brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 696     brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
 697
 698     for (i = 0; i < c->nr_fp_insns; i++) {
 699         const struct prog_instruction *inst = &c->prog_instructions[i];
 700         int dst_flags;
 701         struct brw_reg args[3][4], dst[4];
 702         int j;
 703         int mark = mark_tmps( c );
 704
 705         c->cur_inst = i;
 706
 707 #if 0
 708         printf("Inst %d: ", i);
 709         _mesa_print_instruction(inst);
 710 #endif
 711
 712         /* fetch any constants that this instruction needs */
 713         if (c->fp->use_const_buffer)
 714            fetch_constants(c, inst);
 715
 716         if (inst->Opcode != OPCODE_ARL) {
 717            for (j = 0; j < 4; j++) {
 718               if (inst->DstReg.WriteMask & (1 << j))
 719                  dst[j] = get_dst_reg(c, inst, j);
 720               else
 721                  dst[j] = brw_null_reg();
 722            }
 723         }
 724         for (j = 0; j < brw_wm_nr_args(inst->Opcode); j++)
 725             get_argument_regs(c, inst, j, dst, args[j], WRITEMASK_XYZW);
 726
 727         dst_flags = inst->DstReg.WriteMask;
 728         if (inst->SaturateMode == SATURATE_ZERO_ONE)
 729             dst_flags |= SATURATE;
 730
 731         if (inst->CondUpdate)
 732             brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 733         else
 734             brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
 735
 736         switch (inst->Opcode) {
 737             case WM_PIXELXY:
 738                 emit_pixel_xy(c, dst, dst_flags);
 739                 break;
 740             case WM_DELTAXY:
 741                 emit_delta_xy(p, dst, dst_flags, args[0]);
 742                 break;
 743             case WM_PIXELW:
 744                 emit_pixel_w(c, dst, dst_flags, args[0], args[1]);
 745                 break;
 746             case WM_LINTERP:
 747                 emit_linterp(p, dst, dst_flags, args[0], args[1]);
 748                 break;
 749             case WM_PINTERP:
 750                 emit_pinterp(p, dst, dst_flags, args[0], args[1], args[2]);
 751                 break;
 752             case WM_CINTERP:
 753                 emit_cinterp(p, dst, dst_flags, args[0]);
 754                 break;
 755             case WM_WPOSXY:
 756                 emit_wpos_xy(c, dst, dst_flags, args[0]);
 757                 break;
 758             case WM_FB_WRITE:
 759                 emit_fb_write(c, args[0], args[1], args[2],
 760                               INST_AUX_GET_TARGET(inst->Aux),
 761                               inst->Aux & INST_AUX_EOT);
 762                 break;
 763             case WM_FRONTFACING:
 764                 emit_frontfacing(p, dst, dst_flags);
 765                 break;
 766             case OPCODE_ADD:
 767                 emit_alu2(p, brw_ADD, dst, dst_flags, args[0], args[1]);
 768                 break;
 769             case OPCODE_ARL:
 770                 emit_arl(c, inst);
 771                 break;
 772             case OPCODE_FRC:
 773                 emit_alu1(p, brw_FRC, dst, dst_flags, args[0]);
 774                 break;
 775             case OPCODE_FLR:
 776                 emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
 777                 break;
 778             case OPCODE_LRP:
 779                 emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]);
 780                 break;
 781             case OPCODE_TRUNC:
 782                 emit_alu1(p, brw_RNDZ, dst, dst_flags, args[0]);
 783                 break;
 784             case OPCODE_MOV:
 785             case OPCODE_SWZ:
 786                 emit_alu1(p, brw_MOV, dst, dst_flags, args[0]);
 787                 break;
 788             case OPCODE_DP2:
 789                 emit_dp2(p, dst, dst_flags, args[0], args[1]);
 790                 break;
 791             case OPCODE_DP3:
 792                 emit_dp3(p, dst, dst_flags, args[0], args[1]);
 793                 break;
 794             case OPCODE_DP4:
 795                 emit_dp4(p, dst, dst_flags, args[0], args[1]);
 796                 break;
 797             case OPCODE_XPD:
 798                 emit_xpd(p, dst, dst_flags, args[0], args[1]);
 799                 break;
 800             case OPCODE_DPH:
 801                 emit_dph(p, dst, dst_flags, args[0], args[1]);
 802                 break;
 803             case OPCODE_RCP:
 804                 emit_math1(c, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]);
 805                 break;
 806             case OPCODE_RSQ:
 807                 emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]);
 808                 break;
 809             case OPCODE_SIN:
 810                 emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]);
 811                 break;
 812             case OPCODE_COS:
 813                 emit_math1(c, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]);
 814                 break;
 815             case OPCODE_EX2:
 816                 emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]);
 817                 break;
 818             case OPCODE_LG2:
 819                 emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
 820                 break;
 821             case OPCODE_CMP:
 822                 emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]);
 823                 break;
 824             case OPCODE_MIN:
 825                 emit_min(p, dst, dst_flags, args[0], args[1]);
 826                 break;
 827             case OPCODE_MAX:
 828                 emit_max(p, dst, dst_flags, args[0], args[1]);
 829                 break;
 830             case OPCODE_DDX:
 831             case OPCODE_DDY:
 832                 emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX),
 833                           args[0]);
 834                 break;
 835             case OPCODE_SLT:
 836                 emit_sop(p, dst, dst_flags,
 837                          BRW_CONDITIONAL_L, args[0], args[1]);
 838                 break;
 839             case OPCODE_SLE:
 840                 emit_sop(p, dst, dst_flags,
 841                          BRW_CONDITIONAL_LE, args[0], args[1]);
 842                 break;
 843             case OPCODE_SGT:
 844                 emit_sop(p, dst, dst_flags,
 845                          BRW_CONDITIONAL_G, args[0], args[1]);
 846                 break;
 847             case OPCODE_SGE:
 848                 emit_sop(p, dst, dst_flags,
 849                          BRW_CONDITIONAL_GE, args[0], args[1]);
 850                 break;
 851             case OPCODE_SEQ:
 852                 emit_sop(p, dst, dst_flags,
 853                          BRW_CONDITIONAL_EQ, args[0], args[1]);
 854                 break;
 855             case OPCODE_SNE:
 856                 emit_sop(p, dst, dst_flags,
 857                          BRW_CONDITIONAL_NEQ, args[0], args[1]);
 858                 break;
 859             case OPCODE_SSG:
 860                 emit_sign(p, dst, dst_flags, args[0]);
 861                 break;
 862             case OPCODE_MUL:
 863                 emit_alu2(p, brw_MUL, dst, dst_flags, args[0], args[1]);
 864                 break;
 865             case OPCODE_POW:
 866                 emit_math2(c, BRW_MATH_FUNCTION_POW,
 867                            dst, dst_flags, args[0], args[1]);
 868                 break;
 869             case OPCODE_MAD:
 870                 emit_mad(p, dst, dst_flags, args[0], args[1], args[2]);
 871                 break;
 872             case OPCODE_TEX:
 873                 emit_tex(c, dst, dst_flags, args[0],
 874                          get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
 875                                  0, 1, 0, 0),
 876                          inst->TexSrcTarget,
 877                          inst->TexSrcUnit,
 878                          (c->key.shadowtex_mask & (1 << inst->TexSrcUnit)) != 0);
 879                 break;
 880             case OPCODE_TXB:
 881                 emit_txb(c, dst, dst_flags, args[0],
 882                          get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
 883                                  0, 1, 0, 0),
 884                          inst->TexSrcTarget,
 885                          c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]);
 886                 break;
 887             case OPCODE_KIL_NV:
 888                 emit_kil_nv(c);
 889                 break;
 890             case OPCODE_IF:
 891                 assert(if_depth < MAX_IF_DEPTH);
 892                 if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8);
 893                 if_depth_in_loop[loop_depth]++;
 894                 break;
 895             case OPCODE_ELSE:
 896                 assert(if_depth > 0);
 897                 if_inst[if_depth-1]  = brw_ELSE(p, if_inst[if_depth-1]);
 898                 break;
 899             case OPCODE_ENDIF:
 900                 assert(if_depth > 0);
 901                 brw_ENDIF(p, if_inst[--if_depth]);
 902                 if_depth_in_loop[loop_depth]--;
 903                 break;
 904             case OPCODE_BGNSUB:
 905                 brw_save_label(p, inst->Comment, p->nr_insn);
 906                 break;
 907             case OPCODE_ENDSUB:
 908                 /* no-op */
 909                 break;
 910             case OPCODE_CAL:
 911                 brw_push_insn_state(p);
 912                 brw_set_mask_control(p, BRW_MASK_DISABLE);
 913                 brw_set_access_mode(p, BRW_ALIGN_1);
 914                 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
 915                 brw_set_access_mode(p, BRW_ALIGN_16);
 916                 brw_ADD(p, get_addr_reg(stack_index),
 917                          get_addr_reg(stack_index), brw_imm_d(4));
 918                 brw_save_call(&c->func, inst->Comment, p->nr_insn);
 919                 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
 920                 brw_pop_insn_state(p);
 921                 break;
 922
 923             case OPCODE_RET:
 924                 brw_push_insn_state(p);
 925                 brw_set_mask_control(p, BRW_MASK_DISABLE);
 926                 brw_ADD(p, get_addr_reg(stack_index),
 927                         get_addr_reg(stack_index), brw_imm_d(-4));
 928                 brw_set_access_mode(p, BRW_ALIGN_1);
 929                 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
 930                 brw_set_access_mode(p, BRW_ALIGN_16);
 931                 brw_pop_insn_state(p);
 932
 933                 break;
 934             case OPCODE_BGNLOOP:
 935                 /* XXX may need to invalidate the current_constant regs */
 936                 loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8);
 937                 if_depth_in_loop[loop_depth] = 0;
 938                 break;
 939             case OPCODE_BRK:
 940                 brw_BREAK(p, if_depth_in_loop[loop_depth]);
 941                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 942                 break;
 943             case OPCODE_CONT:
 944                 brw_CONT(p, if_depth_in_loop[loop_depth]);
 945                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 946                 break;
 947             case OPCODE_ENDLOOP:
 948                {
 949                   struct brw_instruction *inst0, *inst1;
 950                   GLuint br = 1;
 951
 952                   if (intel->gen == 5)
 953                      br = 2;
 954
 955                   assert(loop_depth > 0);
 956                   loop_depth--;
 957                   inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
 958                   /* patch all the BREAK/CONT instructions from last BGNLOOP */
 959                   while (inst0 > loop_inst[loop_depth]) {
 960                      inst0--;
 961                      if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 962                          inst0->bits3.if_else.jump_count == 0) {
 963                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 964                      }
 965                      else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 966                               inst0->bits3.if_else.jump_count == 0) {
 967                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 968                      }
 969                   }
 970                }
 971                break;
 972             default:
 973                 printf("unsupported opcode %d (%s) in fragment shader\n",
 974                        inst->Opcode, inst->Opcode < MAX_OPCODE ?
 975                        _mesa_opcode_string(inst->Opcode) : "unknown");
 976         }
 977
 978         /* Release temporaries containing any unaliased source regs. */
 979         release_tmps( c, mark );
 980
 981         if (inst->CondUpdate)
 982             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 983         else
 984             brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 985     }
 986     post_wm_emit(c);
 987
 988     if (INTEL_DEBUG & DEBUG_WM) {
 989       printf("wm-native:\n");
 990       for (i = 0; i < p->nr_insn; i++)
 991          brw_disasm(stdout, &p->store[i], intel->gen);
 992       printf("\n");
 993     }
 994 }
 995
 996 /**
 997  * Do GPU code generation for shaders that use GLSL features such as
 998  * flow control.  Other shaders will be compiled with the
 999  */
1000 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
1001 {
1002     if (INTEL_DEBUG & DEBUG_WM) {
1003         printf("brw_wm_glsl_emit:\n");
1004     }
1005
1006     /* initial instruction translation/simplification */
1007     brw_wm_pass_fp(c);
1008
1009     /* actual code generation */
1010     brw_wm_emit_glsl(brw, c);
1011
1012     if (INTEL_DEBUG & DEBUG_WM) {
1013         brw_wm_print_program(c, "brw_wm_glsl_emit done");
1014     }
1015
1016     c->prog_data.total_grf = num_grf_used(c);
1017     c->prog_data.total_scratch = 0;
1018 }