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[i965] fix wpos height 1 pixel higher
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_glsl.c
1 #include "macros.h"
2 #include "shader/prog_parameter.h"
3 #include "brw_context.h"
4 #include "brw_eu.h"
5 #include "brw_wm.h"
6
7 /* Only guess, need a flag in gl_fragment_program later */
8 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
9 {
10 int i;
11 for (i = 0; i < fp->Base.NumInstructions; i++) {
12 struct prog_instruction *inst = &fp->Base.Instructions[i];
13 switch (inst->Opcode) {
14 case OPCODE_IF:
15 case OPCODE_INT:
16 case OPCODE_ENDIF:
17 case OPCODE_CAL:
18 case OPCODE_BRK:
19 case OPCODE_RET:
20 case OPCODE_DDX:
21 case OPCODE_DDY:
22 case OPCODE_BGNLOOP:
23 return GL_TRUE;
24 default:
25 break;
26 }
27 }
28 return GL_FALSE;
29 }
30
31 static void set_reg(struct brw_wm_compile *c, int file, int index,
32 int component, struct brw_reg reg)
33 {
34 c->wm_regs[file][index][component].reg = reg;
35 c->wm_regs[file][index][component].inited = GL_TRUE;
36 }
37
38 static int get_scalar_dst_index(struct prog_instruction *inst)
39 {
40 int i;
41 for (i = 0; i < 4; i++)
42 if (inst->DstReg.WriteMask & (1<<i))
43 break;
44 return i;
45 }
46
47 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
48 {
49 struct brw_reg reg;
50 reg = brw_vec8_grf(c->tmp_index--, 0);
51 return reg;
52 }
53
54 static void release_tmps(struct brw_wm_compile *c)
55 {
56 c->tmp_index = 127;
57 }
58
59 static struct brw_reg
60 get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs)
61 {
62 struct brw_reg reg;
63 switch (file) {
64 case PROGRAM_STATE_VAR:
65 case PROGRAM_CONSTANT:
66 case PROGRAM_UNIFORM:
67 file = PROGRAM_STATE_VAR;
68 break;
69 case PROGRAM_UNDEFINED:
70 return brw_null_reg();
71 default:
72 break;
73 }
74
75 if(c->wm_regs[file][index][component].inited)
76 reg = c->wm_regs[file][index][component].reg;
77 else
78 reg = brw_vec8_grf(c->reg_index, 0);
79
80 if(!c->wm_regs[file][index][component].inited) {
81 set_reg(c, file, index, component, reg);
82 c->reg_index++;
83 }
84
85 if (neg & (1<< component)) {
86 reg = negate(reg);
87 }
88 if (abs)
89 reg = brw_abs(reg);
90 return reg;
91 }
92
93 static void prealloc_reg(struct brw_wm_compile *c)
94 {
95 int i, j;
96 struct brw_reg reg;
97 int nr_interp_regs = 0;
98 GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
99
100 for (i = 0; i < 4; i++) {
101 reg = (i < c->key.nr_depth_regs)
102 ? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0);
103 set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
104 }
105 c->reg_index += 2*c->key.nr_depth_regs;
106 {
107 int nr_params = c->fp->program.Base.Parameters->NumParameters;
108 struct gl_program_parameter_list *plist =
109 c->fp->program.Base.Parameters;
110 int index = 0;
111 c->prog_data.nr_params = 4*nr_params;
112 for (i = 0; i < nr_params; i++) {
113 for (j = 0; j < 4; j++, index++) {
114 reg = brw_vec1_grf(c->reg_index + index/8,
115 index%8);
116 c->prog_data.param[index] =
117 &plist->ParameterValues[i][j];
118 set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
119 }
120 }
121 c->nr_creg = 2*((4*nr_params+15)/16);
122 c->reg_index += c->nr_creg;
123 }
124 for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
125 if (inputs & (1<<i)) {
126 nr_interp_regs++;
127 reg = brw_vec8_grf(c->reg_index, 0);
128 for (j = 0; j < 4; j++)
129 set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
130 c->reg_index += 2;
131
132 }
133 }
134 c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
135 c->prog_data.urb_read_length = nr_interp_regs * 2;
136 c->prog_data.curb_read_length = c->nr_creg;
137 c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
138 c->reg_index++;
139 c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
140 c->reg_index += 2;
141 }
142
143 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
144 struct prog_instruction *inst, int component, int nr)
145 {
146 return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
147 0, 0);
148 }
149
150 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
151 struct prog_src_register *src, int index, int nr)
152 {
153 int component = GET_SWZ(src->Swizzle, index);
154 return get_reg(c, src->File, src->Index, component, nr,
155 src->NegateBase, src->Abs);
156 }
157
158 static void emit_abs( struct brw_wm_compile *c,
159 struct prog_instruction *inst)
160 {
161 int i;
162 struct brw_compile *p = &c->func;
163 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
164 for (i = 0; i < 4; i++) {
165 if (inst->DstReg.WriteMask & (1<<i)) {
166 struct brw_reg src, dst;
167 dst = get_dst_reg(c, inst, i, 1);
168 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
169 brw_MOV(p, dst, brw_abs(src));
170 }
171 }
172 brw_set_saturate(p, 0);
173 }
174
175 static void emit_int( struct brw_wm_compile *c,
176 struct prog_instruction *inst)
177 {
178 int i;
179 struct brw_compile *p = &c->func;
180 GLuint mask = inst->DstReg.WriteMask;
181 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
182 for (i = 0; i < 4; i++) {
183 if (mask & (1<<i)) {
184 struct brw_reg src, dst;
185 dst = get_dst_reg(c, inst, i, 1) ;
186 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
187 brw_RNDD(p, dst, src);
188 }
189 }
190 brw_set_saturate(p, 0);
191 }
192
193 static void emit_mov( struct brw_wm_compile *c,
194 struct prog_instruction *inst)
195 {
196 int i;
197 struct brw_compile *p = &c->func;
198 GLuint mask = inst->DstReg.WriteMask;
199 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
200 for (i = 0; i < 4; i++) {
201 if (mask & (1<<i)) {
202 struct brw_reg src, dst;
203 dst = get_dst_reg(c, inst, i, 1);
204 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
205 brw_MOV(p, dst, src);
206 }
207 }
208 brw_set_saturate(p, 0);
209 }
210
211 static void emit_pixel_xy(struct brw_wm_compile *c,
212 struct prog_instruction *inst)
213 {
214 struct brw_reg r1 = brw_vec1_grf(1, 0);
215 struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW);
216
217 struct brw_reg dst0, dst1;
218 struct brw_compile *p = &c->func;
219 GLuint mask = inst->DstReg.WriteMask;
220
221 dst0 = get_dst_reg(c, inst, 0, 1);
222 dst1 = get_dst_reg(c, inst, 1, 1);
223 /* Calculate pixel centers by adding 1 or 0 to each of the
224 * micro-tile coordinates passed in r1.
225 */
226 if (mask & WRITEMASK_X) {
227 brw_ADD(p,
228 vec8(retype(dst0, BRW_REGISTER_TYPE_UW)),
229 stride(suboffset(r1_uw, 4), 2, 4, 0),
230 brw_imm_v(0x10101010));
231 }
232
233 if (mask & WRITEMASK_Y) {
234 brw_ADD(p,
235 vec8(retype(dst1, BRW_REGISTER_TYPE_UW)),
236 stride(suboffset(r1_uw, 5), 2, 4, 0),
237 brw_imm_v(0x11001100));
238 }
239
240 }
241
242 static void emit_delta_xy(struct brw_wm_compile *c,
243 struct prog_instruction *inst)
244 {
245 struct brw_reg r1 = brw_vec1_grf(1, 0);
246 struct brw_reg dst0, dst1, src0, src1;
247 struct brw_compile *p = &c->func;
248 GLuint mask = inst->DstReg.WriteMask;
249
250 dst0 = get_dst_reg(c, inst, 0, 1);
251 dst1 = get_dst_reg(c, inst, 1, 1);
252 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
253 src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1);
254 /* Calc delta X,Y by subtracting origin in r1 from the pixel
255 * centers.
256 */
257 if (mask & WRITEMASK_X) {
258 brw_ADD(p,
259 dst0,
260 retype(src0, BRW_REGISTER_TYPE_UW),
261 negate(r1));
262 }
263
264 if (mask & WRITEMASK_Y) {
265 brw_ADD(p,
266 dst1,
267 retype(src1, BRW_REGISTER_TYPE_UW),
268 negate(suboffset(r1,1)));
269
270 }
271
272 }
273
274
275 static void fire_fb_write( struct brw_wm_compile *c,
276 GLuint base_reg,
277 GLuint nr,
278 GLuint target,
279 GLuint eot)
280 {
281 struct brw_compile *p = &c->func;
282 /* Pass through control information:
283 */
284 /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */
285 {
286 brw_push_insn_state(p);
287 brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */
288 brw_MOV(p,
289 brw_message_reg(base_reg + 1),
290 brw_vec8_grf(1, 0));
291 brw_pop_insn_state(p);
292 }
293 /* Send framebuffer write message: */
294 brw_fb_WRITE(p,
295 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
296 base_reg,
297 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
298 target,
299 nr,
300 0,
301 eot);
302 }
303
304 static void emit_fb_write(struct brw_wm_compile *c,
305 struct prog_instruction *inst)
306 {
307 struct brw_compile *p = &c->func;
308 int nr = 2;
309 int channel;
310 GLuint target, eot;
311 struct brw_reg src0;
312
313 /* Reserve a space for AA - may not be needed:
314 */
315 if (c->key.aa_dest_stencil_reg)
316 nr += 1;
317 {
318 brw_push_insn_state(p);
319 for (channel = 0; channel < 4; channel++) {
320 src0 = get_src_reg(c, &inst->SrcReg[0], channel, 1);
321 /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */
322 /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */
323 brw_MOV(p, brw_message_reg(nr + channel), src0);
324 }
325 /* skip over the regs populated above: */
326 nr += 8;
327 brw_pop_insn_state(p);
328 }
329
330 if (c->key.source_depth_to_render_target)
331 {
332 if (c->key.computes_depth) {
333 src0 = get_src_reg(c, &inst->SrcReg[2], 2, 1);
334 brw_MOV(p, brw_message_reg(nr), src0);
335 } else {
336 src0 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
337 brw_MOV(p, brw_message_reg(nr), src0);
338 }
339
340 nr += 2;
341 }
342 target = inst->Sampler >> 1;
343 eot = inst->Sampler & 1;
344 fire_fb_write(c, 0, nr, target, eot);
345 }
346
347 static void emit_pixel_w( struct brw_wm_compile *c,
348 struct prog_instruction *inst)
349 {
350 struct brw_compile *p = &c->func;
351 GLuint mask = inst->DstReg.WriteMask;
352 if (mask & WRITEMASK_W) {
353 struct brw_reg dst, src0, delta0, delta1;
354 struct brw_reg interp3;
355
356 dst = get_dst_reg(c, inst, 3, 1);
357 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
358 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
359 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
360
361 interp3 = brw_vec1_grf(src0.nr+1, 4);
362 /* Calc 1/w - just linterp wpos[3] optimized by putting the
363 * result straight into a message reg.
364 */
365 brw_LINE(p, brw_null_reg(), interp3, delta0);
366 brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1);
367
368 /* Calc w */
369 brw_math_16( p, dst,
370 BRW_MATH_FUNCTION_INV,
371 BRW_MATH_SATURATE_NONE,
372 2, brw_null_reg(),
373 BRW_MATH_PRECISION_FULL);
374 }
375 }
376
377 static void emit_linterp(struct brw_wm_compile *c,
378 struct prog_instruction *inst)
379 {
380 struct brw_compile *p = &c->func;
381 GLuint mask = inst->DstReg.WriteMask;
382 struct brw_reg interp[4];
383 struct brw_reg dst, delta0, delta1;
384 struct brw_reg src0;
385
386 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
387 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
388 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
389 GLuint nr = src0.nr;
390 int i;
391
392 interp[0] = brw_vec1_grf(nr, 0);
393 interp[1] = brw_vec1_grf(nr, 4);
394 interp[2] = brw_vec1_grf(nr+1, 0);
395 interp[3] = brw_vec1_grf(nr+1, 4);
396
397 for(i = 0; i < 4; i++ ) {
398 if (mask & (1<<i)) {
399 dst = get_dst_reg(c, inst, i, 1);
400 brw_LINE(p, brw_null_reg(), interp[i], delta0);
401 brw_MAC(p, dst, suboffset(interp[i],1), delta1);
402 }
403 }
404 }
405
406 static void emit_cinterp(struct brw_wm_compile *c,
407 struct prog_instruction *inst)
408 {
409 struct brw_compile *p = &c->func;
410 GLuint mask = inst->DstReg.WriteMask;
411
412 struct brw_reg interp[4];
413 struct brw_reg dst, src0;
414
415 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
416 GLuint nr = src0.nr;
417 int i;
418
419 interp[0] = brw_vec1_grf(nr, 0);
420 interp[1] = brw_vec1_grf(nr, 4);
421 interp[2] = brw_vec1_grf(nr+1, 0);
422 interp[3] = brw_vec1_grf(nr+1, 4);
423
424 for(i = 0; i < 4; i++ ) {
425 if (mask & (1<<i)) {
426 dst = get_dst_reg(c, inst, i, 1);
427 brw_MOV(p, dst, suboffset(interp[i],3));
428 }
429 }
430 }
431
432 static void emit_pinterp(struct brw_wm_compile *c,
433 struct prog_instruction *inst)
434 {
435 struct brw_compile *p = &c->func;
436 GLuint mask = inst->DstReg.WriteMask;
437
438 struct brw_reg interp[4];
439 struct brw_reg dst, delta0, delta1;
440 struct brw_reg src0, w;
441
442 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
443 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
444 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
445 w = get_src_reg(c, &inst->SrcReg[2], 3, 1);
446 GLuint nr = src0.nr;
447 int i;
448
449 interp[0] = brw_vec1_grf(nr, 0);
450 interp[1] = brw_vec1_grf(nr, 4);
451 interp[2] = brw_vec1_grf(nr+1, 0);
452 interp[3] = brw_vec1_grf(nr+1, 4);
453
454 for(i = 0; i < 4; i++ ) {
455 if (mask & (1<<i)) {
456 dst = get_dst_reg(c, inst, i, 1);
457 brw_LINE(p, brw_null_reg(), interp[i], delta0);
458 brw_MAC(p, dst, suboffset(interp[i],1),
459 delta1);
460 brw_MUL(p, dst, dst, w);
461 }
462 }
463 }
464
465 static void emit_xpd(struct brw_wm_compile *c,
466 struct prog_instruction *inst)
467 {
468 int i;
469 struct brw_compile *p = &c->func;
470 GLuint mask = inst->DstReg.WriteMask;
471 for (i = 0; i < 4; i++) {
472 GLuint i2 = (i+2)%3;
473 GLuint i1 = (i+1)%3;
474 if (mask & (1<<i)) {
475 struct brw_reg src0, src1, dst;
476 dst = get_dst_reg(c, inst, i, 1);
477 src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2, 1));
478 src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1);
479 brw_MUL(p, brw_null_reg(), src0, src1);
480 src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1);
481 src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1);
482 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
483 brw_MAC(p, dst, src0, src1);
484 brw_set_saturate(p, 0);
485 }
486 }
487 brw_set_saturate(p, 0);
488 }
489
490 static void emit_dp3(struct brw_wm_compile *c,
491 struct prog_instruction *inst)
492 {
493 struct brw_reg src0[3], src1[3], dst;
494 int i;
495 struct brw_compile *p = &c->func;
496 for (i = 0; i < 3; i++) {
497 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
498 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
499 }
500
501 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
502 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
503 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
504 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
505 brw_MAC(p, dst, src0[2], src1[2]);
506 brw_set_saturate(p, 0);
507 }
508
509 static void emit_dp4(struct brw_wm_compile *c,
510 struct prog_instruction *inst)
511 {
512 struct brw_reg src0[4], src1[4], dst;
513 int i;
514 struct brw_compile *p = &c->func;
515 for (i = 0; i < 4; i++) {
516 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
517 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
518 }
519 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
520 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
521 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
522 brw_MAC(p, brw_null_reg(), src0[2], src1[2]);
523 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
524 brw_MAC(p, dst, src0[3], src1[3]);
525 brw_set_saturate(p, 0);
526 }
527
528 static void emit_dph(struct brw_wm_compile *c,
529 struct prog_instruction *inst)
530 {
531 struct brw_reg src0[4], src1[4], dst;
532 int i;
533 struct brw_compile *p = &c->func;
534 for (i = 0; i < 4; i++) {
535 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
536 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
537 }
538 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
539 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
540 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
541 brw_MAC(p, dst, src0[2], src1[2]);
542 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
543 brw_ADD(p, dst, src0[3], src1[3]);
544 brw_set_saturate(p, 0);
545 }
546
547 static void emit_math1(struct brw_wm_compile *c,
548 struct prog_instruction *inst, GLuint func)
549 {
550 struct brw_compile *p = &c->func;
551 struct brw_reg src0, dst;
552
553 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
554 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
555 brw_MOV(p, brw_message_reg(2), src0);
556 brw_math(p,
557 dst,
558 func,
559 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
560 2,
561 brw_null_reg(),
562 BRW_MATH_DATA_VECTOR,
563 BRW_MATH_PRECISION_FULL);
564 }
565
566 static void emit_rcp(struct brw_wm_compile *c,
567 struct prog_instruction *inst)
568 {
569 emit_math1(c, inst, BRW_MATH_FUNCTION_INV);
570 }
571
572 static void emit_rsq(struct brw_wm_compile *c,
573 struct prog_instruction *inst)
574 {
575 emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ);
576 }
577
578 static void emit_sin(struct brw_wm_compile *c,
579 struct prog_instruction *inst)
580 {
581 emit_math1(c, inst, BRW_MATH_FUNCTION_SIN);
582 }
583
584 static void emit_cos(struct brw_wm_compile *c,
585 struct prog_instruction *inst)
586 {
587 emit_math1(c, inst, BRW_MATH_FUNCTION_COS);
588 }
589
590 static void emit_ex2(struct brw_wm_compile *c,
591 struct prog_instruction *inst)
592 {
593 emit_math1(c, inst, BRW_MATH_FUNCTION_EXP);
594 }
595
596 static void emit_lg2(struct brw_wm_compile *c,
597 struct prog_instruction *inst)
598 {
599 emit_math1(c, inst, BRW_MATH_FUNCTION_LOG);
600 }
601
602 static void emit_add(struct brw_wm_compile *c,
603 struct prog_instruction *inst)
604 {
605 struct brw_compile *p = &c->func;
606 struct brw_reg src0, src1, dst;
607 GLuint mask = inst->DstReg.WriteMask;
608 int i;
609 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
610 for (i = 0 ; i < 4; i++) {
611 if (mask & (1<<i)) {
612 dst = get_dst_reg(c, inst, i, 1);
613 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
614 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
615 brw_ADD(p, dst, src0, src1);
616 }
617 }
618 brw_set_saturate(p, 0);
619 }
620
621 static void emit_sub(struct brw_wm_compile *c,
622 struct prog_instruction *inst)
623 {
624 struct brw_compile *p = &c->func;
625 struct brw_reg src0, src1, dst;
626 GLuint mask = inst->DstReg.WriteMask;
627 int i;
628 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
629 for (i = 0 ; i < 4; i++) {
630 if (mask & (1<<i)) {
631 dst = get_dst_reg(c, inst, i, 1);
632 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
633 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
634 brw_ADD(p, dst, src0, negate(src1));
635 }
636 }
637 brw_set_saturate(p, 0);
638 }
639
640 static void emit_mul(struct brw_wm_compile *c,
641 struct prog_instruction *inst)
642 {
643 struct brw_compile *p = &c->func;
644 struct brw_reg src0, src1, dst;
645 GLuint mask = inst->DstReg.WriteMask;
646 int i;
647 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
648 for (i = 0 ; i < 4; i++) {
649 if (mask & (1<<i)) {
650 dst = get_dst_reg(c, inst, i, 1);
651 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
652 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
653 brw_MUL(p, dst, src0, src1);
654 }
655 }
656 brw_set_saturate(p, 0);
657 }
658
659 static void emit_frc(struct brw_wm_compile *c,
660 struct prog_instruction *inst)
661 {
662 struct brw_compile *p = &c->func;
663 struct brw_reg src0, dst;
664 GLuint mask = inst->DstReg.WriteMask;
665 int i;
666 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
667 for (i = 0 ; i < 4; i++) {
668 if (mask & (1<<i)) {
669 dst = get_dst_reg(c, inst, i, 1);
670 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
671 brw_FRC(p, dst, src0);
672 }
673 }
674 if (inst->SaturateMode != SATURATE_OFF)
675 brw_set_saturate(p, 0);
676 }
677
678 static void emit_flr(struct brw_wm_compile *c,
679 struct prog_instruction *inst)
680 {
681 struct brw_compile *p = &c->func;
682 struct brw_reg src0, dst;
683 GLuint mask = inst->DstReg.WriteMask;
684 int i;
685 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
686 for (i = 0 ; i < 4; i++) {
687 if (mask & (1<<i)) {
688 dst = get_dst_reg(c, inst, i, 1);
689 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
690 brw_RNDD(p, dst, src0);
691 }
692 }
693 brw_set_saturate(p, 0);
694 }
695
696 static void emit_max(struct brw_wm_compile *c,
697 struct prog_instruction *inst)
698 {
699 struct brw_compile *p = &c->func;
700 GLuint mask = inst->DstReg.WriteMask;
701 struct brw_reg src0, src1, dst;
702 int i;
703 brw_push_insn_state(p);
704 for (i = 0; i < 4; i++) {
705 if (mask & (1<<i)) {
706 dst = get_dst_reg(c, inst, i, 1);
707 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
708 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
709 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
710 brw_MOV(p, dst, src0);
711 brw_set_saturate(p, 0);
712
713 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1);
714 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
715 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
716 brw_MOV(p, dst, src1);
717 brw_set_saturate(p, 0);
718 brw_set_predicate_control_flag_value(p, 0xff);
719 }
720 }
721 brw_pop_insn_state(p);
722 }
723
724 static void emit_min(struct brw_wm_compile *c,
725 struct prog_instruction *inst)
726 {
727 struct brw_compile *p = &c->func;
728 GLuint mask = inst->DstReg.WriteMask;
729 struct brw_reg src0, src1, dst;
730 int i;
731 brw_push_insn_state(p);
732 for (i = 0; i < 4; i++) {
733 if (mask & (1<<i)) {
734 dst = get_dst_reg(c, inst, i, 1);
735 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
736 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
737 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
738 brw_MOV(p, dst, src0);
739 brw_set_saturate(p, 0);
740
741 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0);
742 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
743 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
744 brw_MOV(p, dst, src1);
745 brw_set_saturate(p, 0);
746 brw_set_predicate_control_flag_value(p, 0xff);
747 }
748 }
749 brw_pop_insn_state(p);
750 }
751
752 static void emit_pow(struct brw_wm_compile *c,
753 struct prog_instruction *inst)
754 {
755 struct brw_compile *p = &c->func;
756 struct brw_reg dst, src0, src1;
757 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
758 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
759 src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
760
761 brw_MOV(p, brw_message_reg(2), src0);
762 brw_MOV(p, brw_message_reg(3), src1);
763
764 brw_math(p,
765 dst,
766 BRW_MATH_FUNCTION_POW,
767 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
768 2,
769 brw_null_reg(),
770 BRW_MATH_DATA_VECTOR,
771 BRW_MATH_PRECISION_FULL);
772 }
773
774 static void emit_lrp(struct brw_wm_compile *c,
775 struct prog_instruction *inst)
776 {
777 struct brw_compile *p = &c->func;
778 GLuint mask = inst->DstReg.WriteMask;
779 struct brw_reg dst, tmp1, tmp2, src0, src1, src2;
780 int i;
781 for (i = 0; i < 4; i++) {
782 if (mask & (1<<i)) {
783 dst = get_dst_reg(c, inst, i, 1);
784 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
785
786 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
787
788 if (src1.nr == dst.nr) {
789 tmp1 = alloc_tmp(c);
790 brw_MOV(p, tmp1, src1);
791 } else
792 tmp1 = src1;
793
794 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
795 if (src2.nr == dst.nr) {
796 tmp2 = alloc_tmp(c);
797 brw_MOV(p, tmp2, src2);
798 } else
799 tmp2 = src2;
800
801 brw_ADD(p, dst, negate(src0), brw_imm_f(1.0));
802 brw_MUL(p, brw_null_reg(), dst, tmp2);
803 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
804 brw_MAC(p, dst, src0, tmp1);
805 brw_set_saturate(p, 0);
806 }
807 release_tmps(c);
808 }
809 }
810
811 static void emit_kil(struct brw_wm_compile *c)
812 {
813 struct brw_compile *p = &c->func;
814 struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
815 brw_push_insn_state(p);
816 brw_set_mask_control(p, BRW_MASK_DISABLE);
817 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK
818 brw_AND(p, depth, c->emit_mask_reg, depth);
819 brw_pop_insn_state(p);
820 }
821
822 static void emit_mad(struct brw_wm_compile *c,
823 struct prog_instruction *inst)
824 {
825 struct brw_compile *p = &c->func;
826 GLuint mask = inst->DstReg.WriteMask;
827 struct brw_reg dst, src0, src1, src2;
828 int i;
829
830 for (i = 0; i < 4; i++) {
831 if (mask & (1<<i)) {
832 dst = get_dst_reg(c, inst, i, 1);
833 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
834 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
835 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
836 brw_MUL(p, dst, src0, src1);
837
838 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
839 brw_ADD(p, dst, dst, src2);
840 brw_set_saturate(p, 0);
841 }
842 }
843 }
844
845 static void emit_sop(struct brw_wm_compile *c,
846 struct prog_instruction *inst, GLuint cond)
847 {
848 struct brw_compile *p = &c->func;
849 GLuint mask = inst->DstReg.WriteMask;
850 struct brw_reg dst, src0, src1;
851 int i;
852
853 brw_push_insn_state(p);
854 for (i = 0; i < 4; i++) {
855 if (mask & (1<<i)) {
856 dst = get_dst_reg(c, inst, i, 1);
857 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
858 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
859 brw_CMP(p, brw_null_reg(), cond, src0, src1);
860 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
861 brw_MOV(p, dst, brw_imm_f(0.0));
862 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
863 brw_MOV(p, dst, brw_imm_f(1.0));
864 }
865 }
866 brw_pop_insn_state(p);
867 }
868
869 static void emit_slt(struct brw_wm_compile *c,
870 struct prog_instruction *inst)
871 {
872 emit_sop(c, inst, BRW_CONDITIONAL_L);
873 }
874
875 static void emit_sle(struct brw_wm_compile *c,
876 struct prog_instruction *inst)
877 {
878 emit_sop(c, inst, BRW_CONDITIONAL_LE);
879 }
880
881 static void emit_sgt(struct brw_wm_compile *c,
882 struct prog_instruction *inst)
883 {
884 emit_sop(c, inst, BRW_CONDITIONAL_G);
885 }
886
887 static void emit_sge(struct brw_wm_compile *c,
888 struct prog_instruction *inst)
889 {
890 emit_sop(c, inst, BRW_CONDITIONAL_GE);
891 }
892
893 static void emit_seq(struct brw_wm_compile *c,
894 struct prog_instruction *inst)
895 {
896 emit_sop(c, inst, BRW_CONDITIONAL_EQ);
897 }
898
899 static void emit_sne(struct brw_wm_compile *c,
900 struct prog_instruction *inst)
901 {
902 emit_sop(c, inst, BRW_CONDITIONAL_NEQ);
903 }
904
905 static void emit_ddx(struct brw_wm_compile *c,
906 struct prog_instruction *inst)
907 {
908 struct brw_compile *p = &c->func;
909 GLuint mask = inst->DstReg.WriteMask;
910 struct brw_reg interp[4];
911 struct brw_reg dst;
912 struct brw_reg src0, w;
913 GLuint nr, i;
914 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
915 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
916 nr = src0.nr;
917 interp[0] = brw_vec1_grf(nr, 0);
918 interp[1] = brw_vec1_grf(nr, 4);
919 interp[2] = brw_vec1_grf(nr+1, 0);
920 interp[3] = brw_vec1_grf(nr+1, 4);
921 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
922 for(i = 0; i < 4; i++ ) {
923 if (mask & (1<<i)) {
924 dst = get_dst_reg(c, inst, i, 1);
925 brw_MOV(p, dst, interp[i]);
926 brw_MUL(p, dst, dst, w);
927 }
928 }
929 brw_set_saturate(p, 0);
930 }
931
932 static void emit_ddy(struct brw_wm_compile *c,
933 struct prog_instruction *inst)
934 {
935 struct brw_compile *p = &c->func;
936 GLuint mask = inst->DstReg.WriteMask;
937 struct brw_reg interp[4];
938 struct brw_reg dst;
939 struct brw_reg src0, w;
940 GLuint nr, i;
941
942 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
943 nr = src0.nr;
944 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
945 interp[0] = brw_vec1_grf(nr, 0);
946 interp[1] = brw_vec1_grf(nr, 4);
947 interp[2] = brw_vec1_grf(nr+1, 0);
948 interp[3] = brw_vec1_grf(nr+1, 4);
949 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
950 for(i = 0; i < 4; i++ ) {
951 if (mask & (1<<i)) {
952 dst = get_dst_reg(c, inst, i, 1);
953 brw_MOV(p, dst, suboffset(interp[i], 1));
954 brw_MUL(p, dst, dst, w);
955 }
956 }
957 brw_set_saturate(p, 0);
958 }
959
960 static void emit_wpos_xy(struct brw_wm_compile *c,
961 struct prog_instruction *inst)
962 {
963 struct brw_compile *p = &c->func;
964 GLuint mask = inst->DstReg.WriteMask;
965 struct brw_reg src0[2], dst[2];
966
967 dst[0] = get_dst_reg(c, inst, 0, 1);
968 dst[1] = get_dst_reg(c, inst, 1, 1);
969
970 src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1);
971 src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1);
972
973 /* Calculate the pixel offset from window bottom left into destination
974 * X and Y channels.
975 */
976 if (mask & WRITEMASK_X) {
977 /* X' = X - origin_x */
978 brw_ADD(p,
979 dst[0],
980 retype(src0[0], BRW_REGISTER_TYPE_W),
981 brw_imm_d(- c->key.origin_x));
982 }
983
984 if (mask & WRITEMASK_Y) {
985 /* Y' = height - (Y - origin_y) = height + origin_y - Y */
986 brw_ADD(p,
987 dst[1],
988 negate(retype(src0[1], BRW_REGISTER_TYPE_W)),
989 brw_imm_d(c->key.origin_y + c->key.drawable_height - 1));
990 }
991 }
992
993 /* TODO
994 BIAS on SIMD8 not workind yet...
995 */
996 static void emit_txb(struct brw_wm_compile *c,
997 struct prog_instruction *inst)
998 {
999 struct brw_compile *p = &c->func;
1000 struct brw_reg dst[4], src[4], payload_reg;
1001 GLuint i;
1002 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1003 for (i = 0; i < 4; i++)
1004 dst[i] = get_dst_reg(c, inst, i, 1);
1005 for (i = 0; i < 4; i++)
1006 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1007
1008 switch (inst->TexSrcTarget) {
1009 case TEXTURE_1D_INDEX:
1010 brw_MOV(p, brw_message_reg(2), src[0]);
1011 brw_MOV(p, brw_message_reg(3), brw_imm_f(0));
1012 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1013 break;
1014 case TEXTURE_2D_INDEX:
1015 case TEXTURE_RECT_INDEX:
1016 brw_MOV(p, brw_message_reg(2), src[0]);
1017 brw_MOV(p, brw_message_reg(3), src[1]);
1018 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1019 break;
1020 default:
1021 brw_MOV(p, brw_message_reg(2), src[0]);
1022 brw_MOV(p, brw_message_reg(3), src[1]);
1023 brw_MOV(p, brw_message_reg(4), src[2]);
1024 break;
1025 }
1026 brw_MOV(p, brw_message_reg(5), src[3]);
1027 brw_MOV(p, brw_message_reg(6), brw_imm_f(0));
1028 brw_SAMPLE(p,
1029 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1030 1,
1031 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1032 inst->TexSrcUnit + MAX_DRAW_BUFFERS, /* surface */
1033 inst->TexSrcUnit, /* sampler */
1034 inst->DstReg.WriteMask,
1035 BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS,
1036 4,
1037 4,
1038 0);
1039 }
1040
1041 static void emit_tex(struct brw_wm_compile *c,
1042 struct prog_instruction *inst)
1043 {
1044 struct brw_compile *p = &c->func;
1045 struct brw_reg dst[4], src[4], payload_reg;
1046 GLuint msg_len;
1047 GLuint i, nr;
1048 GLuint emit;
1049 GLboolean shadow = (c->key.shadowtex_mask & (1<<inst->TexSrcUnit)) ? 1 : 0;
1050
1051 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1052
1053 for (i = 0; i < 4; i++)
1054 dst[i] = get_dst_reg(c, inst, i, 1);
1055 for (i = 0; i < 4; i++)
1056 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1057
1058
1059 switch (inst->TexSrcTarget) {
1060 case TEXTURE_1D_INDEX:
1061 emit = WRITEMASK_X;
1062 nr = 1;
1063 break;
1064 case TEXTURE_2D_INDEX:
1065 case TEXTURE_RECT_INDEX:
1066 emit = WRITEMASK_XY;
1067 nr = 2;
1068 break;
1069 default:
1070 emit = WRITEMASK_XYZ;
1071 nr = 3;
1072 break;
1073 }
1074 msg_len = 1;
1075
1076 for (i = 0; i < nr; i++) {
1077 static const GLuint swz[4] = {0,1,2,2};
1078 if (emit & (1<<i))
1079 brw_MOV(p, brw_message_reg(msg_len+1), src[swz[i]]);
1080 else
1081 brw_MOV(p, brw_message_reg(msg_len+1), brw_imm_f(0));
1082 msg_len += 1;
1083 }
1084
1085 if (shadow) {
1086 brw_MOV(p, brw_message_reg(5), brw_imm_f(0));
1087 brw_MOV(p, brw_message_reg(6), src[2]);
1088 }
1089
1090 brw_SAMPLE(p,
1091 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1092 1,
1093 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1094 inst->TexSrcUnit + MAX_DRAW_BUFFERS, /* surface */
1095 inst->TexSrcUnit, /* sampler */
1096 inst->DstReg.WriteMask,
1097 BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE,
1098 4,
1099 shadow ? 6 : 4,
1100 0);
1101
1102 if (shadow)
1103 brw_MOV(p, dst[3], brw_imm_f(1.0));
1104 }
1105
1106 static void post_wm_emit( struct brw_wm_compile *c )
1107 {
1108 GLuint nr_insns = c->fp->program.Base.NumInstructions;
1109 GLuint insn, target_insn;
1110 struct prog_instruction *inst1, *inst2;
1111 struct brw_instruction *brw_inst1, *brw_inst2;
1112 int offset;
1113 for (insn = 0; insn < nr_insns; insn++) {
1114 inst1 = &c->fp->program.Base.Instructions[insn];
1115 brw_inst1 = inst1->Data;
1116 switch (inst1->Opcode) {
1117 case OPCODE_CAL:
1118 target_insn = inst1->BranchTarget;
1119 inst2 = &c->fp->program.Base.Instructions[target_insn];
1120 brw_inst2 = inst2->Data;
1121 offset = brw_inst2 - brw_inst1;
1122 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
1123 break;
1124 default:
1125 break;
1126 }
1127 }
1128 }
1129
1130 static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
1131 {
1132 #define MAX_IFSN 32
1133 #define MAX_LOOP_DEPTH 32
1134 struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH];
1135 struct brw_instruction *inst0, *inst1;
1136 int i, if_insn = 0, loop_insn = 0;
1137 struct brw_compile *p = &c->func;
1138 struct brw_indirect stack_index = brw_indirect(0, 0);
1139
1140 c->reg_index = 0;
1141 prealloc_reg(c);
1142 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1143 brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
1144
1145 for (i = 0; i < c->nr_fp_insns; i++) {
1146 struct prog_instruction *inst = &c->prog_instructions[i];
1147 struct prog_instruction *orig_inst;
1148
1149 if ((orig_inst = inst->Data) != 0)
1150 orig_inst->Data = current_insn(p);
1151
1152 if (inst->CondUpdate)
1153 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
1154 else
1155 brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
1156
1157 switch (inst->Opcode) {
1158 case WM_PIXELXY:
1159 emit_pixel_xy(c, inst);
1160 break;
1161 case WM_DELTAXY:
1162 emit_delta_xy(c, inst);
1163 break;
1164 case WM_PIXELW:
1165 emit_pixel_w(c, inst);
1166 break;
1167 case WM_LINTERP:
1168 emit_linterp(c, inst);
1169 break;
1170 case WM_PINTERP:
1171 emit_pinterp(c, inst);
1172 break;
1173 case WM_CINTERP:
1174 emit_cinterp(c, inst);
1175 break;
1176 case WM_WPOSXY:
1177 emit_wpos_xy(c, inst);
1178 break;
1179 case WM_FB_WRITE:
1180 emit_fb_write(c, inst);
1181 break;
1182 case OPCODE_ABS:
1183 emit_abs(c, inst);
1184 break;
1185 case OPCODE_ADD:
1186 emit_add(c, inst);
1187 break;
1188 case OPCODE_SUB:
1189 emit_sub(c, inst);
1190 break;
1191 case OPCODE_FRC:
1192 emit_frc(c, inst);
1193 break;
1194 case OPCODE_FLR:
1195 emit_flr(c, inst);
1196 break;
1197 case OPCODE_LRP:
1198 emit_lrp(c, inst);
1199 break;
1200 case OPCODE_INT:
1201 emit_int(c, inst);
1202 break;
1203 case OPCODE_MOV:
1204 emit_mov(c, inst);
1205 break;
1206 case OPCODE_DP3:
1207 emit_dp3(c, inst);
1208 break;
1209 case OPCODE_DP4:
1210 emit_dp4(c, inst);
1211 break;
1212 case OPCODE_XPD:
1213 emit_xpd(c, inst);
1214 break;
1215 case OPCODE_DPH:
1216 emit_dph(c, inst);
1217 break;
1218 case OPCODE_RCP:
1219 emit_rcp(c, inst);
1220 break;
1221 case OPCODE_RSQ:
1222 emit_rsq(c, inst);
1223 break;
1224 case OPCODE_SIN:
1225 emit_sin(c, inst);
1226 break;
1227 case OPCODE_COS:
1228 emit_cos(c, inst);
1229 break;
1230 case OPCODE_EX2:
1231 emit_ex2(c, inst);
1232 break;
1233 case OPCODE_LG2:
1234 emit_lg2(c, inst);
1235 break;
1236 case OPCODE_MAX:
1237 emit_max(c, inst);
1238 break;
1239 case OPCODE_MIN:
1240 emit_min(c, inst);
1241 break;
1242 case OPCODE_DDX:
1243 emit_ddx(c, inst);
1244 break;
1245 case OPCODE_DDY:
1246 emit_ddy(c, inst);
1247 break;
1248 case OPCODE_SLT:
1249 emit_slt(c, inst);
1250 break;
1251 case OPCODE_SLE:
1252 emit_sle(c, inst);
1253 break;
1254 case OPCODE_SGT:
1255 emit_sgt(c, inst);
1256 break;
1257 case OPCODE_SGE:
1258 emit_sge(c, inst);
1259 break;
1260 case OPCODE_SEQ:
1261 emit_seq(c, inst);
1262 break;
1263 case OPCODE_SNE:
1264 emit_sne(c, inst);
1265 break;
1266 case OPCODE_MUL:
1267 emit_mul(c, inst);
1268 break;
1269 case OPCODE_POW:
1270 emit_pow(c, inst);
1271 break;
1272 case OPCODE_MAD:
1273 emit_mad(c, inst);
1274 break;
1275 case OPCODE_TEX:
1276 emit_tex(c, inst);
1277 break;
1278 case OPCODE_TXB:
1279 emit_txb(c, inst);
1280 break;
1281 case OPCODE_KIL_NV:
1282 emit_kil(c);
1283 break;
1284 case OPCODE_IF:
1285 assert(if_insn < MAX_IFSN);
1286 if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
1287 break;
1288 case OPCODE_ELSE:
1289 if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
1290 break;
1291 case OPCODE_ENDIF:
1292 assert(if_insn > 0);
1293 brw_ENDIF(p, if_inst[--if_insn]);
1294 break;
1295 case OPCODE_BGNSUB:
1296 case OPCODE_ENDSUB:
1297 break;
1298 case OPCODE_CAL:
1299 brw_push_insn_state(p);
1300 brw_set_mask_control(p, BRW_MASK_DISABLE);
1301 brw_set_access_mode(p, BRW_ALIGN_1);
1302 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
1303 brw_set_access_mode(p, BRW_ALIGN_16);
1304 brw_ADD(p, get_addr_reg(stack_index),
1305 get_addr_reg(stack_index), brw_imm_d(4));
1306 orig_inst = inst->Data;
1307 orig_inst->Data = &p->store[p->nr_insn];
1308 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1309 brw_pop_insn_state(p);
1310 break;
1311
1312 case OPCODE_RET:
1313 brw_push_insn_state(p);
1314 brw_set_mask_control(p, BRW_MASK_DISABLE);
1315 brw_ADD(p, get_addr_reg(stack_index),
1316 get_addr_reg(stack_index), brw_imm_d(-4));
1317 brw_set_access_mode(p, BRW_ALIGN_1);
1318 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
1319 brw_set_access_mode(p, BRW_ALIGN_16);
1320 brw_pop_insn_state(p);
1321
1322 break;
1323 case OPCODE_BGNLOOP:
1324 loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8);
1325 break;
1326 case OPCODE_BRK:
1327 brw_BREAK(p);
1328 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1329 break;
1330 case OPCODE_CONT:
1331 brw_CONT(p);
1332 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1333 break;
1334 case OPCODE_ENDLOOP:
1335 loop_insn--;
1336 inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]);
1337 /* patch all the BREAK instructions from
1338 last BEGINLOOP */
1339 while (inst0 > loop_inst[loop_insn]) {
1340 inst0--;
1341 if (inst0->header.opcode == BRW_OPCODE_BREAK) {
1342 inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
1343 inst0->bits3.if_else.pop_count = 0;
1344 } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
1345 inst0->bits3.if_else.jump_count = inst1 - inst0;
1346 inst0->bits3.if_else.pop_count = 0;
1347 }
1348 }
1349 break;
1350 default:
1351 _mesa_printf("unsupported IR in fragment shader %d\n",
1352 inst->Opcode);
1353 }
1354 if (inst->CondUpdate)
1355 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1356 else
1357 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1358 }
1359 post_wm_emit(c);
1360 for (i = 0; i < c->fp->program.Base.NumInstructions; i++)
1361 c->fp->program.Base.Instructions[i].Data = NULL;
1362 }
1363
1364 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
1365 {
1366 brw_wm_pass_fp(c);
1367 c->tmp_index = 127;
1368 brw_wm_emit_glsl(brw, c);
1369 c->prog_data.total_grf = c->reg_index;
1370 c->prog_data.total_scratch = 0;
1371 }