Merge commit 'origin/gallium-0.1'
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_iz.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "brw_wm.h"
35
36
37 #undef P /* prompted depth */
38 #undef C /* computed */
39 #undef N /* non-promoted? */
40
41 #define P 0
42 #define C 1
43 #define N 2
44
45 const struct {
46 GLuint mode:2;
47 GLuint sd_present:1;
48 GLuint sd_to_rt:1;
49 GLuint dd_present:1;
50 GLuint ds_present:1;
51 } wm_iz_table[IZ_BIT_MAX] =
52 {
53 { P, 0, 0, 0, 0 },
54 { P, 0, 0, 0, 0 },
55 { P, 0, 0, 0, 0 },
56 { P, 0, 0, 0, 0 },
57 { P, 0, 0, 0, 0 },
58 { N, 1, 1, 0, 0 },
59 { N, 0, 1, 0, 0 },
60 { N, 0, 1, 0, 0 },
61 { P, 0, 0, 0, 0 },
62 { P, 0, 0, 0, 0 },
63 { C, 0, 1, 1, 0 },
64 { C, 0, 1, 1, 0 },
65 { P, 0, 0, 0, 0 },
66 { N, 1, 1, 0, 0 },
67 { C, 0, 1, 1, 0 },
68 { C, 0, 1, 1, 0 },
69 { P, 0, 0, 0, 0 },
70 { P, 0, 0, 0, 0 },
71 { P, 0, 0, 0, 0 },
72 { P, 0, 0, 0, 0 },
73 { P, 0, 0, 0, 0 },
74 { N, 1, 1, 0, 0 },
75 { N, 0, 1, 0, 0 },
76 { N, 0, 1, 0, 0 },
77 { P, 0, 0, 0, 0 },
78 { P, 0, 0, 0, 0 },
79 { C, 0, 1, 1, 0 },
80 { C, 0, 1, 1, 0 },
81 { P, 0, 0, 0, 0 },
82 { N, 1, 1, 0, 0 },
83 { C, 0, 1, 1, 0 },
84 { C, 0, 1, 1, 0 },
85 { P, 0, 0, 0, 0 },
86 { P, 0, 0, 0, 0 },
87 { P, 0, 0, 0, 0 },
88 { P, 0, 0, 0, 0 },
89 { P, 0, 0, 0, 0 },
90 { N, 1, 1, 0, 1 },
91 { N, 0, 1, 0, 1 },
92 { N, 0, 1, 0, 1 },
93 { P, 0, 0, 0, 0 },
94 { P, 0, 0, 0, 0 },
95 { C, 0, 1, 1, 1 },
96 { C, 0, 1, 1, 1 },
97 { P, 0, 0, 0, 0 },
98 { N, 1, 1, 0, 1 },
99 { C, 0, 1, 1, 1 },
100 { C, 0, 1, 1, 1 },
101 { P, 0, 0, 0, 0 },
102 { C, 0, 0, 0, 1 },
103 { P, 0, 0, 0, 0 },
104 { C, 0, 1, 0, 1 },
105 { P, 0, 0, 0, 0 },
106 { C, 1, 1, 0, 1 },
107 { C, 0, 1, 0, 1 },
108 { C, 0, 1, 0, 1 },
109 { P, 0, 0, 0, 0 },
110 { C, 1, 1, 1, 1 },
111 { C, 0, 1, 1, 1 },
112 { C, 0, 1, 1, 1 },
113 { P, 0, 0, 0, 0 },
114 { C, 1, 1, 1, 1 },
115 { C, 0, 1, 1, 1 },
116 { C, 0, 1, 1, 1 }
117 };
118
119 void brw_wm_lookup_iz( GLuint line_aa,
120 GLuint lookup,
121 struct brw_wm_prog_key *key )
122 {
123 GLuint reg = 2;
124
125 assert (lookup < IZ_BIT_MAX);
126
127 if (lookup & IZ_PS_COMPUTES_DEPTH_BIT)
128 key->computes_depth = 1;
129
130 if (wm_iz_table[lookup].sd_present) {
131 key->source_depth_reg = reg;
132 reg += 2;
133 }
134
135 if (wm_iz_table[lookup].sd_to_rt)
136 key->source_depth_to_render_target = 1;
137
138 if (wm_iz_table[lookup].ds_present || line_aa != AA_NEVER) {
139 key->aa_dest_stencil_reg = reg;
140 key->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present &&
141 line_aa == AA_SOMETIMES);
142 reg++;
143 }
144
145 if (wm_iz_table[lookup].dd_present) {
146 key->dest_depth_reg = reg;
147 reg+=2;
148 }
149
150 key->nr_depth_regs = (reg+1)/2;
151 }
152