2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
44 static void spill_value(struct brw_wm_compile
*c
,
45 struct brw_wm_value
*value
);
47 static void prealloc_reg(struct brw_wm_compile
*c
,
48 struct brw_wm_value
*value
,
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
55 c
->pass2_grf
[reg
].value
= value
;
56 c
->pass2_grf
[reg
].nextuse
= 0;
58 value
->resident
= &c
->pass2_grf
[reg
];
59 value
->hw_reg
= brw_vec8_grf(reg
*2, 0);
61 if (TEST_PAYLOAD_SPILLS
)
62 spill_value(c
, value
);
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
70 static void init_registers( struct brw_wm_compile
*c
)
72 struct brw_context
*brw
= c
->func
.brw
;
73 struct intel_context
*intel
= &brw
->intel
;
74 GLuint nr_interp_regs
= 0;
78 for (j
= 0; j
< c
->grf_limit
; j
++)
79 c
->pass2_grf
[j
].nextuse
= BRW_WM_MAX_INSN
;
81 for (j
= 0; j
< (c
->nr_payload_regs
+ 1) / 2; j
++)
82 prealloc_reg(c
, &c
->payload
.depth
[j
], i
++);
84 for (j
= 0; j
< c
->nr_creg
; j
++)
85 prealloc_reg(c
, &c
->creg
[j
], i
++);
87 if (intel
->gen
>= 6) {
88 for (unsigned int j
= 0; j
< FRAG_ATTRIB_MAX
; j
++) {
89 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(j
)) {
91 prealloc_reg(c
, &c
->payload
.input_interp
[j
], i
++);
95 for (j
= 0; j
< VERT_RESULT_MAX
; j
++) {
96 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(j
)) {
97 int fp_index
= _mesa_vert_result_to_frag_attrib(j
);
101 prealloc_reg(c
, &c
->payload
.input_interp
[fp_index
], i
++);
104 assert(nr_interp_regs
>= 1);
108 c
->prog_data
.first_curbe_grf
= ALIGN(c
->nr_payload_regs
, 2);
109 c
->prog_data
.urb_read_length
= nr_interp_regs
* 2;
110 c
->prog_data
.curb_read_length
= c
->nr_creg
* 2;
112 c
->max_wm_grf
= i
* 2;
116 /* Update the nextuse value for each register in our file.
118 static void update_register_usage(struct brw_wm_compile
*c
,
123 for (i
= 1; i
< c
->grf_limit
; i
++) {
124 struct brw_wm_grf
*grf
= &c
->pass2_grf
[i
];
126 /* Only search those which can change:
128 if (grf
->nextuse
< thisinsn
) {
129 const struct brw_wm_ref
*ref
= grf
->value
->lastuse
;
131 /* Has last use of value been passed?
133 if (ref
->insn
< thisinsn
) {
134 grf
->value
->resident
= 0;
136 grf
->nextuse
= BRW_WM_MAX_INSN
;
139 /* Else loop through chain to update:
141 while (ref
->prevuse
&& ref
->prevuse
->insn
>= thisinsn
)
144 grf
->nextuse
= ref
->insn
;
151 static void spill_value(struct brw_wm_compile
*c
,
152 struct brw_wm_value
*value
)
154 /* Allocate a spill slot. Note that allocations start from 0x40 -
155 * the first slot is reserved to mean "undef" in brw_wm_emit.c
157 if (!value
->spill_slot
) {
158 c
->last_scratch
+= 0x40;
159 value
->spill_slot
= c
->last_scratch
;
162 /* The spill will be done in brw_wm_emit.c immediately after the
163 * value is calculated, so we can just take this reg without any
166 value
->resident
->value
= NULL
;
167 value
->resident
->nextuse
= BRW_WM_MAX_INSN
;
168 value
->resident
= NULL
;
173 /* Search for contiguous region with the most distant nearest
174 * member. Free regs count as very distant.
176 * TODO: implement spill-to-reg so that we can rearrange discontigous
177 * free regs and then spill the oldest non-free regs in sequence.
178 * This would mean inserting instructions in this pass.
180 static GLuint
search_contiguous_regs(struct brw_wm_compile
*c
,
184 struct brw_wm_grf
*grf
= c
->pass2_grf
;
189 /* Start search at 1: r0 is special and can't be used or spilled.
191 for (i
= 1; i
< c
->grf_limit
&& furthest
< BRW_WM_MAX_INSN
; i
++) {
192 GLuint group_nextuse
= BRW_WM_MAX_INSN
;
194 for (j
= 0; j
< nr
; j
++) {
195 if (grf
[i
+j
].nextuse
< group_nextuse
)
196 group_nextuse
= grf
[i
+j
].nextuse
;
199 if (group_nextuse
> furthest
) {
200 furthest
= group_nextuse
;
205 assert(furthest
!= thisinsn
);
207 /* Any non-empty regs will need to be spilled:
209 for (j
= 0; j
< nr
; j
++)
210 if (grf
[reg
+j
].value
)
211 spill_value(c
, grf
[reg
+j
].value
);
217 static void alloc_contiguous_dest(struct brw_wm_compile
*c
,
218 struct brw_wm_value
*dst
[],
222 GLuint reg
= search_contiguous_regs(c
, nr
, thisinsn
);
225 for (i
= 0; i
< nr
; i
++) {
227 /* Need to grab a dummy value in TEX case. Don't introduce
228 * it into the tracking scheme.
230 dst
[i
] = &c
->vreg
[c
->nr_vreg
++];
233 assert(!dst
[i
]->resident
);
234 assert(c
->pass2_grf
[reg
+i
].nextuse
!= thisinsn
);
236 c
->pass2_grf
[reg
+i
].value
= dst
[i
];
237 c
->pass2_grf
[reg
+i
].nextuse
= thisinsn
;
239 dst
[i
]->resident
= &c
->pass2_grf
[reg
+i
];
242 dst
[i
]->hw_reg
= brw_vec8_grf((reg
+i
)*2, 0);
245 if ((reg
+nr
)*2 > c
->max_wm_grf
)
246 c
->max_wm_grf
= (reg
+nr
) * 2;
250 static void load_args(struct brw_wm_compile
*c
,
251 struct brw_wm_instruction
*inst
)
253 GLuint thisinsn
= inst
- c
->instruction
;
256 for (i
= 0; i
< 3; i
++) {
257 for (j
= 0; j
< 4; j
++) {
258 struct brw_wm_ref
*ref
= inst
->src
[i
][j
];
261 if (!ref
->value
->resident
) {
262 /* Need to bring the value in from scratch space. The code for
263 * this will be done in brw_wm_emit.c, here we just do the
264 * register allocation and mark the ref as requiring a fill.
266 GLuint reg
= search_contiguous_regs(c
, 1, thisinsn
);
268 c
->pass2_grf
[reg
].value
= ref
->value
;
269 c
->pass2_grf
[reg
].nextuse
= thisinsn
;
271 ref
->value
->resident
= &c
->pass2_grf
[reg
];
273 /* Note that a fill is required:
275 ref
->unspill_reg
= reg
*2;
278 /* Adjust the hw_reg to point at the value's current location:
280 assert(ref
->value
== ref
->value
->resident
->value
);
281 ref
->hw_reg
.nr
+= (ref
->value
->resident
- c
->pass2_grf
) * 2;
289 /* Step 3: Work forwards once again. Perform register allocations,
290 * taking into account instructions like TEX which require contiguous
291 * result registers. Where necessary spill registers to scratch space
294 void brw_wm_pass2( struct brw_wm_compile
*c
)
301 for (insn
= 0; insn
< c
->nr_insns
; insn
++) {
302 struct brw_wm_instruction
*inst
= &c
->instruction
[insn
];
304 /* Update registers' nextuse values:
306 update_register_usage(c
, insn
);
308 /* May need to unspill some args.
312 /* Allocate registers to hold results:
314 switch (inst
->opcode
) {
318 alloc_contiguous_dest(c
, inst
->dst
, 4, insn
);
322 for (i
= 0; i
< 4; i
++) {
323 if (inst
->writemask
& (1<<i
)) {
324 assert(inst
->dst
[i
]);
325 alloc_contiguous_dest(c
, &inst
->dst
[i
], 1, insn
);
331 if (TEST_DST_SPILLS
&& inst
->opcode
!= WM_PIXELXY
) {
332 for (i
= 0; i
< 4; i
++)
334 spill_value(c
, inst
->dst
[i
]);
338 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
339 brw_wm_print_program(c
, "pass2");
342 c
->state
= PASS2_DONE
;
344 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
345 brw_wm_print_program(c
, "pass2/done");