src/mesa/drivers/dri/i965/brw_wm_pass2.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_wm.h"
  35 #include "program.h"
  36 #include "arbprogparse.h"
  37 #include "program_instruction.h"
  38
  39 /* Use these to force spilling so that that functionality can be
  40  * tested with known-good examples rather than having to construct new
  41  * tests.
  42  */
  43 #define TEST_PAYLOAD_SPILLS 0
  44 #define TEST_DST_SPILLS 0
  45
  46 static void spill_value(struct brw_wm_compile *c,
  47                         struct brw_wm_value *value);
  48
  49 static void prealloc_reg(struct brw_wm_compile *c,
  50                          struct brw_wm_value *value,
  51                          GLuint reg)
  52 {
  53    if (value->lastuse) {
  54       /* Set nextuse to zero, it will be corrected by
  55        * update_register_usage().
  56        */
  57       c->pass2_grf[reg].value = value;
  58       c->pass2_grf[reg].nextuse = 0;
  59
  60       value->resident = &c->pass2_grf[reg];
  61       value->hw_reg = brw_vec8_grf(reg*2, 0);
  62
  63       if (TEST_PAYLOAD_SPILLS)
  64          spill_value(c, value);
  65    }
  66 }
  67
  68
  69 /* Initialize all the register values.  Do the initial setup
  70  * calculations for interpolants.
  71  */
  72 static void init_registers( struct brw_wm_compile *c )
  73 {
  74    GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted;
  75    GLuint nr_interp_regs = 0;
  76    GLuint i = 0;
  77    GLuint j;
  78
  79    for (j = 0; j < c->grf_limit; j++)
  80       c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
  81
  82    for (j = 0; j < c->key.nr_depth_regs; j++)
  83       prealloc_reg(c, &c->payload.depth[j], i++);
  84
  85    for (j = 0; j < c->nr_creg; j++)
  86       prealloc_reg(c, &c->creg[j], i++);
  87
  88    for (j = 0; j < FRAG_ATTRIB_MAX; j++)
  89       if (inputs & (1<<j)) {
  90          nr_interp_regs++;
  91          prealloc_reg(c, &c->payload.input_interp[j], i++);
  92       }
  93
  94    assert(nr_interp_regs >= 1);
  95
  96    c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
  97    c->prog_data.urb_read_length = nr_interp_regs * 2;
  98    c->prog_data.curb_read_length = c->nr_creg * 2;
  99
 100    c->max_wm_grf = i * 2;
 101 }
 102
 103
 104 /* Update the nextuse value for each register in our file.
 105  */
 106 static void update_register_usage(struct brw_wm_compile *c,
 107                                   GLuint thisinsn)
 108 {
 109    GLuint i;
 110
 111    for (i = 1; i < c->grf_limit; i++) {
 112       struct brw_wm_grf *grf = &c->pass2_grf[i];
 113
 114       /* Only search those which can change:
 115        */
 116       if (grf->nextuse < thisinsn) {
 117          struct brw_wm_ref *ref = grf->value->lastuse;
 118
 119          /* Has last use of value been passed?
 120           */
 121          if (ref->insn < thisinsn) {
 122             grf->value->resident = 0;
 123             grf->value = 0;
 124             grf->nextuse = BRW_WM_MAX_INSN;
 125          }
 126          else {
 127             /* Else loop through chain to update:
 128              */
 129             while (ref->prevuse && ref->prevuse->insn >= thisinsn)
 130                ref = ref->prevuse;
 131
 132             grf->nextuse = ref->insn;
 133          }
 134       }
 135    }
 136 }
 137
 138
 139 static void spill_value(struct brw_wm_compile *c,
 140                         struct brw_wm_value *value)
 141 {
 142    /* Allocate a spill slot.  Note that allocations start from 0x40 -
 143     * the first slot is reserved to mean "undef" in brw_wm_emit.c
 144     */
 145    if (!value->spill_slot) {
 146       c->last_scratch += 0x40;
 147       value->spill_slot = c->last_scratch;
 148    }
 149
 150    /* The spill will be done in brw_wm_emit.c immediately after the
 151     * value is calculated, so we can just take this reg without any
 152     * further work.
 153     */
 154    value->resident->value = NULL;
 155    value->resident->nextuse = BRW_WM_MAX_INSN;
 156    value->resident = NULL;
 157 }
 158
 159
 160
 161 /* Search for contiguous region with the most distant nearest
 162  * member.  Free regs count as very distant.
 163  *
 164  * TODO: implement spill-to-reg so that we can rearrange discontigous
 165  * free regs and then spill the oldest non-free regs in sequence.
 166  * This would mean inserting instructions in this pass.
 167  */
 168 static GLuint search_contiguous_regs(struct brw_wm_compile *c,
 169                                      GLuint nr,
 170                                      GLuint thisinsn)
 171 {
 172    struct brw_wm_grf *grf = c->pass2_grf;
 173    GLuint furthest = 0;
 174    GLuint reg = 0;
 175    GLuint i, j;
 176
 177    /* Start search at 1: r0 is special and can't be used or spilled.
 178     */
 179    for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) {
 180       GLuint group_nextuse = BRW_WM_MAX_INSN;
 181
 182       for (j = 0; j < nr; j++) {
 183          if (grf[i+j].nextuse < group_nextuse)
 184             group_nextuse = grf[i+j].nextuse;
 185       }
 186
 187       if (group_nextuse > furthest) {
 188          furthest = group_nextuse;
 189          reg = i;
 190       }
 191    }
 192
 193    assert(furthest != thisinsn);
 194
 195    /* Any non-empty regs will need to be spilled:
 196     */
 197    for (j = 0; j < nr; j++)
 198       if (grf[reg+j].value)
 199          spill_value(c, grf[reg+j].value);
 200
 201    return reg;
 202 }
 203
 204
 205 static void alloc_contiguous_dest(struct brw_wm_compile *c,
 206                                   struct brw_wm_value *dst[],
 207                                   GLuint nr,
 208                                   GLuint thisinsn)
 209 {
 210    GLuint reg = search_contiguous_regs(c, nr, thisinsn);
 211    GLuint i;
 212
 213    for (i = 0; i < nr; i++) {
 214       if (!dst[i]) {
 215          /* Need to grab a dummy value in TEX case.  Don't introduce
 216           * it into the tracking scheme.
 217           */
 218          dst[i] = &c->vreg[c->nr_vreg++];
 219       }
 220       else {
 221          assert(!dst[i]->resident);
 222          assert(c->pass2_grf[reg+i].nextuse != thisinsn);
 223
 224          c->pass2_grf[reg+i].value = dst[i];
 225          c->pass2_grf[reg+i].nextuse = thisinsn;
 226
 227          dst[i]->resident = &c->pass2_grf[reg+i];
 228       }
 229
 230       dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0);
 231    }
 232
 233    if ((reg+nr)*2 > c->max_wm_grf)
 234       c->max_wm_grf = (reg+nr) * 2;
 235 }
 236
 237
 238 static void load_args(struct brw_wm_compile *c,
 239                       struct brw_wm_instruction *inst)
 240 {
 241    GLuint thisinsn = inst - c->instruction;
 242    GLuint i,j;
 243
 244    for (i = 0; i < 3; i++) {
 245       for (j = 0; j < 4; j++) {
 246          struct brw_wm_ref *ref = inst->src[i][j];
 247
 248          if (ref) {
 249             if (!ref->value->resident) {
 250                /* Need to bring the value in from scratch space.  The code for
 251                 * this will be done in brw_wm_emit.c, here we just do the
 252                 * register allocation and mark the ref as requiring a fill.
 253                 */
 254                GLuint reg = search_contiguous_regs(c, 1, thisinsn);
 255
 256                c->pass2_grf[reg].value = ref->value;
 257                c->pass2_grf[reg].nextuse = thisinsn;
 258
 259                ref->value->resident = &c->pass2_grf[reg];
 260
 261                /* Note that a fill is required:
 262                 */
 263                ref->unspill_reg = reg*2;
 264             }
 265
 266             /* Adjust the hw_reg to point at the value's current location:
 267              */
 268             assert(ref->value == ref->value->resident->value);
 269             ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2;
 270          }
 271       }
 272    }
 273 }
 274
 275
 276
 277 /* Step 3: Work forwards once again.  Perform register allocations,
 278  * taking into account instructions like TEX which require contiguous
 279  * result registers.  Where necessary spill registers to scratch space
 280  * and reload later.
 281  */
 282 void brw_wm_pass2( struct brw_wm_compile *c )
 283 {
 284    GLuint insn;
 285    GLuint i;
 286
 287    init_registers(c);
 288
 289    for (insn = 0; insn < c->nr_insns; insn++) {
 290       struct brw_wm_instruction *inst = &c->instruction[insn];
 291
 292       /* Update registers' nextuse values:
 293        */
 294       update_register_usage(c, insn);
 295
 296       /* May need to unspill some args.
 297        */
 298       load_args(c, inst);
 299
 300       /* Allocate registers to hold results:
 301        */
 302       switch (inst->opcode) {
 303       case OPCODE_TEX:
 304       case OPCODE_TXB:
 305       case OPCODE_TXP:
 306          alloc_contiguous_dest(c, inst->dst, 4, insn);
 307          break;
 308
 309       default:
 310          for (i = 0; i < 4; i++) {
 311             if (inst->writemask & (1<<i)) {
 312                assert(inst->dst[i]);
 313                alloc_contiguous_dest(c, &inst->dst[i], 1, insn);
 314             }
 315          }
 316          break;
 317       }
 318
 319       if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY)
 320          for (i = 0; i < 4; i++)
 321             if (inst->dst[i])
 322                spill_value(c, inst->dst[i]);
 323
 324    }
 325
 326    if (INTEL_DEBUG & DEBUG_WM) {
 327       brw_wm_print_program(c, "pass2");
 328    }
 329
 330    c->state = PASS2_DONE;
 331
 332    if (INTEL_DEBUG & DEBUG_WM) {
 333       brw_wm_print_program(c, "pass2/done");
 334    }
 335 }
 336
 337
 338