2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
44 static void spill_value(struct brw_wm_compile
*c
,
45 struct brw_wm_value
*value
);
47 static void prealloc_reg(struct brw_wm_compile
*c
,
48 struct brw_wm_value
*value
,
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
55 c
->pass2_grf
[reg
].value
= value
;
56 c
->pass2_grf
[reg
].nextuse
= 0;
58 value
->resident
= &c
->pass2_grf
[reg
];
59 value
->hw_reg
= brw_vec8_grf(reg
*2, 0);
61 if (TEST_PAYLOAD_SPILLS
)
62 spill_value(c
, value
);
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
70 static void init_registers( struct brw_wm_compile
*c
)
72 GLuint nr_interp_regs
= 0;
76 for (j
= 0; j
< c
->grf_limit
; j
++)
77 c
->pass2_grf
[j
].nextuse
= BRW_WM_MAX_INSN
;
79 for (j
= 0; j
< (c
->key
.nr_payload_regs
+ 1) / 2; j
++)
80 prealloc_reg(c
, &c
->payload
.depth
[j
], i
++);
82 for (j
= 0; j
< c
->nr_creg
; j
++)
83 prealloc_reg(c
, &c
->creg
[j
], i
++);
85 for (j
= 0; j
< VERT_RESULT_MAX
; j
++) {
86 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(j
)) {
89 if (j
>= VERT_RESULT_VAR0
)
90 fp_index
= j
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
91 else if (j
<= VERT_RESULT_TEX7
)
98 prealloc_reg(c
, &c
->payload
.input_interp
[fp_index
], i
++);
102 assert(nr_interp_regs
>= 1);
104 c
->prog_data
.first_curbe_grf
= ALIGN(c
->key
.nr_payload_regs
, 2);
105 c
->prog_data
.urb_read_length
= nr_interp_regs
* 2;
106 c
->prog_data
.curb_read_length
= c
->nr_creg
* 2;
108 c
->max_wm_grf
= i
* 2;
112 /* Update the nextuse value for each register in our file.
114 static void update_register_usage(struct brw_wm_compile
*c
,
119 for (i
= 1; i
< c
->grf_limit
; i
++) {
120 struct brw_wm_grf
*grf
= &c
->pass2_grf
[i
];
122 /* Only search those which can change:
124 if (grf
->nextuse
< thisinsn
) {
125 const struct brw_wm_ref
*ref
= grf
->value
->lastuse
;
127 /* Has last use of value been passed?
129 if (ref
->insn
< thisinsn
) {
130 grf
->value
->resident
= 0;
132 grf
->nextuse
= BRW_WM_MAX_INSN
;
135 /* Else loop through chain to update:
137 while (ref
->prevuse
&& ref
->prevuse
->insn
>= thisinsn
)
140 grf
->nextuse
= ref
->insn
;
147 static void spill_value(struct brw_wm_compile
*c
,
148 struct brw_wm_value
*value
)
150 /* Allocate a spill slot. Note that allocations start from 0x40 -
151 * the first slot is reserved to mean "undef" in brw_wm_emit.c
153 if (!value
->spill_slot
) {
154 c
->last_scratch
+= 0x40;
155 value
->spill_slot
= c
->last_scratch
;
158 /* The spill will be done in brw_wm_emit.c immediately after the
159 * value is calculated, so we can just take this reg without any
162 value
->resident
->value
= NULL
;
163 value
->resident
->nextuse
= BRW_WM_MAX_INSN
;
164 value
->resident
= NULL
;
169 /* Search for contiguous region with the most distant nearest
170 * member. Free regs count as very distant.
172 * TODO: implement spill-to-reg so that we can rearrange discontigous
173 * free regs and then spill the oldest non-free regs in sequence.
174 * This would mean inserting instructions in this pass.
176 static GLuint
search_contiguous_regs(struct brw_wm_compile
*c
,
180 struct brw_wm_grf
*grf
= c
->pass2_grf
;
185 /* Start search at 1: r0 is special and can't be used or spilled.
187 for (i
= 1; i
< c
->grf_limit
&& furthest
< BRW_WM_MAX_INSN
; i
++) {
188 GLuint group_nextuse
= BRW_WM_MAX_INSN
;
190 for (j
= 0; j
< nr
; j
++) {
191 if (grf
[i
+j
].nextuse
< group_nextuse
)
192 group_nextuse
= grf
[i
+j
].nextuse
;
195 if (group_nextuse
> furthest
) {
196 furthest
= group_nextuse
;
201 assert(furthest
!= thisinsn
);
203 /* Any non-empty regs will need to be spilled:
205 for (j
= 0; j
< nr
; j
++)
206 if (grf
[reg
+j
].value
)
207 spill_value(c
, grf
[reg
+j
].value
);
213 static void alloc_contiguous_dest(struct brw_wm_compile
*c
,
214 struct brw_wm_value
*dst
[],
218 GLuint reg
= search_contiguous_regs(c
, nr
, thisinsn
);
221 for (i
= 0; i
< nr
; i
++) {
223 /* Need to grab a dummy value in TEX case. Don't introduce
224 * it into the tracking scheme.
226 dst
[i
] = &c
->vreg
[c
->nr_vreg
++];
229 assert(!dst
[i
]->resident
);
230 assert(c
->pass2_grf
[reg
+i
].nextuse
!= thisinsn
);
232 c
->pass2_grf
[reg
+i
].value
= dst
[i
];
233 c
->pass2_grf
[reg
+i
].nextuse
= thisinsn
;
235 dst
[i
]->resident
= &c
->pass2_grf
[reg
+i
];
238 dst
[i
]->hw_reg
= brw_vec8_grf((reg
+i
)*2, 0);
241 if ((reg
+nr
)*2 > c
->max_wm_grf
)
242 c
->max_wm_grf
= (reg
+nr
) * 2;
246 static void load_args(struct brw_wm_compile
*c
,
247 struct brw_wm_instruction
*inst
)
249 GLuint thisinsn
= inst
- c
->instruction
;
252 for (i
= 0; i
< 3; i
++) {
253 for (j
= 0; j
< 4; j
++) {
254 struct brw_wm_ref
*ref
= inst
->src
[i
][j
];
257 if (!ref
->value
->resident
) {
258 /* Need to bring the value in from scratch space. The code for
259 * this will be done in brw_wm_emit.c, here we just do the
260 * register allocation and mark the ref as requiring a fill.
262 GLuint reg
= search_contiguous_regs(c
, 1, thisinsn
);
264 c
->pass2_grf
[reg
].value
= ref
->value
;
265 c
->pass2_grf
[reg
].nextuse
= thisinsn
;
267 ref
->value
->resident
= &c
->pass2_grf
[reg
];
269 /* Note that a fill is required:
271 ref
->unspill_reg
= reg
*2;
274 /* Adjust the hw_reg to point at the value's current location:
276 assert(ref
->value
== ref
->value
->resident
->value
);
277 ref
->hw_reg
.nr
+= (ref
->value
->resident
- c
->pass2_grf
) * 2;
285 /* Step 3: Work forwards once again. Perform register allocations,
286 * taking into account instructions like TEX which require contiguous
287 * result registers. Where necessary spill registers to scratch space
290 void brw_wm_pass2( struct brw_wm_compile
*c
)
297 for (insn
= 0; insn
< c
->nr_insns
; insn
++) {
298 struct brw_wm_instruction
*inst
= &c
->instruction
[insn
];
300 /* Update registers' nextuse values:
302 update_register_usage(c
, insn
);
304 /* May need to unspill some args.
308 /* Allocate registers to hold results:
310 switch (inst
->opcode
) {
314 alloc_contiguous_dest(c
, inst
->dst
, 4, insn
);
318 for (i
= 0; i
< 4; i
++) {
319 if (inst
->writemask
& (1<<i
)) {
320 assert(inst
->dst
[i
]);
321 alloc_contiguous_dest(c
, &inst
->dst
[i
], 1, insn
);
327 if (TEST_DST_SPILLS
&& inst
->opcode
!= WM_PIXELXY
) {
328 for (i
= 0; i
< 4; i
++)
330 spill_value(c
, inst
->dst
[i
]);
334 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
335 brw_wm_print_program(c
, "pass2");
338 c
->state
= PASS2_DONE
;
340 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
341 brw_wm_print_program(c
, "pass2/done");