src/mesa/drivers/dri/i965/brw_wm_pass2.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_wm.h"
  35
  36
  37 /* Use these to force spilling so that that functionality can be
  38  * tested with known-good examples rather than having to construct new
  39  * tests.
  40  */
  41 #define TEST_PAYLOAD_SPILLS 0
  42 #define TEST_DST_SPILLS 0
  43
  44 static void spill_value(struct brw_wm_compile *c,
  45                         struct brw_wm_value *value);
  46
  47 static void prealloc_reg(struct brw_wm_compile *c,
  48                          struct brw_wm_value *value,
  49                          GLuint reg)
  50 {
  51    if (value->lastuse) {
  52       /* Set nextuse to zero, it will be corrected by
  53        * update_register_usage().
  54        */
  55       c->pass2_grf[reg].value = value;
  56       c->pass2_grf[reg].nextuse = 0;
  57
  58       value->resident = &c->pass2_grf[reg];
  59       value->hw_reg = brw_vec8_grf(reg*2, 0);
  60
  61       if (TEST_PAYLOAD_SPILLS)
  62          spill_value(c, value);
  63    }
  64 }
  65
  66
  67 /* Initialize all the register values.  Do the initial setup
  68  * calculations for interpolants.
  69  */
  70 static void init_registers( struct brw_wm_compile *c )
  71 {
  72    struct brw_context *brw = c->func.brw;
  73    GLuint inputs = (brw->vs.prog_data->outputs_written & DO_SETUP_BITS);
  74    GLuint nr_interp_regs = 0;
  75    GLuint i = 0;
  76    GLuint j;
  77
  78    for (j = 0; j < c->grf_limit; j++)
  79       c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
  80
  81    for (j = 0; j < c->key.nr_depth_regs; j++)
  82       prealloc_reg(c, &c->payload.depth[j], i++);
  83
  84    for (j = 0; j < c->nr_creg; j++)
  85       prealloc_reg(c, &c->creg[j], i++);
  86
  87    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
  88       if (inputs & (1<<j)) {
  89          /* index for vs output and ps input are not the same
  90             in shader varying */
  91          GLuint index;
  92          if (j > FRAG_ATTRIB_VAR0)
  93              index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
  94          else
  95              index = j;
  96          nr_interp_regs++;
  97          prealloc_reg(c, &c->payload.input_interp[index], i++);
  98       }
  99    }
 100
 101    assert(nr_interp_regs >= 1);
 102
 103    c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
 104    c->prog_data.urb_read_length = nr_interp_regs * 2;
 105    c->prog_data.curb_read_length = c->nr_creg * 2;
 106
 107    c->max_wm_grf = i * 2;
 108 }
 109
 110
 111 /* Update the nextuse value for each register in our file.
 112  */
 113 static void update_register_usage(struct brw_wm_compile *c,
 114                                   GLuint thisinsn)
 115 {
 116    GLuint i;
 117
 118    for (i = 1; i < c->grf_limit; i++) {
 119       struct brw_wm_grf *grf = &c->pass2_grf[i];
 120
 121       /* Only search those which can change:
 122        */
 123       if (grf->nextuse < thisinsn) {
 124          const struct brw_wm_ref *ref = grf->value->lastuse;
 125
 126          /* Has last use of value been passed?
 127           */
 128          if (ref->insn < thisinsn) {
 129             grf->value->resident = 0;
 130             grf->value = 0;
 131             grf->nextuse = BRW_WM_MAX_INSN;
 132          }
 133          else {
 134             /* Else loop through chain to update:
 135              */
 136             while (ref->prevuse && ref->prevuse->insn >= thisinsn)
 137                ref = ref->prevuse;
 138
 139             grf->nextuse = ref->insn;
 140          }
 141       }
 142    }
 143 }
 144
 145
 146 static void spill_value(struct brw_wm_compile *c,
 147                         struct brw_wm_value *value)
 148 {
 149    /* Allocate a spill slot.  Note that allocations start from 0x40 -
 150     * the first slot is reserved to mean "undef" in brw_wm_emit.c
 151     */
 152    if (!value->spill_slot) {
 153       c->last_scratch += 0x40;
 154       value->spill_slot = c->last_scratch;
 155    }
 156
 157    /* The spill will be done in brw_wm_emit.c immediately after the
 158     * value is calculated, so we can just take this reg without any
 159     * further work.
 160     */
 161    value->resident->value = NULL;
 162    value->resident->nextuse = BRW_WM_MAX_INSN;
 163    value->resident = NULL;
 164 }
 165
 166
 167
 168 /* Search for contiguous region with the most distant nearest
 169  * member.  Free regs count as very distant.
 170  *
 171  * TODO: implement spill-to-reg so that we can rearrange discontigous
 172  * free regs and then spill the oldest non-free regs in sequence.
 173  * This would mean inserting instructions in this pass.
 174  */
 175 static GLuint search_contiguous_regs(struct brw_wm_compile *c,
 176                                      GLuint nr,
 177                                      GLuint thisinsn)
 178 {
 179    struct brw_wm_grf *grf = c->pass2_grf;
 180    GLuint furthest = 0;
 181    GLuint reg = 0;
 182    GLuint i, j;
 183
 184    /* Start search at 1: r0 is special and can't be used or spilled.
 185     */
 186    for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) {
 187       GLuint group_nextuse = BRW_WM_MAX_INSN;
 188
 189       for (j = 0; j < nr; j++) {
 190          if (grf[i+j].nextuse < group_nextuse)
 191             group_nextuse = grf[i+j].nextuse;
 192       }
 193
 194       if (group_nextuse > furthest) {
 195          furthest = group_nextuse;
 196          reg = i;
 197       }
 198    }
 199
 200    assert(furthest != thisinsn);
 201
 202    /* Any non-empty regs will need to be spilled:
 203     */
 204    for (j = 0; j < nr; j++)
 205       if (grf[reg+j].value)
 206          spill_value(c, grf[reg+j].value);
 207
 208    return reg;
 209 }
 210
 211
 212 static void alloc_contiguous_dest(struct brw_wm_compile *c,
 213                                   struct brw_wm_value *dst[],
 214                                   GLuint nr,
 215                                   GLuint thisinsn)
 216 {
 217    GLuint reg = search_contiguous_regs(c, nr, thisinsn);
 218    GLuint i;
 219
 220    for (i = 0; i < nr; i++) {
 221       if (!dst[i]) {
 222          /* Need to grab a dummy value in TEX case.  Don't introduce
 223           * it into the tracking scheme.
 224           */
 225          dst[i] = &c->vreg[c->nr_vreg++];
 226       }
 227       else {
 228          assert(!dst[i]->resident);
 229          assert(c->pass2_grf[reg+i].nextuse != thisinsn);
 230
 231          c->pass2_grf[reg+i].value = dst[i];
 232          c->pass2_grf[reg+i].nextuse = thisinsn;
 233
 234          dst[i]->resident = &c->pass2_grf[reg+i];
 235       }
 236
 237       dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0);
 238    }
 239
 240    if ((reg+nr)*2 > c->max_wm_grf)
 241       c->max_wm_grf = (reg+nr) * 2;
 242 }
 243
 244
 245 static void load_args(struct brw_wm_compile *c,
 246                       struct brw_wm_instruction *inst)
 247 {
 248    GLuint thisinsn = inst - c->instruction;
 249    GLuint i,j;
 250
 251    for (i = 0; i < 3; i++) {
 252       for (j = 0; j < 4; j++) {
 253          struct brw_wm_ref *ref = inst->src[i][j];
 254
 255          if (ref) {
 256             if (!ref->value->resident) {
 257                /* Need to bring the value in from scratch space.  The code for
 258                 * this will be done in brw_wm_emit.c, here we just do the
 259                 * register allocation and mark the ref as requiring a fill.
 260                 */
 261                GLuint reg = search_contiguous_regs(c, 1, thisinsn);
 262
 263                c->pass2_grf[reg].value = ref->value;
 264                c->pass2_grf[reg].nextuse = thisinsn;
 265
 266                ref->value->resident = &c->pass2_grf[reg];
 267
 268                /* Note that a fill is required:
 269                 */
 270                ref->unspill_reg = reg*2;
 271             }
 272
 273             /* Adjust the hw_reg to point at the value's current location:
 274              */
 275             assert(ref->value == ref->value->resident->value);
 276             ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2;
 277          }
 278       }
 279    }
 280 }
 281
 282
 283
 284 /* Step 3: Work forwards once again.  Perform register allocations,
 285  * taking into account instructions like TEX which require contiguous
 286  * result registers.  Where necessary spill registers to scratch space
 287  * and reload later.
 288  */
 289 void brw_wm_pass2( struct brw_wm_compile *c )
 290 {
 291    GLuint insn;
 292    GLuint i;
 293
 294    init_registers(c);
 295
 296    for (insn = 0; insn < c->nr_insns; insn++) {
 297       struct brw_wm_instruction *inst = &c->instruction[insn];
 298
 299       /* Update registers' nextuse values:
 300        */
 301       update_register_usage(c, insn);
 302
 303       /* May need to unspill some args.
 304        */
 305       load_args(c, inst);
 306
 307       /* Allocate registers to hold results:
 308        */
 309       switch (inst->opcode) {
 310       case OPCODE_TEX:
 311       case OPCODE_TXB:
 312       case OPCODE_TXP:
 313          alloc_contiguous_dest(c, inst->dst, 4, insn);
 314          break;
 315
 316       default:
 317          for (i = 0; i < 4; i++) {
 318             if (inst->writemask & (1<<i)) {
 319                assert(inst->dst[i]);
 320                alloc_contiguous_dest(c, &inst->dst[i], 1, insn);
 321             }
 322          }
 323          break;
 324       }
 325
 326       if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) {
 327          for (i = 0; i < 4; i++)
 328             if (inst->dst[i])
 329                spill_value(c, inst->dst[i]);
 330       }
 331    }
 332
 333    if (INTEL_DEBUG & DEBUG_WM) {
 334       brw_wm_print_program(c, "pass2");
 335    }
 336
 337    c->state = PASS2_DONE;
 338
 339    if (INTEL_DEBUG & DEBUG_WM) {
 340        brw_wm_print_program(c, "pass2/done");
 341    }
 342 }