2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
44 static void spill_value(struct brw_wm_compile
*c
,
45 struct brw_wm_value
*value
);
47 static void prealloc_reg(struct brw_wm_compile
*c
,
48 struct brw_wm_value
*value
,
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
55 c
->pass2_grf
[reg
].value
= value
;
56 c
->pass2_grf
[reg
].nextuse
= 0;
58 value
->resident
= &c
->pass2_grf
[reg
];
59 value
->hw_reg
= brw_vec8_grf(reg
*2, 0);
61 if (TEST_PAYLOAD_SPILLS
)
62 spill_value(c
, value
);
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
70 static void init_registers( struct brw_wm_compile
*c
)
72 GLuint inputs
= FRAG_BIT_WPOS
| c
->fp_interp_emitted
;
73 GLuint nr_interp_regs
= 0;
77 for (j
= 0; j
< c
->grf_limit
; j
++)
78 c
->pass2_grf
[j
].nextuse
= BRW_WM_MAX_INSN
;
80 for (j
= 0; j
< c
->key
.nr_depth_regs
; j
++)
81 prealloc_reg(c
, &c
->payload
.depth
[j
], i
++);
83 for (j
= 0; j
< c
->nr_creg
; j
++)
84 prealloc_reg(c
, &c
->creg
[j
], i
++);
86 for (j
= 0; j
< FRAG_ATTRIB_MAX
; j
++)
87 if (inputs
& (1<<j
)) {
89 prealloc_reg(c
, &c
->payload
.input_interp
[j
], i
++);
92 assert(nr_interp_regs
>= 1);
94 c
->prog_data
.first_curbe_grf
= c
->key
.nr_depth_regs
* 2;
95 c
->prog_data
.urb_read_length
= nr_interp_regs
* 2;
96 c
->prog_data
.curb_read_length
= c
->nr_creg
* 2;
98 c
->max_wm_grf
= i
* 2;
102 /* Update the nextuse value for each register in our file.
104 static void update_register_usage(struct brw_wm_compile
*c
,
109 for (i
= 1; i
< c
->grf_limit
; i
++) {
110 struct brw_wm_grf
*grf
= &c
->pass2_grf
[i
];
112 /* Only search those which can change:
114 if (grf
->nextuse
< thisinsn
) {
115 struct brw_wm_ref
*ref
= grf
->value
->lastuse
;
117 /* Has last use of value been passed?
119 if (ref
->insn
< thisinsn
) {
120 grf
->value
->resident
= 0;
122 grf
->nextuse
= BRW_WM_MAX_INSN
;
125 /* Else loop through chain to update:
127 while (ref
->prevuse
&& ref
->prevuse
->insn
>= thisinsn
)
130 grf
->nextuse
= ref
->insn
;
137 static void spill_value(struct brw_wm_compile
*c
,
138 struct brw_wm_value
*value
)
140 /* Allocate a spill slot. Note that allocations start from 0x40 -
141 * the first slot is reserved to mean "undef" in brw_wm_emit.c
143 if (!value
->spill_slot
) {
144 c
->last_scratch
+= 0x40;
145 value
->spill_slot
= c
->last_scratch
;
148 /* The spill will be done in brw_wm_emit.c immediately after the
149 * value is calculated, so we can just take this reg without any
152 value
->resident
->value
= NULL
;
153 value
->resident
->nextuse
= BRW_WM_MAX_INSN
;
154 value
->resident
= NULL
;
159 /* Search for contiguous region with the most distant nearest
160 * member. Free regs count as very distant.
162 * TODO: implement spill-to-reg so that we can rearrange discontigous
163 * free regs and then spill the oldest non-free regs in sequence.
164 * This would mean inserting instructions in this pass.
166 static GLuint
search_contiguous_regs(struct brw_wm_compile
*c
,
170 struct brw_wm_grf
*grf
= c
->pass2_grf
;
175 /* Start search at 1: r0 is special and can't be used or spilled.
177 for (i
= 1; i
< c
->grf_limit
&& furthest
< BRW_WM_MAX_INSN
; i
++) {
178 GLuint group_nextuse
= BRW_WM_MAX_INSN
;
180 for (j
= 0; j
< nr
; j
++) {
181 if (grf
[i
+j
].nextuse
< group_nextuse
)
182 group_nextuse
= grf
[i
+j
].nextuse
;
185 if (group_nextuse
> furthest
) {
186 furthest
= group_nextuse
;
191 assert(furthest
!= thisinsn
);
193 /* Any non-empty regs will need to be spilled:
195 for (j
= 0; j
< nr
; j
++)
196 if (grf
[reg
+j
].value
)
197 spill_value(c
, grf
[reg
+j
].value
);
203 static void alloc_contiguous_dest(struct brw_wm_compile
*c
,
204 struct brw_wm_value
*dst
[],
208 GLuint reg
= search_contiguous_regs(c
, nr
, thisinsn
);
211 for (i
= 0; i
< nr
; i
++) {
213 /* Need to grab a dummy value in TEX case. Don't introduce
214 * it into the tracking scheme.
216 dst
[i
] = &c
->vreg
[c
->nr_vreg
++];
219 assert(!dst
[i
]->resident
);
220 assert(c
->pass2_grf
[reg
+i
].nextuse
!= thisinsn
);
222 c
->pass2_grf
[reg
+i
].value
= dst
[i
];
223 c
->pass2_grf
[reg
+i
].nextuse
= thisinsn
;
225 dst
[i
]->resident
= &c
->pass2_grf
[reg
+i
];
228 dst
[i
]->hw_reg
= brw_vec8_grf((reg
+i
)*2, 0);
231 if ((reg
+nr
)*2 > c
->max_wm_grf
)
232 c
->max_wm_grf
= (reg
+nr
) * 2;
236 static void load_args(struct brw_wm_compile
*c
,
237 struct brw_wm_instruction
*inst
)
239 GLuint thisinsn
= inst
- c
->instruction
;
242 for (i
= 0; i
< 3; i
++) {
243 for (j
= 0; j
< 4; j
++) {
244 struct brw_wm_ref
*ref
= inst
->src
[i
][j
];
247 if (!ref
->value
->resident
) {
248 /* Need to bring the value in from scratch space. The code for
249 * this will be done in brw_wm_emit.c, here we just do the
250 * register allocation and mark the ref as requiring a fill.
252 GLuint reg
= search_contiguous_regs(c
, 1, thisinsn
);
254 c
->pass2_grf
[reg
].value
= ref
->value
;
255 c
->pass2_grf
[reg
].nextuse
= thisinsn
;
257 ref
->value
->resident
= &c
->pass2_grf
[reg
];
259 /* Note that a fill is required:
261 ref
->unspill_reg
= reg
*2;
264 /* Adjust the hw_reg to point at the value's current location:
266 assert(ref
->value
== ref
->value
->resident
->value
);
267 ref
->hw_reg
.nr
+= (ref
->value
->resident
- c
->pass2_grf
) * 2;
275 /* Step 3: Work forwards once again. Perform register allocations,
276 * taking into account instructions like TEX which require contiguous
277 * result registers. Where necessary spill registers to scratch space
280 void brw_wm_pass2( struct brw_wm_compile
*c
)
287 for (insn
= 0; insn
< c
->nr_insns
; insn
++) {
288 struct brw_wm_instruction
*inst
= &c
->instruction
[insn
];
290 /* Update registers' nextuse values:
292 update_register_usage(c
, insn
);
294 /* May need to unspill some args.
298 /* Allocate registers to hold results:
300 switch (inst
->opcode
) {
304 alloc_contiguous_dest(c
, inst
->dst
, 4, insn
);
308 for (i
= 0; i
< 4; i
++) {
309 if (inst
->writemask
& (1<<i
)) {
310 assert(inst
->dst
[i
]);
311 alloc_contiguous_dest(c
, &inst
->dst
[i
], 1, insn
);
317 if (TEST_DST_SPILLS
&& inst
->opcode
!= WM_PIXELXY
)
318 for (i
= 0; i
< 4; i
++)
320 spill_value(c
, inst
->dst
[i
]);
324 if (INTEL_DEBUG
& DEBUG_WM
) {
325 brw_wm_print_program(c
, "pass2");
328 c
->state
= PASS2_DONE
;
330 if (INTEL_DEBUG
& DEBUG_WM
) {
331 brw_wm_print_program(c
, "pass2/done");