2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
44 static void spill_value(struct brw_wm_compile
*c
,
45 struct brw_wm_value
*value
);
47 static void prealloc_reg(struct brw_wm_compile
*c
,
48 struct brw_wm_value
*value
,
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
55 c
->pass2_grf
[reg
].value
= value
;
56 c
->pass2_grf
[reg
].nextuse
= 0;
58 value
->resident
= &c
->pass2_grf
[reg
];
59 value
->hw_reg
= brw_vec8_grf(reg
*2, 0);
61 if (TEST_PAYLOAD_SPILLS
)
62 spill_value(c
, value
);
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
70 static void init_registers( struct brw_wm_compile
*c
)
72 struct brw_context
*brw
= c
->func
.brw
;
73 GLuint inputs
= (brw
->vs
.prog_data
->outputs_written
& DO_SETUP_BITS
);
74 GLuint nr_interp_regs
= 0;
78 for (j
= 0; j
< c
->grf_limit
; j
++)
79 c
->pass2_grf
[j
].nextuse
= BRW_WM_MAX_INSN
;
81 for (j
= 0; j
< c
->key
.nr_depth_regs
; j
++)
82 prealloc_reg(c
, &c
->payload
.depth
[j
], i
++);
84 for (j
= 0; j
< c
->nr_creg
; j
++)
85 prealloc_reg(c
, &c
->creg
[j
], i
++);
87 for (j
= 0; j
< FRAG_ATTRIB_MAX
; j
++)
88 if (inputs
& (1<<j
)) {
89 /* index for vs output and ps input are not the same
92 if (j
> FRAG_ATTRIB_VAR0
)
93 index
= j
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
97 prealloc_reg(c
, &c
->payload
.input_interp
[index
], i
++);
100 assert(nr_interp_regs
>= 1);
102 c
->prog_data
.first_curbe_grf
= c
->key
.nr_depth_regs
* 2;
103 c
->prog_data
.urb_read_length
= nr_interp_regs
* 2;
104 c
->prog_data
.curb_read_length
= c
->nr_creg
* 2;
106 c
->max_wm_grf
= i
* 2;
110 /* Update the nextuse value for each register in our file.
112 static void update_register_usage(struct brw_wm_compile
*c
,
117 for (i
= 1; i
< c
->grf_limit
; i
++) {
118 struct brw_wm_grf
*grf
= &c
->pass2_grf
[i
];
120 /* Only search those which can change:
122 if (grf
->nextuse
< thisinsn
) {
123 struct brw_wm_ref
*ref
= grf
->value
->lastuse
;
125 /* Has last use of value been passed?
127 if (ref
->insn
< thisinsn
) {
128 grf
->value
->resident
= 0;
130 grf
->nextuse
= BRW_WM_MAX_INSN
;
133 /* Else loop through chain to update:
135 while (ref
->prevuse
&& ref
->prevuse
->insn
>= thisinsn
)
138 grf
->nextuse
= ref
->insn
;
145 static void spill_value(struct brw_wm_compile
*c
,
146 struct brw_wm_value
*value
)
148 /* Allocate a spill slot. Note that allocations start from 0x40 -
149 * the first slot is reserved to mean "undef" in brw_wm_emit.c
151 if (!value
->spill_slot
) {
152 c
->last_scratch
+= 0x40;
153 value
->spill_slot
= c
->last_scratch
;
156 /* The spill will be done in brw_wm_emit.c immediately after the
157 * value is calculated, so we can just take this reg without any
160 value
->resident
->value
= NULL
;
161 value
->resident
->nextuse
= BRW_WM_MAX_INSN
;
162 value
->resident
= NULL
;
167 /* Search for contiguous region with the most distant nearest
168 * member. Free regs count as very distant.
170 * TODO: implement spill-to-reg so that we can rearrange discontigous
171 * free regs and then spill the oldest non-free regs in sequence.
172 * This would mean inserting instructions in this pass.
174 static GLuint
search_contiguous_regs(struct brw_wm_compile
*c
,
178 struct brw_wm_grf
*grf
= c
->pass2_grf
;
183 /* Start search at 1: r0 is special and can't be used or spilled.
185 for (i
= 1; i
< c
->grf_limit
&& furthest
< BRW_WM_MAX_INSN
; i
++) {
186 GLuint group_nextuse
= BRW_WM_MAX_INSN
;
188 for (j
= 0; j
< nr
; j
++) {
189 if (grf
[i
+j
].nextuse
< group_nextuse
)
190 group_nextuse
= grf
[i
+j
].nextuse
;
193 if (group_nextuse
> furthest
) {
194 furthest
= group_nextuse
;
199 assert(furthest
!= thisinsn
);
201 /* Any non-empty regs will need to be spilled:
203 for (j
= 0; j
< nr
; j
++)
204 if (grf
[reg
+j
].value
)
205 spill_value(c
, grf
[reg
+j
].value
);
211 static void alloc_contiguous_dest(struct brw_wm_compile
*c
,
212 struct brw_wm_value
*dst
[],
216 GLuint reg
= search_contiguous_regs(c
, nr
, thisinsn
);
219 for (i
= 0; i
< nr
; i
++) {
221 /* Need to grab a dummy value in TEX case. Don't introduce
222 * it into the tracking scheme.
224 dst
[i
] = &c
->vreg
[c
->nr_vreg
++];
227 assert(!dst
[i
]->resident
);
228 assert(c
->pass2_grf
[reg
+i
].nextuse
!= thisinsn
);
230 c
->pass2_grf
[reg
+i
].value
= dst
[i
];
231 c
->pass2_grf
[reg
+i
].nextuse
= thisinsn
;
233 dst
[i
]->resident
= &c
->pass2_grf
[reg
+i
];
236 dst
[i
]->hw_reg
= brw_vec8_grf((reg
+i
)*2, 0);
239 if ((reg
+nr
)*2 > c
->max_wm_grf
)
240 c
->max_wm_grf
= (reg
+nr
) * 2;
244 static void load_args(struct brw_wm_compile
*c
,
245 struct brw_wm_instruction
*inst
)
247 GLuint thisinsn
= inst
- c
->instruction
;
250 for (i
= 0; i
< 3; i
++) {
251 for (j
= 0; j
< 4; j
++) {
252 struct brw_wm_ref
*ref
= inst
->src
[i
][j
];
255 if (!ref
->value
->resident
) {
256 /* Need to bring the value in from scratch space. The code for
257 * this will be done in brw_wm_emit.c, here we just do the
258 * register allocation and mark the ref as requiring a fill.
260 GLuint reg
= search_contiguous_regs(c
, 1, thisinsn
);
262 c
->pass2_grf
[reg
].value
= ref
->value
;
263 c
->pass2_grf
[reg
].nextuse
= thisinsn
;
265 ref
->value
->resident
= &c
->pass2_grf
[reg
];
267 /* Note that a fill is required:
269 ref
->unspill_reg
= reg
*2;
272 /* Adjust the hw_reg to point at the value's current location:
274 assert(ref
->value
== ref
->value
->resident
->value
);
275 ref
->hw_reg
.nr
+= (ref
->value
->resident
- c
->pass2_grf
) * 2;
283 /* Step 3: Work forwards once again. Perform register allocations,
284 * taking into account instructions like TEX which require contiguous
285 * result registers. Where necessary spill registers to scratch space
288 void brw_wm_pass2( struct brw_wm_compile
*c
)
295 for (insn
= 0; insn
< c
->nr_insns
; insn
++) {
296 struct brw_wm_instruction
*inst
= &c
->instruction
[insn
];
298 /* Update registers' nextuse values:
300 update_register_usage(c
, insn
);
302 /* May need to unspill some args.
306 /* Allocate registers to hold results:
308 switch (inst
->opcode
) {
312 alloc_contiguous_dest(c
, inst
->dst
, 4, insn
);
316 for (i
= 0; i
< 4; i
++) {
317 if (inst
->writemask
& (1<<i
)) {
318 assert(inst
->dst
[i
]);
319 alloc_contiguous_dest(c
, &inst
->dst
[i
], 1, insn
);
325 if (TEST_DST_SPILLS
&& inst
->opcode
!= WM_PIXELXY
)
326 for (i
= 0; i
< 4; i
++)
328 spill_value(c
, inst
->dst
[i
]);
332 if (INTEL_DEBUG
& DEBUG_WM
) {
333 brw_wm_print_program(c
, "pass2");
336 c
->state
= PASS2_DONE
;
338 if (INTEL_DEBUG
& DEBUG_WM
) {
339 brw_wm_print_program(c
, "pass2/done");