2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
39 /***********************************************************************
40 * WM unit - fragment programs and rasterization
43 struct brw_wm_unit_key
{
44 unsigned int total_grf
, total_scratch
;
45 unsigned int urb_entry_read_length
;
46 unsigned int curb_entry_read_length
;
47 unsigned int dispatch_grf_start_reg
;
49 unsigned int curbe_offset
;
50 unsigned int urb_size
;
52 unsigned int nr_surfaces
, sampler_count
;
53 GLboolean uses_depth
, computes_depth
, uses_kill
, is_glsl
;
54 GLboolean polygon_stipple
, stats_wm
, line_stipple
, offset_enable
;
55 GLfloat offset_units
, offset_factor
;
59 wm_unit_populate_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
)
61 GLcontext
*ctx
= &brw
->intel
.ctx
;
62 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
63 const struct brw_fragment_program
*bfp
= (struct brw_fragment_program
*) fp
;
64 struct intel_context
*intel
= &brw
->intel
;
66 memset(key
, 0, sizeof(*key
));
68 /* CACHE_NEW_WM_PROG */
69 key
->total_grf
= brw
->wm
.prog_data
->total_grf
;
70 key
->urb_entry_read_length
= brw
->wm
.prog_data
->urb_read_length
;
71 key
->curb_entry_read_length
= brw
->wm
.prog_data
->curb_read_length
;
72 key
->dispatch_grf_start_reg
= brw
->wm
.prog_data
->first_curbe_grf
;
73 key
->total_scratch
= ALIGN(brw
->wm
.prog_data
->total_scratch
, 1024);
75 /* BRW_NEW_URB_FENCE */
76 key
->urb_size
= brw
->urb
.vsize
;
78 /* BRW_NEW_CURBE_OFFSETS */
79 key
->curbe_offset
= brw
->curbe
.wm_start
;
81 /* BRW_NEW_NR_SURFACEs */
82 key
->nr_surfaces
= brw
->wm
.nr_surfaces
;
84 /* CACHE_NEW_SAMPLER */
85 key
->sampler_count
= brw
->wm
.sampler_count
;
87 /* _NEW_POLYGONSTIPPLE */
88 key
->polygon_stipple
= ctx
->Polygon
.StippleFlag
;
90 /* BRW_NEW_FRAGMENT_PROGRAM */
91 key
->uses_depth
= (fp
->Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
)) != 0;
93 /* as far as we can tell */
95 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) != 0;
96 /* BRW_NEW_DEPTH_BUFFER
97 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
100 if (brw
->state
.depth_region
== NULL
)
101 key
->computes_depth
= 0;
104 key
->uses_kill
= fp
->UsesKill
|| ctx
->Color
.AlphaEnabled
;
105 key
->is_glsl
= bfp
->isGLSL
;
107 /* temporary sanity check assertion */
108 ASSERT(bfp
->isGLSL
== brw_wm_is_glsl(fp
));
111 key
->stats_wm
= intel
->stats_wm
;
114 key
->line_stipple
= ctx
->Line
.StippleFlag
;
117 key
->offset_enable
= ctx
->Polygon
.OffsetFill
;
118 key
->offset_units
= ctx
->Polygon
.OffsetUnits
;
119 key
->offset_factor
= ctx
->Polygon
.OffsetFactor
;
123 * Setup wm hardware state. See page 225 of Volume 2
126 wm_unit_create_from_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
,
129 struct intel_context
*intel
= &brw
->intel
;
130 struct brw_wm_unit_state wm
;
133 memset(&wm
, 0, sizeof(wm
));
135 wm
.thread0
.grf_reg_count
= ALIGN(key
->total_grf
, 16) / 16 - 1;
136 wm
.thread0
.kernel_start_pointer
= brw
->wm
.prog_bo
->offset
>> 6; /* reloc */
137 wm
.thread1
.depth_coef_urb_read_offset
= 1;
138 wm
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
141 wm
.thread1
.binding_table_entry_count
= 0; /* hardware requirement */
143 wm
.thread1
.binding_table_entry_count
= key
->nr_surfaces
;
145 if (key
->total_scratch
!= 0) {
146 wm
.thread2
.scratch_space_base_pointer
=
147 brw
->wm
.scratch_bo
->offset
>> 10; /* reloc */
148 wm
.thread2
.per_thread_scratch_space
= key
->total_scratch
/ 1024 - 1;
150 wm
.thread2
.scratch_space_base_pointer
= 0;
151 wm
.thread2
.per_thread_scratch_space
= 0;
154 wm
.thread3
.dispatch_grf_start_reg
= key
->dispatch_grf_start_reg
;
155 wm
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
156 wm
.thread3
.urb_entry_read_offset
= 0;
157 wm
.thread3
.const_urb_entry_read_length
= key
->curb_entry_read_length
;
158 wm
.thread3
.const_urb_entry_read_offset
= key
->curbe_offset
* 2;
161 wm
.wm4
.sampler_count
= 0; /* hardware requirement */
163 wm
.wm4
.sampler_count
= (key
->sampler_count
+ 1) / 4;
165 if (brw
->wm
.sampler_bo
!= NULL
) {
167 wm
.wm4
.sampler_state_pointer
= brw
->wm
.sampler_bo
->offset
>> 5;
169 wm
.wm4
.sampler_state_pointer
= 0;
172 wm
.wm5
.program_uses_depth
= key
->uses_depth
;
173 wm
.wm5
.program_computes_depth
= key
->computes_depth
;
174 wm
.wm5
.program_uses_killpixel
= key
->uses_kill
;
177 wm
.wm5
.enable_8_pix
= 1;
179 wm
.wm5
.enable_16_pix
= 1;
181 wm
.wm5
.max_threads
= brw
->wm_max_threads
- 1;
182 wm
.wm5
.thread_dispatch_enable
= 1; /* AKA: color_write */
183 wm
.wm5
.legacy_line_rast
= 0;
184 wm
.wm5
.legacy_global_depth_bias
= 0;
185 wm
.wm5
.early_depth_test
= 1; /* never need to disable */
186 wm
.wm5
.line_aa_region_width
= 0;
187 wm
.wm5
.line_endcap_aa_region_width
= 1;
189 wm
.wm5
.polygon_stipple
= key
->polygon_stipple
;
191 if (key
->offset_enable
) {
192 wm
.wm5
.depth_offset
= 1;
193 /* Something wierd going on with legacy_global_depth_bias,
194 * offset_constant, scaling and MRD. This value passes glean
195 * but gives some odd results elsewere (eg. the
196 * quad-offset-units test).
198 wm
.global_depth_offset_constant
= key
->offset_units
* 2;
200 /* This is the only value that passes glean:
202 wm
.global_depth_offset_scale
= key
->offset_factor
;
205 wm
.wm5
.line_stipple
= key
->line_stipple
;
207 if (INTEL_DEBUG
& DEBUG_STATS
|| key
->stats_wm
)
208 wm
.wm4
.stats_enable
= 1;
210 bo
= brw_upload_cache(&brw
->cache
, BRW_WM_UNIT
,
215 /* Emit WM program relocation */
216 dri_bo_emit_reloc(bo
,
217 I915_GEM_DOMAIN_INSTRUCTION
, 0,
218 wm
.thread0
.grf_reg_count
<< 1,
219 offsetof(struct brw_wm_unit_state
, thread0
),
222 /* Emit scratch space relocation */
223 if (key
->total_scratch
!= 0) {
224 dri_bo_emit_reloc(bo
,
226 wm
.thread2
.per_thread_scratch_space
,
227 offsetof(struct brw_wm_unit_state
, thread2
),
231 /* Emit sampler state relocation */
232 if (key
->sampler_count
!= 0) {
233 dri_bo_emit_reloc(bo
,
234 I915_GEM_DOMAIN_INSTRUCTION
, 0,
235 wm
.wm4
.stats_enable
| (wm
.wm4
.sampler_count
<< 2),
236 offsetof(struct brw_wm_unit_state
, wm4
),
244 static void upload_wm_unit( struct brw_context
*brw
)
246 struct intel_context
*intel
= &brw
->intel
;
247 struct brw_wm_unit_key key
;
248 dri_bo
*reloc_bufs
[3];
249 wm_unit_populate_key(brw
, &key
);
251 /* Allocate the necessary scratch space if we haven't already. Don't
252 * bother reducing the allocation later, since we use scratch so
255 assert(key
.total_scratch
<= 12 * 1024);
256 if (key
.total_scratch
) {
257 GLuint total
= key
.total_scratch
* brw
->wm_max_threads
;
259 if (brw
->wm
.scratch_bo
&& total
> brw
->wm
.scratch_bo
->size
) {
260 dri_bo_unreference(brw
->wm
.scratch_bo
);
261 brw
->wm
.scratch_bo
= NULL
;
263 if (brw
->wm
.scratch_bo
== NULL
) {
264 brw
->wm
.scratch_bo
= dri_bo_alloc(intel
->bufmgr
,
271 reloc_bufs
[0] = brw
->wm
.prog_bo
;
272 reloc_bufs
[1] = brw
->wm
.scratch_bo
;
273 reloc_bufs
[2] = brw
->wm
.sampler_bo
;
275 dri_bo_unreference(brw
->wm
.state_bo
);
276 brw
->wm
.state_bo
= brw_search_cache(&brw
->cache
, BRW_WM_UNIT
,
280 if (brw
->wm
.state_bo
== NULL
) {
281 brw
->wm
.state_bo
= wm_unit_create_from_key(brw
, &key
, reloc_bufs
);
285 const struct brw_tracked_state brw_wm_unit
= {
287 .mesa
= (_NEW_POLYGON
|
288 _NEW_POLYGONSTIPPLE
|
293 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
294 BRW_NEW_CURBE_OFFSETS
|
295 BRW_NEW_DEPTH_BUFFER
|
296 BRW_NEW_NR_WM_SURFACES
),
298 .cache
= (CACHE_NEW_WM_PROG
|
301 .prepare
= upload_wm_unit
,