src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_fbo.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 bool
  45 brw_color_buffer_write_enabled(struct brw_context *brw)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    /* BRW_NEW_FRAGMENT_PROGRAM */
  49    const struct gl_fragment_program *fp = brw->fragment_program;
  50    int i;
  51
  52    /* _NEW_BUFFERS */
  53    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  54       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  55
  56       /* _NEW_COLOR */
  57       if (rb &&
  58           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  59            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  60           (ctx->Color.ColorMask[i][0] ||
  61            ctx->Color.ColorMask[i][1] ||
  62            ctx->Color.ColorMask[i][2] ||
  63            ctx->Color.ColorMask[i][3])) {
  64          return true;
  65       }
  66    }
  67
  68    return false;
  69 }
  70
  71 /**
  72  * Setup wm hardware state.  See page 225 of Volume 2
  73  */
  74 static void
  75 brw_upload_wm_unit(struct brw_context *brw)
  76 {
  77    struct gl_context *ctx = &brw->ctx;
  78    /* BRW_NEW_FRAGMENT_PROGRAM */
  79    const struct gl_fragment_program *fp = brw->fragment_program;
  80    /* CACHE_NEW_WM_PROG */
  81    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  82    struct brw_wm_unit_state *wm;
  83
  84    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  85                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  86    memset(wm, 0, sizeof(*wm));
  87
  88    if (prog_data->prog_offset_16) {
  89       /* These two fields should be the same pre-gen6, which is why we
  90        * only have one hardware field to program for both dispatch
  91        * widths.
  92        */
  93       assert(prog_data->base.dispatch_grf_start_reg ==
  94              prog_data->dispatch_grf_start_reg_16);
  95    }
  96
  97    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
  98    wm->thread0.grf_reg_count = prog_data->reg_blocks;
  99    wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16;
 100
 101    wm->thread0.kernel_start_pointer =
 102       brw_program_reloc(brw,
 103                         brw->wm.base.state_offset +
 104                         offsetof(struct brw_wm_unit_state, thread0),
 105                         brw->wm.base.prog_offset +
 106                         (wm->thread0.grf_reg_count << 1)) >> 6;
 107
 108    wm->wm9.kernel_start_pointer_2 =
 109       brw_program_reloc(brw,
 110                         brw->wm.base.state_offset +
 111                         offsetof(struct brw_wm_unit_state, wm9),
 112                         brw->wm.base.prog_offset +
 113                         prog_data->prog_offset_16 +
 114                         (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 115
 116    wm->thread1.depth_coef_urb_read_offset = 1;
 117    /* Use ALT floating point mode for ARB fragment programs, because they
 118     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 119     * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
 120     * to differentiate between the GLSL and non-GLSL cases.
 121     */
 122    if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 123       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 124    else
 125       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 126
 127    wm->thread1.binding_table_entry_count =
 128       prog_data->base.binding_table.size_bytes / 4;
 129
 130    if (prog_data->base.total_scratch != 0) {
 131       wm->thread2.scratch_space_base_pointer =
 132          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 133       wm->thread2.per_thread_scratch_space =
 134          ffs(prog_data->base.total_scratch) - 11;
 135    } else {
 136       wm->thread2.scratch_space_base_pointer = 0;
 137       wm->thread2.per_thread_scratch_space = 0;
 138    }
 139
 140    wm->thread3.dispatch_grf_start_reg =
 141       prog_data->base.dispatch_grf_start_reg;
 142    wm->thread3.urb_entry_read_length =
 143       prog_data->num_varying_inputs * 2;
 144    wm->thread3.urb_entry_read_offset = 0;
 145    wm->thread3.const_urb_entry_read_length =
 146       prog_data->base.curb_read_length;
 147    /* BRW_NEW_CURBE_OFFSETS */
 148    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 149
 150    if (brw->gen == 5)
 151       wm->wm4.sampler_count = 0; /* hardware requirement */
 152    else {
 153       /* CACHE_NEW_SAMPLER */
 154       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 155    }
 156
 157    if (brw->wm.base.sampler_count) {
 158       /* reloc */
 159       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 160                                        brw->wm.base.sampler_offset) >> 5;
 161    } else {
 162       wm->wm4.sampler_state_pointer = 0;
 163    }
 164
 165    /* BRW_NEW_FRAGMENT_PROGRAM */
 166    wm->wm5.program_uses_depth = (fp->Base.InputsRead &
 167                                  (1 << VARYING_SLOT_POS)) != 0;
 168    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 169                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 170    /* _NEW_BUFFERS
 171     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 172     * Depth field.
 173     */
 174    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 175       wm->wm5.program_computes_depth = 0;
 176
 177    /* _NEW_COLOR */
 178    wm->wm5.program_uses_killpixel =
 179       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 180
 181    wm->wm5.enable_8_pix = 1;
 182    if (prog_data->prog_offset_16)
 183       wm->wm5.enable_16_pix = 1;
 184
 185    wm->wm5.max_threads = brw->max_wm_threads - 1;
 186
 187    /* _NEW_BUFFERS | _NEW_COLOR */
 188    if (brw_color_buffer_write_enabled(brw) ||
 189        wm->wm5.program_uses_killpixel ||
 190        wm->wm5.program_computes_depth) {
 191       wm->wm5.thread_dispatch_enable = 1;
 192    }
 193
 194    wm->wm5.legacy_line_rast = 0;
 195    wm->wm5.legacy_global_depth_bias = 0;
 196    wm->wm5.early_depth_test = 1;                /* never need to disable */
 197    wm->wm5.line_aa_region_width = 0;
 198    wm->wm5.line_endcap_aa_region_width = 1;
 199
 200    /* _NEW_POLYGONSTIPPLE */
 201    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 202
 203    /* _NEW_POLYGON */
 204    if (ctx->Polygon.OffsetFill) {
 205       wm->wm5.depth_offset = 1;
 206       /* Something wierd going on with legacy_global_depth_bias,
 207        * offset_constant, scaling and MRD.  This value passes glean
 208        * but gives some odd results elsewere (eg. the
 209        * quad-offset-units test).
 210        */
 211       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 212
 213       /* This is the only value that passes glean:
 214        */
 215       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 216    }
 217
 218    /* _NEW_LINE */
 219    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 220
 221    /* BRW_NEW_STATS_WM */
 222    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 223       wm->wm4.stats_enable = 1;
 224
 225    /* Emit scratch space relocation */
 226    if (prog_data->base.total_scratch != 0) {
 227       drm_intel_bo_emit_reloc(brw->batch.bo,
 228                               brw->wm.base.state_offset +
 229                               offsetof(struct brw_wm_unit_state, thread2),
 230                               brw->wm.base.scratch_bo,
 231                               wm->thread2.per_thread_scratch_space,
 232                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 233    }
 234
 235    /* Emit sampler state relocation */
 236    if (brw->wm.base.sampler_count != 0) {
 237       drm_intel_bo_emit_reloc(brw->batch.bo,
 238                               brw->wm.base.state_offset +
 239                               offsetof(struct brw_wm_unit_state, wm4),
 240                               brw->batch.bo, (brw->wm.base.sampler_offset |
 241                                               wm->wm4.stats_enable |
 242                                               (wm->wm4.sampler_count << 2)),
 243                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 244    }
 245
 246    brw->state.dirty.cache |= CACHE_NEW_WM_UNIT;
 247 }
 248
 249 const struct brw_tracked_state brw_wm_unit = {
 250    .dirty = {
 251       .mesa = (_NEW_POLYGON |
 252                _NEW_POLYGONSTIPPLE |
 253                _NEW_LINE |
 254                _NEW_COLOR |
 255                _NEW_BUFFERS),
 256
 257       .brw = (BRW_NEW_BATCH |
 258               BRW_NEW_PROGRAM_CACHE |
 259               BRW_NEW_FRAGMENT_PROGRAM |
 260               BRW_NEW_CURBE_OFFSETS |
 261               BRW_NEW_STATS_WM),
 262
 263       .cache = (CACHE_NEW_WM_PROG |
 264                 CACHE_NEW_SAMPLER)
 265    },
 266    .emit = brw_upload_wm_unit,
 267 };
 268