src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40
  41 /***********************************************************************
  42  * WM unit - fragment programs and rasterization
  43  */
  44
  45 bool
  46 brw_color_buffer_write_enabled(struct brw_context *brw)
  47 {
  48    struct gl_context *ctx = &brw->ctx;
  49    /* BRW_NEW_FRAGMENT_PROGRAM */
  50    const struct gl_fragment_program *fp = brw->fragment_program;
  51    unsigned i;
  52
  53    /* _NEW_BUFFERS */
  54    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  55       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  56
  57       /* _NEW_COLOR */
  58       if (rb &&
  59           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  60            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  61           (ctx->Color.ColorMask[i][0] ||
  62            ctx->Color.ColorMask[i][1] ||
  63            ctx->Color.ColorMask[i][2] ||
  64            ctx->Color.ColorMask[i][3])) {
  65          return true;
  66       }
  67    }
  68
  69    return false;
  70 }
  71
  72 /**
  73  * Setup wm hardware state.  See page 225 of Volume 2
  74  */
  75 static void
  76 brw_upload_wm_unit(struct brw_context *brw)
  77 {
  78    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  79    struct gl_context *ctx = &brw->ctx;
  80    /* BRW_NEW_FRAGMENT_PROGRAM */
  81    const struct gl_fragment_program *fp = brw->fragment_program;
  82    /* BRW_NEW_FS_PROG_DATA */
  83    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  84    struct brw_wm_unit_state *wm;
  85
  86    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  87                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  88    memset(wm, 0, sizeof(*wm));
  89
  90    if (prog_data->dispatch_8 && prog_data->dispatch_16) {
  91       /* These two fields should be the same pre-gen6, which is why we
  92        * only have one hardware field to program for both dispatch
  93        * widths.
  94        */
  95       assert(prog_data->base.dispatch_grf_start_reg ==
  96              prog_data->dispatch_grf_start_reg_2);
  97    }
  98
  99    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
 100    wm->wm5.enable_8_pix = prog_data->dispatch_8;
 101    wm->wm5.enable_16_pix = prog_data->dispatch_16;
 102
 103    if (prog_data->dispatch_8 || prog_data->dispatch_16) {
 104       wm->thread0.grf_reg_count = prog_data->reg_blocks_0;
 105       wm->thread0.kernel_start_pointer =
 106          brw_program_reloc(brw,
 107                            brw->wm.base.state_offset +
 108                            offsetof(struct brw_wm_unit_state, thread0),
 109                            brw->wm.base.prog_offset +
 110                            (wm->thread0.grf_reg_count << 1)) >> 6;
 111    }
 112
 113    if (prog_data->prog_offset_2) {
 114       wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_2;
 115       wm->wm9.kernel_start_pointer_2 =
 116          brw_program_reloc(brw,
 117                            brw->wm.base.state_offset +
 118                            offsetof(struct brw_wm_unit_state, wm9),
 119                            brw->wm.base.prog_offset +
 120                            prog_data->prog_offset_2 +
 121                            (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 122    }
 123
 124    wm->thread1.depth_coef_urb_read_offset = 1;
 125    if (prog_data->base.use_alt_mode)
 126       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 127    else
 128       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 129
 130    wm->thread1.binding_table_entry_count =
 131       prog_data->base.binding_table.size_bytes / 4;
 132
 133    if (prog_data->base.total_scratch != 0) {
 134       wm->thread2.scratch_space_base_pointer =
 135          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 136       wm->thread2.per_thread_scratch_space =
 137          ffs(brw->wm.base.per_thread_scratch) - 11;
 138    } else {
 139       wm->thread2.scratch_space_base_pointer = 0;
 140       wm->thread2.per_thread_scratch_space = 0;
 141    }
 142
 143    wm->thread3.dispatch_grf_start_reg =
 144       prog_data->base.dispatch_grf_start_reg;
 145    wm->thread3.urb_entry_read_length =
 146       prog_data->num_varying_inputs * 2;
 147    wm->thread3.urb_entry_read_offset = 0;
 148    wm->thread3.const_urb_entry_read_length =
 149       prog_data->base.curb_read_length;
 150    /* BRW_NEW_CURBE_OFFSETS */
 151    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 152
 153    if (brw->gen == 5)
 154       wm->wm4.sampler_count = 0; /* hardware requirement */
 155    else {
 156       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 157    }
 158
 159    if (brw->wm.base.sampler_count) {
 160       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 161       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 162                                        brw->wm.base.sampler_offset) >> 5;
 163    } else {
 164       wm->wm4.sampler_state_pointer = 0;
 165    }
 166
 167    /* BRW_NEW_FRAGMENT_PROGRAM */
 168    wm->wm5.program_uses_depth = prog_data->uses_src_depth;
 169    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 170                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 171    /* _NEW_BUFFERS
 172     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 173     * Depth field.
 174     */
 175    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 176       wm->wm5.program_computes_depth = 0;
 177
 178    /* _NEW_COLOR */
 179    wm->wm5.program_uses_killpixel =
 180       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 181
 182    wm->wm5.max_threads = devinfo->max_wm_threads - 1;
 183
 184    /* _NEW_BUFFERS | _NEW_COLOR */
 185    if (brw_color_buffer_write_enabled(brw) ||
 186        wm->wm5.program_uses_killpixel ||
 187        wm->wm5.program_computes_depth) {
 188       wm->wm5.thread_dispatch_enable = 1;
 189    }
 190
 191    wm->wm5.legacy_line_rast = 0;
 192    wm->wm5.legacy_global_depth_bias = 0;
 193    wm->wm5.early_depth_test = 1;                /* never need to disable */
 194    wm->wm5.line_aa_region_width = 0;
 195    wm->wm5.line_endcap_aa_region_width = 1;
 196
 197    /* _NEW_POLYGONSTIPPLE */
 198    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 199
 200    /* _NEW_POLYGON */
 201    if (ctx->Polygon.OffsetFill) {
 202       wm->wm5.depth_offset = 1;
 203       /* Something weird going on with legacy_global_depth_bias,
 204        * offset_constant, scaling and MRD.  This value passes glean
 205        * but gives some odd results elsewere (eg. the
 206        * quad-offset-units test).
 207        */
 208       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 209
 210       /* This is the only value that passes glean:
 211        */
 212       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 213    }
 214
 215    /* _NEW_LINE */
 216    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 217
 218    /* BRW_NEW_STATS_WM */
 219    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 220       wm->wm4.stats_enable = 1;
 221
 222    /* Emit scratch space relocation */
 223    if (prog_data->base.total_scratch != 0) {
 224       drm_intel_bo_emit_reloc(brw->batch.bo,
 225                               brw->wm.base.state_offset +
 226                               offsetof(struct brw_wm_unit_state, thread2),
 227                               brw->wm.base.scratch_bo,
 228                               wm->thread2.per_thread_scratch_space,
 229                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 230    }
 231
 232    /* Emit sampler state relocation */
 233    if (brw->wm.base.sampler_count != 0) {
 234       drm_intel_bo_emit_reloc(brw->batch.bo,
 235                               brw->wm.base.state_offset +
 236                               offsetof(struct brw_wm_unit_state, wm4),
 237                               brw->batch.bo, (brw->wm.base.sampler_offset |
 238                                               wm->wm4.stats_enable |
 239                                               (wm->wm4.sampler_count << 2)),
 240                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 241    }
 242
 243    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 244
 245    /* _NEW_POLGYON */
 246    if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
 247       BEGIN_BATCH(2);
 248       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 249       OUT_BATCH_F(ctx->Polygon.OffsetClamp);
 250       ADVANCE_BATCH();
 251
 252       brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
 253    }
 254 }
 255
 256 const struct brw_tracked_state brw_wm_unit = {
 257    .dirty = {
 258       .mesa = _NEW_BUFFERS |
 259               _NEW_COLOR |
 260               _NEW_LINE |
 261               _NEW_POLYGON |
 262               _NEW_POLYGONSTIPPLE,
 263       .brw = BRW_NEW_BATCH |
 264              BRW_NEW_BLORP |
 265              BRW_NEW_CURBE_OFFSETS |
 266              BRW_NEW_FRAGMENT_PROGRAM |
 267              BRW_NEW_FS_PROG_DATA |
 268              BRW_NEW_PROGRAM_CACHE |
 269              BRW_NEW_SAMPLER_STATE_TABLE |
 270              BRW_NEW_STATS_WM,
 271    },
 272    .emit = brw_upload_wm_unit,
 273 };