src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_fbo.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 bool
  45 brw_color_buffer_write_enabled(struct brw_context *brw)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    /* BRW_NEW_FRAGMENT_PROGRAM */
  49    const struct gl_fragment_program *fp = brw->fragment_program;
  50    int i;
  51
  52    /* _NEW_BUFFERS */
  53    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  54       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  55
  56       /* _NEW_COLOR */
  57       if (rb &&
  58           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  59            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  60           (ctx->Color.ColorMask[i][0] ||
  61            ctx->Color.ColorMask[i][1] ||
  62            ctx->Color.ColorMask[i][2] ||
  63            ctx->Color.ColorMask[i][3])) {
  64          return true;
  65       }
  66    }
  67
  68    return false;
  69 }
  70
  71 /**
  72  * Setup wm hardware state.  See page 225 of Volume 2
  73  */
  74 static void
  75 brw_upload_wm_unit(struct brw_context *brw)
  76 {
  77    struct gl_context *ctx = &brw->ctx;
  78    const struct gl_fragment_program *fp = brw->fragment_program;
  79    struct brw_wm_unit_state *wm;
  80
  81    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  82                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  83    memset(wm, 0, sizeof(*wm));
  84
  85    if (brw->wm.prog_data->prog_offset_16) {
  86       /* These two fields should be the same pre-gen6, which is why we
  87        * only have one hardware field to program for both dispatch
  88        * widths.
  89        */
  90       assert(brw->wm.prog_data->base.dispatch_grf_start_reg ==
  91              brw->wm.prog_data->dispatch_grf_start_reg_16);
  92    }
  93
  94    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
  95    wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks;
  96    wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16;
  97
  98    wm->thread0.kernel_start_pointer =
  99       brw_program_reloc(brw,
 100                         brw->wm.base.state_offset +
 101                         offsetof(struct brw_wm_unit_state, thread0),
 102                         brw->wm.base.prog_offset +
 103                         (wm->thread0.grf_reg_count << 1)) >> 6;
 104
 105    wm->wm9.kernel_start_pointer_2 =
 106       brw_program_reloc(brw,
 107                         brw->wm.base.state_offset +
 108                         offsetof(struct brw_wm_unit_state, wm9),
 109                         brw->wm.base.prog_offset +
 110                         brw->wm.prog_data->prog_offset_16 +
 111                         (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 112
 113    wm->thread1.depth_coef_urb_read_offset = 1;
 114    /* Use ALT floating point mode for ARB fragment programs, because they
 115     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 116     * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
 117     * to differentiate between the GLSL and non-GLSL cases.
 118     */
 119    if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 120       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 121    else
 122       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 123
 124    wm->thread1.binding_table_entry_count =
 125       brw->wm.prog_data->base.binding_table.size_bytes / 4;
 126
 127    if (brw->wm.prog_data->total_scratch != 0) {
 128       wm->thread2.scratch_space_base_pointer =
 129          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 130       wm->thread2.per_thread_scratch_space =
 131          ffs(brw->wm.prog_data->total_scratch) - 11;
 132    } else {
 133       wm->thread2.scratch_space_base_pointer = 0;
 134       wm->thread2.per_thread_scratch_space = 0;
 135    }
 136
 137    wm->thread3.dispatch_grf_start_reg =
 138       brw->wm.prog_data->base.dispatch_grf_start_reg;
 139    wm->thread3.urb_entry_read_length =
 140       brw->wm.prog_data->num_varying_inputs * 2;
 141    wm->thread3.urb_entry_read_offset = 0;
 142    wm->thread3.const_urb_entry_read_length =
 143       brw->wm.prog_data->curb_read_length;
 144    /* BRW_NEW_CURBE_OFFSETS */
 145    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 146
 147    if (brw->gen == 5)
 148       wm->wm4.sampler_count = 0; /* hardware requirement */
 149    else {
 150       /* CACHE_NEW_SAMPLER */
 151       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 152    }
 153
 154    if (brw->wm.base.sampler_count) {
 155       /* reloc */
 156       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 157                                        brw->wm.base.sampler_offset) >> 5;
 158    } else {
 159       wm->wm4.sampler_state_pointer = 0;
 160    }
 161
 162    /* BRW_NEW_FRAGMENT_PROGRAM */
 163    wm->wm5.program_uses_depth = (fp->Base.InputsRead &
 164                                  (1 << VARYING_SLOT_POS)) != 0;
 165    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 166                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 167    /* _NEW_BUFFERS
 168     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 169     * Depth field.
 170     */
 171    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 172       wm->wm5.program_computes_depth = 0;
 173
 174    /* _NEW_COLOR */
 175    wm->wm5.program_uses_killpixel = fp->UsesKill || ctx->Color.AlphaEnabled;
 176
 177    wm->wm5.enable_8_pix = 1;
 178    if (brw->wm.prog_data->prog_offset_16)
 179       wm->wm5.enable_16_pix = 1;
 180
 181    wm->wm5.max_threads = brw->max_wm_threads - 1;
 182
 183    /* _NEW_BUFFERS | _NEW_COLOR */
 184    if (brw_color_buffer_write_enabled(brw) ||
 185        wm->wm5.program_uses_killpixel ||
 186        wm->wm5.program_computes_depth) {
 187       wm->wm5.thread_dispatch_enable = 1;
 188    }
 189
 190    wm->wm5.legacy_line_rast = 0;
 191    wm->wm5.legacy_global_depth_bias = 0;
 192    wm->wm5.early_depth_test = 1;                /* never need to disable */
 193    wm->wm5.line_aa_region_width = 0;
 194    wm->wm5.line_endcap_aa_region_width = 1;
 195
 196    /* _NEW_POLYGONSTIPPLE */
 197    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 198
 199    /* _NEW_POLYGON */
 200    if (ctx->Polygon.OffsetFill) {
 201       wm->wm5.depth_offset = 1;
 202       /* Something wierd going on with legacy_global_depth_bias,
 203        * offset_constant, scaling and MRD.  This value passes glean
 204        * but gives some odd results elsewere (eg. the
 205        * quad-offset-units test).
 206        */
 207       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 208
 209       /* This is the only value that passes glean:
 210        */
 211       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 212    }
 213
 214    /* _NEW_LINE */
 215    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 216
 217    /* BRW_NEW_STATS_WM */
 218    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 219       wm->wm4.stats_enable = 1;
 220
 221    /* Emit scratch space relocation */
 222    if (brw->wm.prog_data->total_scratch != 0) {
 223       drm_intel_bo_emit_reloc(brw->batch.bo,
 224                               brw->wm.base.state_offset +
 225                               offsetof(struct brw_wm_unit_state, thread2),
 226                               brw->wm.base.scratch_bo,
 227                               wm->thread2.per_thread_scratch_space,
 228                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 229    }
 230
 231    /* Emit sampler state relocation */
 232    if (brw->wm.base.sampler_count != 0) {
 233       drm_intel_bo_emit_reloc(brw->batch.bo,
 234                               brw->wm.base.state_offset +
 235                               offsetof(struct brw_wm_unit_state, wm4),
 236                               brw->batch.bo, (brw->wm.base.sampler_offset |
 237                                               wm->wm4.stats_enable |
 238                                               (wm->wm4.sampler_count << 2)),
 239                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 240    }
 241
 242    SET_DIRTY_BIT(cache, CACHE_NEW_WM_UNIT);
 243 }
 244
 245 const struct brw_tracked_state brw_wm_unit = {
 246    .dirty = {
 247       .mesa = (_NEW_POLYGON |
 248                _NEW_POLYGONSTIPPLE |
 249                _NEW_LINE |
 250                _NEW_COLOR |
 251                _NEW_BUFFERS),
 252
 253       .brw = (BRW_NEW_BATCH |
 254               BRW_NEW_PROGRAM_CACHE |
 255               BRW_NEW_FRAGMENT_PROGRAM |
 256               BRW_NEW_CURBE_OFFSETS |
 257               BRW_NEW_STATS_WM),
 258
 259       .cache = (CACHE_NEW_WM_PROG |
 260                 CACHE_NEW_SAMPLER)
 261    },
 262    .emit = brw_upload_wm_unit,
 263 };
 264