src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40 #include "compiler/nir/nir.h"
  41
  42 /***********************************************************************
  43  * WM unit - fragment programs and rasterization
  44  */
  45
  46 bool
  47 brw_color_buffer_write_enabled(struct brw_context *brw)
  48 {
  49    struct gl_context *ctx = &brw->ctx;
  50    /* BRW_NEW_FRAGMENT_PROGRAM */
  51    const struct gl_program *fp = brw->fragment_program;
  52    unsigned i;
  53
  54    /* _NEW_BUFFERS */
  55    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  56       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  57       uint64_t outputs_written = fp->info.outputs_written;
  58
  59       /* _NEW_COLOR */
  60       if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  61                  outputs_written & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  62           (ctx->Color.ColorMask[i][0] ||
  63            ctx->Color.ColorMask[i][1] ||
  64            ctx->Color.ColorMask[i][2] ||
  65            ctx->Color.ColorMask[i][3])) {
  66          return true;
  67       }
  68    }
  69
  70    return false;
  71 }
  72
  73 /**
  74  * Setup wm hardware state.  See page 225 of Volume 2
  75  */
  76 static void
  77 brw_upload_wm_unit(struct brw_context *brw)
  78 {
  79    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  80    struct gl_context *ctx = &brw->ctx;
  81    /* BRW_NEW_FRAGMENT_PROGRAM */
  82    const struct gl_program *fp = brw->fragment_program;
  83    /* BRW_NEW_FS_PROG_DATA */
  84    const struct brw_wm_prog_data *prog_data =
  85       brw_wm_prog_data(brw->wm.base.prog_data);
  86    struct brw_wm_unit_state *wm;
  87
  88    wm = brw_state_batch(brw, sizeof(*wm), 32, &brw->wm.base.state_offset);
  89    memset(wm, 0, sizeof(*wm));
  90
  91    if (prog_data->dispatch_8 && prog_data->dispatch_16) {
  92       /* These two fields should be the same pre-gen6, which is why we
  93        * only have one hardware field to program for both dispatch
  94        * widths.
  95        */
  96       assert(prog_data->base.dispatch_grf_start_reg ==
  97              prog_data->dispatch_grf_start_reg_2);
  98    }
  99
 100    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
 101    wm->wm5.enable_8_pix = prog_data->dispatch_8;
 102    wm->wm5.enable_16_pix = prog_data->dispatch_16;
 103
 104    if (prog_data->dispatch_8 || prog_data->dispatch_16) {
 105       wm->thread0.grf_reg_count = prog_data->reg_blocks_0;
 106       wm->thread0.kernel_start_pointer =
 107          brw_program_reloc(brw,
 108                            brw->wm.base.state_offset +
 109                            offsetof(struct brw_wm_unit_state, thread0),
 110                            brw->wm.base.prog_offset +
 111                            (wm->thread0.grf_reg_count << 1)) >> 6;
 112    }
 113
 114    if (prog_data->prog_offset_2) {
 115       wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_2;
 116       wm->wm9.kernel_start_pointer_2 =
 117          brw_program_reloc(brw,
 118                            brw->wm.base.state_offset +
 119                            offsetof(struct brw_wm_unit_state, wm9),
 120                            brw->wm.base.prog_offset +
 121                            prog_data->prog_offset_2 +
 122                            (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 123    }
 124
 125    wm->thread1.depth_coef_urb_read_offset = 1;
 126    if (prog_data->base.use_alt_mode)
 127       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 128    else
 129       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 130
 131    wm->thread1.binding_table_entry_count =
 132       prog_data->base.binding_table.size_bytes / 4;
 133
 134    if (prog_data->base.total_scratch != 0) {
 135       wm->thread2.scratch_space_base_pointer =
 136          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 137       wm->thread2.per_thread_scratch_space =
 138          ffs(brw->wm.base.per_thread_scratch) - 11;
 139    } else {
 140       wm->thread2.scratch_space_base_pointer = 0;
 141       wm->thread2.per_thread_scratch_space = 0;
 142    }
 143
 144    wm->thread3.dispatch_grf_start_reg =
 145       prog_data->base.dispatch_grf_start_reg;
 146    wm->thread3.urb_entry_read_length =
 147       prog_data->num_varying_inputs * 2;
 148    wm->thread3.urb_entry_read_offset = 0;
 149    wm->thread3.const_urb_entry_read_length =
 150       prog_data->base.curb_read_length;
 151    /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
 152    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 153
 154    if (brw->gen == 5)
 155       wm->wm4.sampler_count = 0; /* hardware requirement */
 156    else {
 157       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 158    }
 159
 160    if (brw->wm.base.sampler_count) {
 161       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 162       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 163                                        brw->wm.base.sampler_offset) >> 5;
 164    } else {
 165       wm->wm4.sampler_state_pointer = 0;
 166    }
 167
 168    /* BRW_NEW_FRAGMENT_PROGRAM */
 169    wm->wm5.program_uses_depth = prog_data->uses_src_depth;
 170    wm->wm5.program_computes_depth = (fp->info.outputs_written &
 171                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 172    /* _NEW_BUFFERS
 173     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 174     * Depth field.
 175     */
 176    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 177       wm->wm5.program_computes_depth = 0;
 178
 179    /* _NEW_COLOR */
 180    wm->wm5.program_uses_killpixel =
 181       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 182
 183    wm->wm5.max_threads = devinfo->max_wm_threads - 1;
 184
 185    /* _NEW_BUFFERS | _NEW_COLOR */
 186    if (brw_color_buffer_write_enabled(brw) ||
 187        wm->wm5.program_uses_killpixel ||
 188        wm->wm5.program_computes_depth) {
 189       wm->wm5.thread_dispatch_enable = 1;
 190    }
 191
 192    wm->wm5.legacy_line_rast = 0;
 193    wm->wm5.legacy_global_depth_bias = 0;
 194    wm->wm5.early_depth_test = 1;                /* never need to disable */
 195    wm->wm5.line_aa_region_width = 0;
 196    wm->wm5.line_endcap_aa_region_width = 1;
 197
 198    /* _NEW_POLYGONSTIPPLE */
 199    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 200
 201    /* _NEW_POLYGON */
 202    if (ctx->Polygon.OffsetFill) {
 203       wm->wm5.depth_offset = 1;
 204       /* Something weird going on with legacy_global_depth_bias,
 205        * offset_constant, scaling and MRD.  This value passes glean
 206        * but gives some odd results elsewere (eg. the
 207        * quad-offset-units test).
 208        */
 209       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 210
 211       /* This is the only value that passes glean:
 212        */
 213       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 214    }
 215
 216    /* _NEW_LINE */
 217    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 218
 219    /* BRW_NEW_STATS_WM */
 220    if (brw->stats_wm)
 221       wm->wm4.stats_enable = 1;
 222
 223    /* Emit scratch space relocation */
 224    if (prog_data->base.total_scratch != 0) {
 225       brw_emit_reloc(&brw->batch,
 226                      brw->wm.base.state_offset +
 227                      offsetof(struct brw_wm_unit_state, thread2),
 228                      brw->wm.base.scratch_bo,
 229                      wm->thread2.per_thread_scratch_space,
 230                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 231    }
 232
 233    /* Emit sampler state relocation */
 234    if (brw->wm.base.sampler_count != 0) {
 235       brw_emit_reloc(&brw->batch,
 236                      brw->wm.base.state_offset +
 237                      offsetof(struct brw_wm_unit_state, wm4),
 238                      brw->batch.bo,
 239                      brw->wm.base.sampler_offset | wm->wm4.stats_enable |
 240                      (wm->wm4.sampler_count << 2),
 241                      I915_GEM_DOMAIN_INSTRUCTION, 0);
 242    }
 243
 244    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 245
 246    /* _NEW_POLGYON */
 247    if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
 248       BEGIN_BATCH(2);
 249       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 250       OUT_BATCH_F(ctx->Polygon.OffsetClamp);
 251       ADVANCE_BATCH();
 252
 253       brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
 254    }
 255 }
 256
 257 const struct brw_tracked_state brw_wm_unit = {
 258    .dirty = {
 259       .mesa = _NEW_BUFFERS |
 260               _NEW_COLOR |
 261               _NEW_LINE |
 262               _NEW_POLYGON |
 263               _NEW_POLYGONSTIPPLE,
 264       .brw = BRW_NEW_BATCH |
 265              BRW_NEW_BLORP |
 266              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 267              BRW_NEW_FRAGMENT_PROGRAM |
 268              BRW_NEW_FS_PROG_DATA |
 269              BRW_NEW_PROGRAM_CACHE |
 270              BRW_NEW_SAMPLER_STATE_TABLE |
 271              BRW_NEW_STATS_WM,
 272    },
 273    .emit = brw_upload_wm_unit,
 274 };