src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40 #include "compiler/nir/nir.h"
  41
  42 /***********************************************************************
  43  * WM unit - fragment programs and rasterization
  44  */
  45
  46 bool
  47 brw_color_buffer_write_enabled(struct brw_context *brw)
  48 {
  49    struct gl_context *ctx = &brw->ctx;
  50    /* BRW_NEW_FRAGMENT_PROGRAM */
  51    const struct gl_program *fp = brw->fragment_program;
  52    unsigned i;
  53
  54    /* _NEW_BUFFERS */
  55    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  56       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  57       uint64_t outputs_written = fp->info.outputs_written;
  58
  59       /* _NEW_COLOR */
  60       if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  61                  outputs_written & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  62           (ctx->Color.ColorMask[i][0] ||
  63            ctx->Color.ColorMask[i][1] ||
  64            ctx->Color.ColorMask[i][2] ||
  65            ctx->Color.ColorMask[i][3])) {
  66          return true;
  67       }
  68    }
  69
  70    return false;
  71 }
  72
  73 /**
  74  * Setup wm hardware state.  See page 225 of Volume 2
  75  */
  76 static void
  77 brw_upload_wm_unit(struct brw_context *brw)
  78 {
  79    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  80    struct gl_context *ctx = &brw->ctx;
  81    /* BRW_NEW_FRAGMENT_PROGRAM */
  82    const struct gl_program *fp = brw->fragment_program;
  83    /* BRW_NEW_FS_PROG_DATA */
  84    const struct brw_wm_prog_data *prog_data =
  85       brw_wm_prog_data(brw->wm.base.prog_data);
  86    struct brw_wm_unit_state *wm;
  87
  88    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  89                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  90    memset(wm, 0, sizeof(*wm));
  91
  92    if (prog_data->dispatch_8 && prog_data->dispatch_16) {
  93       /* These two fields should be the same pre-gen6, which is why we
  94        * only have one hardware field to program for both dispatch
  95        * widths.
  96        */
  97       assert(prog_data->base.dispatch_grf_start_reg ==
  98              prog_data->dispatch_grf_start_reg_2);
  99    }
 100
 101    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
 102    wm->wm5.enable_8_pix = prog_data->dispatch_8;
 103    wm->wm5.enable_16_pix = prog_data->dispatch_16;
 104
 105    if (prog_data->dispatch_8 || prog_data->dispatch_16) {
 106       wm->thread0.grf_reg_count = prog_data->reg_blocks_0;
 107       wm->thread0.kernel_start_pointer =
 108          brw_program_reloc(brw,
 109                            brw->wm.base.state_offset +
 110                            offsetof(struct brw_wm_unit_state, thread0),
 111                            brw->wm.base.prog_offset +
 112                            (wm->thread0.grf_reg_count << 1)) >> 6;
 113    }
 114
 115    if (prog_data->prog_offset_2) {
 116       wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_2;
 117       wm->wm9.kernel_start_pointer_2 =
 118          brw_program_reloc(brw,
 119                            brw->wm.base.state_offset +
 120                            offsetof(struct brw_wm_unit_state, wm9),
 121                            brw->wm.base.prog_offset +
 122                            prog_data->prog_offset_2 +
 123                            (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 124    }
 125
 126    wm->thread1.depth_coef_urb_read_offset = 1;
 127    if (prog_data->base.use_alt_mode)
 128       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 129    else
 130       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 131
 132    wm->thread1.binding_table_entry_count =
 133       prog_data->base.binding_table.size_bytes / 4;
 134
 135    if (prog_data->base.total_scratch != 0) {
 136       wm->thread2.scratch_space_base_pointer =
 137          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 138       wm->thread2.per_thread_scratch_space =
 139          ffs(brw->wm.base.per_thread_scratch) - 11;
 140    } else {
 141       wm->thread2.scratch_space_base_pointer = 0;
 142       wm->thread2.per_thread_scratch_space = 0;
 143    }
 144
 145    wm->thread3.dispatch_grf_start_reg =
 146       prog_data->base.dispatch_grf_start_reg;
 147    wm->thread3.urb_entry_read_length =
 148       prog_data->num_varying_inputs * 2;
 149    wm->thread3.urb_entry_read_offset = 0;
 150    wm->thread3.const_urb_entry_read_length =
 151       prog_data->base.curb_read_length;
 152    /* BRW_NEW_CURBE_OFFSETS */
 153    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 154
 155    if (brw->gen == 5)
 156       wm->wm4.sampler_count = 0; /* hardware requirement */
 157    else {
 158       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 159    }
 160
 161    if (brw->wm.base.sampler_count) {
 162       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 163       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 164                                        brw->wm.base.sampler_offset) >> 5;
 165    } else {
 166       wm->wm4.sampler_state_pointer = 0;
 167    }
 168
 169    /* BRW_NEW_FRAGMENT_PROGRAM */
 170    wm->wm5.program_uses_depth = prog_data->uses_src_depth;
 171    wm->wm5.program_computes_depth = (fp->info.outputs_written &
 172                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 173    /* _NEW_BUFFERS
 174     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 175     * Depth field.
 176     */
 177    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 178       wm->wm5.program_computes_depth = 0;
 179
 180    /* _NEW_COLOR */
 181    wm->wm5.program_uses_killpixel =
 182       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 183
 184    wm->wm5.max_threads = devinfo->max_wm_threads - 1;
 185
 186    /* _NEW_BUFFERS | _NEW_COLOR */
 187    if (brw_color_buffer_write_enabled(brw) ||
 188        wm->wm5.program_uses_killpixel ||
 189        wm->wm5.program_computes_depth) {
 190       wm->wm5.thread_dispatch_enable = 1;
 191    }
 192
 193    wm->wm5.legacy_line_rast = 0;
 194    wm->wm5.legacy_global_depth_bias = 0;
 195    wm->wm5.early_depth_test = 1;                /* never need to disable */
 196    wm->wm5.line_aa_region_width = 0;
 197    wm->wm5.line_endcap_aa_region_width = 1;
 198
 199    /* _NEW_POLYGONSTIPPLE */
 200    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 201
 202    /* _NEW_POLYGON */
 203    if (ctx->Polygon.OffsetFill) {
 204       wm->wm5.depth_offset = 1;
 205       /* Something weird going on with legacy_global_depth_bias,
 206        * offset_constant, scaling and MRD.  This value passes glean
 207        * but gives some odd results elsewere (eg. the
 208        * quad-offset-units test).
 209        */
 210       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 211
 212       /* This is the only value that passes glean:
 213        */
 214       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 215    }
 216
 217    /* _NEW_LINE */
 218    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 219
 220    /* BRW_NEW_STATS_WM */
 221    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 222       wm->wm4.stats_enable = 1;
 223
 224    /* Emit scratch space relocation */
 225    if (prog_data->base.total_scratch != 0) {
 226       drm_intel_bo_emit_reloc(brw->batch.bo,
 227                               brw->wm.base.state_offset +
 228                               offsetof(struct brw_wm_unit_state, thread2),
 229                               brw->wm.base.scratch_bo,
 230                               wm->thread2.per_thread_scratch_space,
 231                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 232    }
 233
 234    /* Emit sampler state relocation */
 235    if (brw->wm.base.sampler_count != 0) {
 236       drm_intel_bo_emit_reloc(brw->batch.bo,
 237                               brw->wm.base.state_offset +
 238                               offsetof(struct brw_wm_unit_state, wm4),
 239                               brw->batch.bo, (brw->wm.base.sampler_offset |
 240                                               wm->wm4.stats_enable |
 241                                               (wm->wm4.sampler_count << 2)),
 242                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 243    }
 244
 245    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 246
 247    /* _NEW_POLGYON */
 248    if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
 249       BEGIN_BATCH(2);
 250       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 251       OUT_BATCH_F(ctx->Polygon.OffsetClamp);
 252       ADVANCE_BATCH();
 253
 254       brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
 255    }
 256 }
 257
 258 const struct brw_tracked_state brw_wm_unit = {
 259    .dirty = {
 260       .mesa = _NEW_BUFFERS |
 261               _NEW_COLOR |
 262               _NEW_LINE |
 263               _NEW_POLYGON |
 264               _NEW_POLYGONSTIPPLE,
 265       .brw = BRW_NEW_BATCH |
 266              BRW_NEW_BLORP |
 267              BRW_NEW_CURBE_OFFSETS |
 268              BRW_NEW_FRAGMENT_PROGRAM |
 269              BRW_NEW_FS_PROG_DATA |
 270              BRW_NEW_PROGRAM_CACHE |
 271              BRW_NEW_SAMPLER_STATE_TABLE |
 272              BRW_NEW_STATS_WM,
 273    },
 274    .emit = brw_upload_wm_unit,
 275 };