src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "bufmgr.h"
  38
  39 /***********************************************************************
  40  * WM unit - fragment programs and rasterization
  41  */
  42
  43 static void invalidate_scratch_cb( struct intel_context *intel,
  44                                    void *unused )
  45 {
  46    /* nothing */
  47 }
  48
  49
  50 static void upload_wm_unit(struct brw_context *brw )
  51 {
  52    struct intel_context *intel = &brw->intel;
  53    struct brw_wm_unit_state wm;
  54    GLuint max_threads;
  55
  56    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
  57       max_threads = 0;
  58    else
  59       max_threads = 31;
  60
  61
  62    memset(&wm, 0, sizeof(wm));
  63
  64    /* CACHE_NEW_WM_PROG */
  65    wm.thread0.grf_reg_count = ((brw->wm.prog_data->total_grf-1) & ~15) / 16;
  66    wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6;
  67    wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  68    wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  69    wm.thread3.const_urb_entry_read_length = brw->wm.prog_data->curb_read_length;
  70
  71    wm.wm5.max_threads = max_threads;
  72
  73    if (brw->wm.prog_data->total_scratch) {
  74       GLuint per_thread = (brw->wm.prog_data->total_scratch + 1023) / 1024;
  75       GLuint total = per_thread * (max_threads + 1);
  76
  77       /* Scratch space -- just have to make sure there is sufficient
  78        * allocated for the active program and current number of threads.
  79        */
  80
  81       if (!brw->wm.scratch_buffer) {
  82          bmGenBuffers(intel, "wm scratch", 1, &brw->wm.scratch_buffer);
  83          bmBufferSetInvalidateCB(intel,
  84                                  brw->wm.scratch_buffer,
  85                                  invalidate_scratch_cb,
  86                                  NULL,
  87                                  GL_FALSE);
  88       }
  89
  90       if (total > brw->wm.scratch_buffer_size) {
  91          brw->wm.scratch_buffer_size = total;
  92          bmBufferData(intel,
  93                       brw->wm.scratch_buffer,
  94                       brw->wm.scratch_buffer_size,
  95                       NULL,
  96                       0);
  97       }
  98
  99       assert(per_thread <= 12 * 1024);
 100       wm.thread2.per_thread_scratch_space = (per_thread / 1024) - 1;
 101       wm.thread2.scratch_space_base_pointer =
 102          bmBufferOffset(intel, brw->wm.scratch_buffer) >> 10;
 103    }
 104
 105    /* CACHE_NEW_SURFACE */
 106    wm.thread1.binding_table_entry_count = brw->wm.nr_surfaces;
 107
 108    /* BRW_NEW_CURBE_OFFSETS */
 109    wm.thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 110
 111    wm.thread3.urb_entry_read_offset = 0;
 112    wm.thread1.depth_coef_urb_read_offset = 1;
 113    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 114
 115    /* CACHE_NEW_SAMPLER */
 116    wm.wm4.sampler_count = brw->wm.sampler_count;
 117    wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
 118
 119    /* BRW_NEW_FRAGMENT_PROGRAM */
 120    {
 121       struct gl_fragment_program *fp = brw->fragment_program;
 122
 123       if (fp->Base.InputsRead & (1<<FRAG_ATTRIB_WPOS))
 124          wm.wm5.program_uses_depth = 1; /* as far as we can tell */
 125
 126       if (fp->Base.OutputsWritten & (1<<FRAG_RESULT_DEPR))
 127          wm.wm5.program_computes_depth = 1;
 128
 129       /* _NEW_COLOR */
 130       if (fp->UsesKill ||
 131           brw->attribs.Color->AlphaEnabled)
 132          wm.wm5.program_uses_killpixel = 1;
 133    }
 134
 135    wm.wm5.enable_16_pix = 1;
 136    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 137    wm.wm5.legacy_line_rast = 0;
 138    wm.wm5.legacy_global_depth_bias = 0;
 139    wm.wm5.early_depth_test = 1;         /* never need to disable */
 140    wm.wm5.line_aa_region_width = 0;
 141    wm.wm5.line_endcap_aa_region_width = 1;
 142
 143    /* _NEW_POLYGONSTIPPLE */
 144    if (brw->attribs.Polygon->StippleFlag)
 145       wm.wm5.polygon_stipple = 1;
 146
 147    /* _NEW_POLYGON */
 148    if (brw->attribs.Polygon->OffsetFill) {
 149       wm.wm5.depth_offset = 1;
 150       /* Something wierd going on with legacy_global_depth_bias,
 151        * offset_constant, scaling and MRD.  This value passes glean
 152        * but gives some odd results elsewere (eg. the
 153        * quad-offset-units test).
 154        */
 155       wm.global_depth_offset_constant = brw->attribs.Polygon->OffsetUnits * 2;
 156
 157       /* This is the only value that passes glean:
 158        */
 159       wm.global_depth_offset_scale = brw->attribs.Polygon->OffsetFactor;
 160    }
 161
 162    /* _NEW_LINE */
 163    if (brw->attribs.Line->StippleFlag) {
 164       wm.wm5.line_stipple = 1;
 165    }
 166
 167    if (INTEL_DEBUG & DEBUG_STATS)
 168       wm.wm4.stats_enable = 1;
 169
 170    brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
 171 }
 172
 173 const struct brw_tracked_state brw_wm_unit = {
 174    .dirty = {
 175       .mesa = (_NEW_POLYGON |
 176                _NEW_POLYGONSTIPPLE |
 177                _NEW_LINE |
 178                _NEW_COLOR),
 179
 180       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 181               BRW_NEW_CURBE_OFFSETS |
 182               BRW_NEW_FENCE),
 183
 184       .cache = (CACHE_NEW_SURFACE |
 185                 CACHE_NEW_WM_PROG |
 186                 CACHE_NEW_SAMPLER)
 187    },
 188    .update = upload_wm_unit
 189 };
 190