src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_fbo.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 bool
  45 brw_color_buffer_write_enabled(struct brw_context *brw)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    const struct gl_fragment_program *fp = brw->fragment_program;
  49    int i;
  50
  51    /* _NEW_BUFFERS */
  52    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  53       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  54
  55       /* _NEW_COLOR */
  56       if (rb &&
  57           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  58            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  59           (ctx->Color.ColorMask[i][0] ||
  60            ctx->Color.ColorMask[i][1] ||
  61            ctx->Color.ColorMask[i][2] ||
  62            ctx->Color.ColorMask[i][3])) {
  63          return true;
  64       }
  65    }
  66
  67    return false;
  68 }
  69
  70 /**
  71  * Setup wm hardware state.  See page 225 of Volume 2
  72  */
  73 static void
  74 brw_upload_wm_unit(struct brw_context *brw)
  75 {
  76    struct gl_context *ctx = &brw->ctx;
  77    const struct gl_fragment_program *fp = brw->fragment_program;
  78    struct brw_wm_unit_state *wm;
  79
  80    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  81                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  82    memset(wm, 0, sizeof(*wm));
  83
  84    if (brw->wm.prog_data->prog_offset_16) {
  85       /* These two fields should be the same pre-gen6, which is why we
  86        * only have one hardware field to program for both dispatch
  87        * widths.
  88        */
  89       assert(brw->wm.prog_data->first_curbe_grf ==
  90              brw->wm.prog_data->first_curbe_grf_16);
  91    }
  92
  93    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
  94    wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks;
  95    wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16;
  96
  97    wm->thread0.kernel_start_pointer =
  98       brw_program_reloc(brw,
  99                         brw->wm.base.state_offset +
 100                         offsetof(struct brw_wm_unit_state, thread0),
 101                         brw->wm.base.prog_offset +
 102                         (wm->thread0.grf_reg_count << 1)) >> 6;
 103
 104    wm->wm9.kernel_start_pointer_2 =
 105       brw_program_reloc(brw,
 106                         brw->wm.base.state_offset +
 107                         offsetof(struct brw_wm_unit_state, wm9),
 108                         brw->wm.base.prog_offset +
 109                         brw->wm.prog_data->prog_offset_16 +
 110                         (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 111
 112    wm->thread1.depth_coef_urb_read_offset = 1;
 113    /* Use ALT floating point mode for ARB fragment programs, because they
 114     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 115     * rendering, CurrentFragmentProgram is used for this check to
 116     * differentiate between the GLSL and non-GLSL cases.
 117     */
 118    if (ctx->Shader.CurrentFragmentProgram == NULL)
 119       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 120    else
 121       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 122
 123    wm->thread1.binding_table_entry_count = 0;
 124
 125    if (brw->wm.prog_data->total_scratch != 0) {
 126       wm->thread2.scratch_space_base_pointer =
 127          brw->wm.base.scratch_bo->offset >> 10; /* reloc */
 128       wm->thread2.per_thread_scratch_space =
 129          ffs(brw->wm.prog_data->total_scratch) - 11;
 130    } else {
 131       wm->thread2.scratch_space_base_pointer = 0;
 132       wm->thread2.per_thread_scratch_space = 0;
 133    }
 134
 135    wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
 136    wm->thread3.urb_entry_read_length =
 137       brw->wm.prog_data->num_varying_inputs * 2;
 138    wm->thread3.urb_entry_read_offset = 0;
 139    wm->thread3.const_urb_entry_read_length =
 140       brw->wm.prog_data->curb_read_length;
 141    /* BRW_NEW_CURBE_OFFSETS */
 142    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 143
 144    if (brw->gen == 5)
 145       wm->wm4.sampler_count = 0; /* hardware requirement */
 146    else {
 147       /* CACHE_NEW_SAMPLER */
 148       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 149    }
 150
 151    if (brw->wm.base.sampler_count) {
 152       /* reloc */
 153       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset +
 154                                        brw->wm.base.sampler_offset) >> 5;
 155    } else {
 156       wm->wm4.sampler_state_pointer = 0;
 157    }
 158
 159    /* BRW_NEW_FRAGMENT_PROGRAM */
 160    wm->wm5.program_uses_depth = (fp->Base.InputsRead &
 161                                  (1 << VARYING_SLOT_POS)) != 0;
 162    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 163                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 164    /* _NEW_BUFFERS
 165     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 166     * Depth field.
 167     */
 168    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 169       wm->wm5.program_computes_depth = 0;
 170
 171    /* _NEW_COLOR */
 172    wm->wm5.program_uses_killpixel = fp->UsesKill || ctx->Color.AlphaEnabled;
 173
 174    wm->wm5.enable_8_pix = 1;
 175    if (brw->wm.prog_data->prog_offset_16)
 176       wm->wm5.enable_16_pix = 1;
 177
 178    wm->wm5.max_threads = brw->max_wm_threads - 1;
 179
 180    /* _NEW_BUFFERS | _NEW_COLOR */
 181    if (brw_color_buffer_write_enabled(brw) ||
 182        wm->wm5.program_uses_killpixel ||
 183        wm->wm5.program_computes_depth) {
 184       wm->wm5.thread_dispatch_enable = 1;
 185    }
 186
 187    wm->wm5.legacy_line_rast = 0;
 188    wm->wm5.legacy_global_depth_bias = 0;
 189    wm->wm5.early_depth_test = 1;                /* never need to disable */
 190    wm->wm5.line_aa_region_width = 0;
 191    wm->wm5.line_endcap_aa_region_width = 1;
 192
 193    /* _NEW_POLYGONSTIPPLE */
 194    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 195
 196    /* _NEW_POLYGON */
 197    if (ctx->Polygon.OffsetFill) {
 198       wm->wm5.depth_offset = 1;
 199       /* Something wierd going on with legacy_global_depth_bias,
 200        * offset_constant, scaling and MRD.  This value passes glean
 201        * but gives some odd results elsewere (eg. the
 202        * quad-offset-units test).
 203        */
 204       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 205
 206       /* This is the only value that passes glean:
 207        */
 208       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 209    }
 210
 211    /* _NEW_LINE */
 212    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 213
 214    /* BRW_NEW_STATS_WM */
 215    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 216       wm->wm4.stats_enable = 1;
 217
 218    /* Emit scratch space relocation */
 219    if (brw->wm.prog_data->total_scratch != 0) {
 220       drm_intel_bo_emit_reloc(brw->batch.bo,
 221                               brw->wm.base.state_offset +
 222                               offsetof(struct brw_wm_unit_state, thread2),
 223                               brw->wm.base.scratch_bo,
 224                               wm->thread2.per_thread_scratch_space,
 225                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 226    }
 227
 228    /* Emit sampler state relocation */
 229    if (brw->wm.base.sampler_count != 0) {
 230       drm_intel_bo_emit_reloc(brw->batch.bo,
 231                               brw->wm.base.state_offset +
 232                               offsetof(struct brw_wm_unit_state, wm4),
 233                               brw->batch.bo, (brw->wm.base.sampler_offset |
 234                                               wm->wm4.stats_enable |
 235                                               (wm->wm4.sampler_count << 2)),
 236                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 237    }
 238
 239    brw->state.dirty.cache |= CACHE_NEW_WM_UNIT;
 240 }
 241
 242 const struct brw_tracked_state brw_wm_unit = {
 243    .dirty = {
 244       .mesa = (_NEW_POLYGON |
 245                _NEW_POLYGONSTIPPLE |
 246                _NEW_LINE |
 247                _NEW_COLOR |
 248                _NEW_BUFFERS),
 249
 250       .brw = (BRW_NEW_BATCH |
 251               BRW_NEW_PROGRAM_CACHE |
 252               BRW_NEW_FRAGMENT_PROGRAM |
 253               BRW_NEW_CURBE_OFFSETS |
 254               BRW_NEW_STATS_WM),
 255
 256       .cache = (CACHE_NEW_WM_PROG |
 257                 CACHE_NEW_SAMPLER)
 258    },
 259    .emit = brw_upload_wm_unit,
 260 };
 261