2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
39 /***********************************************************************
40 * WM unit - fragment programs and rasterization
43 struct brw_wm_unit_key
{
44 unsigned int total_grf
, total_scratch
;
45 unsigned int urb_entry_read_length
;
46 unsigned int curb_entry_read_length
;
47 unsigned int dispatch_grf_start_reg
;
49 unsigned int curbe_offset
;
50 unsigned int urb_size
;
52 unsigned int nr_surfaces
, sampler_count
;
53 GLboolean uses_depth
, computes_depth
, uses_kill
, is_glsl
;
54 GLboolean polygon_stipple
, stats_wm
, line_stipple
, offset_enable
;
55 GLfloat offset_units
, offset_factor
;
59 wm_unit_populate_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
)
61 GLcontext
*ctx
= &brw
->intel
.ctx
;
62 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
63 const struct brw_fragment_program
*bfp
= (struct brw_fragment_program
*) fp
;
64 struct intel_context
*intel
= &brw
->intel
;
66 memset(key
, 0, sizeof(*key
));
68 /* CACHE_NEW_WM_PROG */
69 key
->total_grf
= brw
->wm
.prog_data
->total_grf
;
70 key
->urb_entry_read_length
= brw
->wm
.prog_data
->urb_read_length
;
71 key
->curb_entry_read_length
= brw
->wm
.prog_data
->curb_read_length
;
72 key
->dispatch_grf_start_reg
= brw
->wm
.prog_data
->first_curbe_grf
;
73 key
->total_scratch
= ALIGN(brw
->wm
.prog_data
->total_scratch
, 1024);
75 /* BRW_NEW_URB_FENCE */
76 key
->urb_size
= brw
->urb
.vsize
;
78 /* BRW_NEW_CURBE_OFFSETS */
79 key
->curbe_offset
= brw
->curbe
.wm_start
;
81 /* BRW_NEW_NR_SURFACEs */
82 key
->nr_surfaces
= brw
->wm
.nr_surfaces
;
84 /* CACHE_NEW_SAMPLER */
85 key
->sampler_count
= brw
->wm
.sampler_count
;
87 /* _NEW_POLYGONSTIPPLE */
88 key
->polygon_stipple
= ctx
->Polygon
.StippleFlag
;
90 /* BRW_NEW_FRAGMENT_PROGRAM */
91 key
->uses_depth
= (fp
->Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
)) != 0;
93 /* as far as we can tell */
95 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) != 0;
96 /* BRW_NEW_DEPTH_BUFFER
97 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
100 if (brw
->state
.depth_region
== NULL
)
101 key
->computes_depth
= 0;
104 key
->uses_kill
= fp
->UsesKill
|| ctx
->Color
.AlphaEnabled
;
105 key
->is_glsl
= bfp
->isGLSL
;
107 /* If using the fragment shader backend, the program is always
110 if (ctx
->Shader
.CurrentProgram
) {
113 for (i
= 0; i
< ctx
->Shader
.CurrentProgram
->_NumLinkedShaders
; i
++) {
114 struct brw_shader
*shader
=
115 (struct brw_shader
*)ctx
->Shader
.CurrentProgram
->_LinkedShaders
[i
];;
117 if (shader
->base
.Type
== GL_FRAGMENT_SHADER
&&
118 shader
->ir
!= NULL
) {
119 key
->is_glsl
= GL_TRUE
;
125 key
->stats_wm
= intel
->stats_wm
;
128 key
->line_stipple
= ctx
->Line
.StippleFlag
;
131 key
->offset_enable
= ctx
->Polygon
.OffsetFill
;
132 key
->offset_units
= ctx
->Polygon
.OffsetUnits
;
133 key
->offset_factor
= ctx
->Polygon
.OffsetFactor
;
137 * Setup wm hardware state. See page 225 of Volume 2
139 static drm_intel_bo
*
140 wm_unit_create_from_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
,
141 drm_intel_bo
**reloc_bufs
)
143 struct intel_context
*intel
= &brw
->intel
;
144 struct brw_wm_unit_state wm
;
147 memset(&wm
, 0, sizeof(wm
));
149 wm
.thread0
.grf_reg_count
= ALIGN(key
->total_grf
, 16) / 16 - 1;
150 wm
.thread0
.kernel_start_pointer
= brw
->wm
.prog_bo
->offset
>> 6; /* reloc */
151 wm
.thread1
.depth_coef_urb_read_offset
= 1;
152 wm
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
155 wm
.thread1
.binding_table_entry_count
= 0; /* hardware requirement */
157 wm
.thread1
.binding_table_entry_count
= key
->nr_surfaces
;
159 if (key
->total_scratch
!= 0) {
160 wm
.thread2
.scratch_space_base_pointer
=
161 brw
->wm
.scratch_bo
->offset
>> 10; /* reloc */
162 wm
.thread2
.per_thread_scratch_space
= key
->total_scratch
/ 1024 - 1;
164 wm
.thread2
.scratch_space_base_pointer
= 0;
165 wm
.thread2
.per_thread_scratch_space
= 0;
168 wm
.thread3
.dispatch_grf_start_reg
= key
->dispatch_grf_start_reg
;
169 wm
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
170 wm
.thread3
.urb_entry_read_offset
= 0;
171 wm
.thread3
.const_urb_entry_read_length
= key
->curb_entry_read_length
;
172 wm
.thread3
.const_urb_entry_read_offset
= key
->curbe_offset
* 2;
175 wm
.wm4
.sampler_count
= 0; /* hardware requirement */
177 wm
.wm4
.sampler_count
= (key
->sampler_count
+ 1) / 4;
179 if (brw
->wm
.sampler_bo
!= NULL
) {
181 wm
.wm4
.sampler_state_pointer
= brw
->wm
.sampler_bo
->offset
>> 5;
183 wm
.wm4
.sampler_state_pointer
= 0;
186 wm
.wm5
.program_uses_depth
= key
->uses_depth
;
187 wm
.wm5
.program_computes_depth
= key
->computes_depth
;
188 wm
.wm5
.program_uses_killpixel
= key
->uses_kill
;
191 wm
.wm5
.enable_8_pix
= 1;
193 wm
.wm5
.enable_16_pix
= 1;
195 wm
.wm5
.max_threads
= brw
->wm_max_threads
- 1;
196 wm
.wm5
.thread_dispatch_enable
= 1; /* AKA: color_write */
197 wm
.wm5
.legacy_line_rast
= 0;
198 wm
.wm5
.legacy_global_depth_bias
= 0;
199 wm
.wm5
.early_depth_test
= 1; /* never need to disable */
200 wm
.wm5
.line_aa_region_width
= 0;
201 wm
.wm5
.line_endcap_aa_region_width
= 1;
203 wm
.wm5
.polygon_stipple
= key
->polygon_stipple
;
205 if (key
->offset_enable
) {
206 wm
.wm5
.depth_offset
= 1;
207 /* Something wierd going on with legacy_global_depth_bias,
208 * offset_constant, scaling and MRD. This value passes glean
209 * but gives some odd results elsewere (eg. the
210 * quad-offset-units test).
212 wm
.global_depth_offset_constant
= key
->offset_units
* 2;
214 /* This is the only value that passes glean:
216 wm
.global_depth_offset_scale
= key
->offset_factor
;
219 wm
.wm5
.line_stipple
= key
->line_stipple
;
221 if (INTEL_DEBUG
& DEBUG_STATS
|| key
->stats_wm
)
222 wm
.wm4
.stats_enable
= 1;
224 bo
= brw_upload_cache(&brw
->cache
, BRW_WM_UNIT
,
229 /* Emit WM program relocation */
230 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, thread0
),
231 brw
->wm
.prog_bo
, wm
.thread0
.grf_reg_count
<< 1,
232 I915_GEM_DOMAIN_INSTRUCTION
, 0);
234 /* Emit scratch space relocation */
235 if (key
->total_scratch
!= 0) {
236 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, thread2
),
238 wm
.thread2
.per_thread_scratch_space
,
239 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
242 /* Emit sampler state relocation */
243 if (key
->sampler_count
!= 0) {
244 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, wm4
),
245 brw
->wm
.sampler_bo
, (wm
.wm4
.stats_enable
|
246 (wm
.wm4
.sampler_count
<< 2)),
247 I915_GEM_DOMAIN_INSTRUCTION
, 0);
254 static void upload_wm_unit( struct brw_context
*brw
)
256 struct intel_context
*intel
= &brw
->intel
;
257 struct brw_wm_unit_key key
;
258 drm_intel_bo
*reloc_bufs
[3];
259 wm_unit_populate_key(brw
, &key
);
261 /* Allocate the necessary scratch space if we haven't already. Don't
262 * bother reducing the allocation later, since we use scratch so
265 assert(key
.total_scratch
<= 12 * 1024);
266 if (key
.total_scratch
) {
267 GLuint total
= key
.total_scratch
* brw
->wm_max_threads
;
269 if (brw
->wm
.scratch_bo
&& total
> brw
->wm
.scratch_bo
->size
) {
270 drm_intel_bo_unreference(brw
->wm
.scratch_bo
);
271 brw
->wm
.scratch_bo
= NULL
;
273 if (brw
->wm
.scratch_bo
== NULL
) {
274 brw
->wm
.scratch_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
281 reloc_bufs
[0] = brw
->wm
.prog_bo
;
282 reloc_bufs
[1] = brw
->wm
.scratch_bo
;
283 reloc_bufs
[2] = brw
->wm
.sampler_bo
;
285 drm_intel_bo_unreference(brw
->wm
.state_bo
);
286 brw
->wm
.state_bo
= brw_search_cache(&brw
->cache
, BRW_WM_UNIT
,
290 if (brw
->wm
.state_bo
== NULL
) {
291 brw
->wm
.state_bo
= wm_unit_create_from_key(brw
, &key
, reloc_bufs
);
295 const struct brw_tracked_state brw_wm_unit
= {
297 .mesa
= (_NEW_POLYGON
|
298 _NEW_POLYGONSTIPPLE
|
303 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
304 BRW_NEW_CURBE_OFFSETS
|
305 BRW_NEW_DEPTH_BUFFER
|
306 BRW_NEW_NR_WM_SURFACES
),
308 .cache
= (CACHE_NEW_WM_PROG
|
311 .prepare
= upload_wm_unit
,