src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "dri_bufmgr.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 static void upload_wm_unit(struct brw_context *brw )
  45 {
  46    struct intel_context *intel = &brw->intel;
  47    struct brw_wm_unit_state wm;
  48    GLuint max_threads;
  49    GLuint per_thread;
  50    dri_bo *reloc_bufs[3];
  51
  52    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
  53       max_threads = 0;
  54    else
  55       max_threads = 31;
  56
  57
  58    memset(&wm, 0, sizeof(wm));
  59
  60    /* CACHE_NEW_WM_PROG */
  61    wm.thread0.grf_reg_count = ALIGN(brw->wm.prog_data->total_grf, 16) / 16 - 1;
  62    wm.thread0.kernel_start_pointer = brw->wm.prog_bo->offset >> 6; /* reloc */
  63    wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  64    wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  65    wm.thread3.const_urb_entry_read_length = brw->wm.prog_data->curb_read_length;
  66
  67    wm.wm5.max_threads = max_threads;
  68
  69    per_thread = ALIGN(brw->wm.prog_data->total_scratch, 1024);
  70    assert(per_thread <= 12 * 1024);
  71
  72    if (brw->wm.prog_data->total_scratch) {
  73       GLuint total = per_thread * (max_threads + 1);
  74
  75       /* Scratch space -- just have to make sure there is sufficient
  76        * allocated for the active program and current number of threads.
  77        */
  78       brw->wm.scratch_buffer_size = total;
  79       if (brw->wm.scratch_buffer &&
  80           brw->wm.scratch_buffer_size > brw->wm.scratch_buffer->size) {
  81          dri_bo_unreference(brw->wm.scratch_buffer);
  82          brw->wm.scratch_buffer = NULL;
  83       }
  84       if (!brw->wm.scratch_buffer) {
  85          brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr,
  86                                                "wm scratch",
  87                                                brw->wm.scratch_buffer_size,
  88                                                4096, DRM_BO_FLAG_MEM_TT);
  89       }
  90    }
  91
  92    /* CACHE_NEW_SURFACE */
  93    wm.thread1.binding_table_entry_count = brw->wm.nr_surfaces;
  94
  95    /* CACHE_NEW_WM_PROG */
  96    if (per_thread != 0) {
  97    /* reloc */
  98       wm.thread2.scratch_space_base_pointer =
  99          brw->wm.scratch_buffer->offset >> 10;
 100       wm.thread2.per_thread_scratch_space = per_thread / 1024 - 1;
 101    } else {
 102       wm.thread2.scratch_space_base_pointer = 0;
 103       wm.thread2.per_thread_scratch_space = 0;
 104    }
 105
 106    /* BRW_NEW_CURBE_OFFSETS */
 107    wm.thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 108
 109    wm.thread3.urb_entry_read_offset = 0;
 110    wm.thread1.depth_coef_urb_read_offset = 1;
 111    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 112
 113    /* CACHE_NEW_SAMPLER */
 114    wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
 115    if (brw->wm.sampler_bo != NULL) {
 116       /* reloc */
 117       wm.wm4.sampler_state_pointer = brw->wm.sampler_bo->offset >> 5;
 118    } else {
 119       wm.wm4.sampler_state_pointer = 0;
 120    }
 121
 122    /* BRW_NEW_FRAGMENT_PROGRAM */
 123    {
 124       const struct gl_fragment_program *fp = brw->fragment_program;
 125
 126       if (fp->Base.InputsRead & (1<<FRAG_ATTRIB_WPOS))
 127          wm.wm5.program_uses_depth = 1; /* as far as we can tell */
 128
 129       if (fp->Base.OutputsWritten & (1<<FRAG_RESULT_DEPR))
 130          wm.wm5.program_computes_depth = 1;
 131
 132       /* _NEW_COLOR */
 133       if (fp->UsesKill ||
 134           brw->attribs.Color->AlphaEnabled)
 135          wm.wm5.program_uses_killpixel = 1;
 136
 137       if (brw_wm_is_glsl(fp))
 138           wm.wm5.enable_8_pix = 1;
 139       else
 140           wm.wm5.enable_16_pix = 1;
 141    }
 142
 143    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 144    wm.wm5.legacy_line_rast = 0;
 145    wm.wm5.legacy_global_depth_bias = 0;
 146    wm.wm5.early_depth_test = 1;         /* never need to disable */
 147    wm.wm5.line_aa_region_width = 0;
 148    wm.wm5.line_endcap_aa_region_width = 1;
 149
 150    /* _NEW_POLYGONSTIPPLE */
 151    if (brw->attribs.Polygon->StippleFlag)
 152       wm.wm5.polygon_stipple = 1;
 153
 154    /* _NEW_POLYGON */
 155    if (brw->attribs.Polygon->OffsetFill) {
 156       wm.wm5.depth_offset = 1;
 157       /* Something wierd going on with legacy_global_depth_bias,
 158        * offset_constant, scaling and MRD.  This value passes glean
 159        * but gives some odd results elsewere (eg. the
 160        * quad-offset-units test).
 161        */
 162       wm.global_depth_offset_constant = brw->attribs.Polygon->OffsetUnits * 2;
 163
 164       /* This is the only value that passes glean:
 165        */
 166       wm.global_depth_offset_scale = brw->attribs.Polygon->OffsetFactor;
 167    }
 168
 169    /* _NEW_LINE */
 170    if (brw->attribs.Line->StippleFlag) {
 171       wm.wm5.line_stipple = 1;
 172    }
 173
 174    if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
 175       wm.wm4.stats_enable = 1;
 176
 177    reloc_bufs[0] = brw->wm.prog_bo;
 178    reloc_bufs[1] = brw->wm.scratch_buffer;
 179    reloc_bufs[2] = brw->wm.sampler_bo;
 180
 181    brw->wm.thread0_delta = wm.thread0.grf_reg_count << 1;
 182    brw->wm.thread2_delta = wm.thread2.per_thread_scratch_space;
 183    brw->wm.wm4_delta = wm.wm4.stats_enable | (wm.wm4.sampler_count << 2);
 184
 185    dri_bo_unreference(brw->wm.state_bo);
 186    brw->wm.state_bo = brw_cache_data( &brw->cache, BRW_WM_UNIT, &wm,
 187                                       reloc_bufs, 3 );
 188 }
 189
 190 static void emit_reloc_wm_unit(struct brw_context *brw)
 191 {
 192    /* Emit WM program relocation */
 193    dri_emit_reloc(brw->wm.state_bo,
 194                   DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 195                   brw->wm.thread0_delta,
 196                   offsetof(struct brw_wm_unit_state, thread0),
 197                   brw->wm.prog_bo);
 198
 199    /* Emit scratch space relocation */
 200    if (brw->wm.scratch_buffer != NULL) {
 201       dri_emit_reloc(brw->wm.state_bo,
 202                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
 203                      brw->wm.thread2_delta,
 204                      offsetof(struct brw_wm_unit_state, thread2),
 205                      brw->wm.scratch_buffer);
 206    }
 207
 208    /* Emit sampler state relocation */
 209    if (brw->wm.sampler_bo != NULL) {
 210       dri_emit_reloc(brw->wm.state_bo,
 211                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 212                      brw->wm.wm4_delta,
 213                      offsetof(struct brw_wm_unit_state, wm4),
 214                      brw->wm.sampler_bo);
 215    }
 216 }
 217
 218 const struct brw_tracked_state brw_wm_unit = {
 219    .dirty = {
 220       .mesa = (_NEW_POLYGON |
 221                _NEW_POLYGONSTIPPLE |
 222                _NEW_LINE |
 223                _NEW_COLOR),
 224
 225       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 226               BRW_NEW_CURBE_OFFSETS |
 227               BRW_NEW_LOCK),
 228
 229       .cache = (CACHE_NEW_SURFACE |
 230                 CACHE_NEW_WM_PROG |
 231                 CACHE_NEW_SAMPLER)
 232    },
 233    .update = upload_wm_unit,
 234    .emit_reloc = emit_reloc_wm_unit,
 235 };
 236