src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "brw_wm.h"
  38
  39 /***********************************************************************
  40  * WM unit - fragment programs and rasterization
  41  */
  42
  43 struct brw_wm_unit_key {
  44    unsigned int total_grf, total_scratch;
  45    unsigned int urb_entry_read_length;
  46    unsigned int curb_entry_read_length;
  47    unsigned int dispatch_grf_start_reg;
  48
  49    unsigned int curbe_offset;
  50
  51    unsigned int nr_surfaces, sampler_count;
  52    GLboolean uses_depth, computes_depth, uses_kill, is_glsl;
  53    GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
  54    GLboolean color_write_enable;
  55    GLfloat offset_units, offset_factor;
  56 };
  57
  58 bool
  59 brw_color_buffer_write_enabled(struct brw_context *brw)
  60 {
  61    struct gl_context *ctx = &brw->intel.ctx;
  62    const struct gl_fragment_program *fp = brw->fragment_program;
  63    int i;
  64
  65    /* _NEW_BUFFERS */
  66    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  67       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  68
  69       /* _NEW_COLOR */
  70       if (rb &&
  71           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  72            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  73           (ctx->Color.ColorMask[i][0] ||
  74            ctx->Color.ColorMask[i][1] ||
  75            ctx->Color.ColorMask[i][2] ||
  76            ctx->Color.ColorMask[i][3])) {
  77          return true;
  78       }
  79    }
  80
  81    return false;
  82 }
  83
  84 static void
  85 wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
  86 {
  87    struct gl_context *ctx = &brw->intel.ctx;
  88    const struct gl_fragment_program *fp = brw->fragment_program;
  89    struct intel_context *intel = &brw->intel;
  90
  91    memset(key, 0, sizeof(*key));
  92
  93    /* CACHE_NEW_WM_PROG */
  94    key->total_grf = brw->wm.prog_data->total_grf;
  95    key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  96    key->curb_entry_read_length = brw->wm.prog_data->curb_read_length;
  97    key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  98    key->total_scratch = brw->wm.prog_data->total_scratch;
  99
 100    /* BRW_NEW_CURBE_OFFSETS */
 101    key->curbe_offset = brw->curbe.wm_start;
 102
 103    /* BRW_NEW_NR_SURFACEs */
 104    key->nr_surfaces = brw->wm.nr_surfaces;
 105
 106    /* CACHE_NEW_SAMPLER */
 107    key->sampler_count = brw->wm.sampler_count;
 108
 109    /* _NEW_POLYGONSTIPPLE */
 110    key->polygon_stipple = ctx->Polygon.StippleFlag;
 111
 112    /* BRW_NEW_FRAGMENT_PROGRAM */
 113    key->uses_depth = (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 114
 115    /* as far as we can tell */
 116    key->computes_depth =
 117       (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 118    /* BRW_NEW_DEPTH_BUFFER
 119     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 120     * Depth field.
 121     */
 122    if (brw->state.depth_region == NULL)
 123       key->computes_depth = 0;
 124
 125    /* _NEW_BUFFERS | _NEW_COLOR */
 126    key->color_write_enable = brw_color_buffer_write_enabled(brw);
 127
 128    /* _NEW_COLOR */
 129    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
 130
 131    /* If using the fragment shader backend, the program is always
 132     * 8-wide.
 133     */
 134    if (ctx->Shader.CurrentFragmentProgram) {
 135       struct brw_shader *shader = (struct brw_shader *)
 136          ctx->Shader.CurrentFragmentProgram->_LinkedShaders[MESA_SHADER_FRAGMENT];
 137
 138       if (shader != NULL && shader->ir != NULL) {
 139          key->is_glsl = GL_TRUE;
 140       }
 141    }
 142
 143    /* _NEW_DEPTH */
 144    key->stats_wm = intel->stats_wm;
 145
 146    /* _NEW_LINE */
 147    key->line_stipple = ctx->Line.StippleFlag;
 148
 149    /* _NEW_POLYGON */
 150    key->offset_enable = ctx->Polygon.OffsetFill;
 151    key->offset_units = ctx->Polygon.OffsetUnits;
 152    key->offset_factor = ctx->Polygon.OffsetFactor;
 153 }
 154
 155 /**
 156  * Setup wm hardware state.  See page 225 of Volume 2
 157  */
 158 static drm_intel_bo *
 159 wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
 160                         drm_intel_bo **reloc_bufs)
 161 {
 162    struct intel_context *intel = &brw->intel;
 163    struct brw_wm_unit_state wm;
 164    drm_intel_bo *bo;
 165
 166    memset(&wm, 0, sizeof(wm));
 167
 168    wm.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
 169    wm.thread0.kernel_start_pointer = brw->wm.prog_bo->offset >> 6; /* reloc */
 170    wm.thread1.depth_coef_urb_read_offset = 1;
 171    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 172
 173    if (intel->gen == 5)
 174       wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
 175    else
 176       wm.thread1.binding_table_entry_count = key->nr_surfaces;
 177
 178    if (key->total_scratch != 0) {
 179       wm.thread2.scratch_space_base_pointer =
 180          brw->wm.scratch_bo->offset >> 10; /* reloc */
 181       wm.thread2.per_thread_scratch_space = ffs(key->total_scratch) - 11;
 182    } else {
 183       wm.thread2.scratch_space_base_pointer = 0;
 184       wm.thread2.per_thread_scratch_space = 0;
 185    }
 186
 187    wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg;
 188    wm.thread3.urb_entry_read_length = key->urb_entry_read_length;
 189    wm.thread3.urb_entry_read_offset = 0;
 190    wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
 191    wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 192
 193    if (intel->gen == 5)
 194       wm.wm4.sampler_count = 0; /* hardware requirement */
 195    else
 196       wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
 197
 198    if (brw->wm.sampler_bo != NULL) {
 199       /* reloc */
 200       wm.wm4.sampler_state_pointer = brw->wm.sampler_bo->offset >> 5;
 201    } else {
 202       wm.wm4.sampler_state_pointer = 0;
 203    }
 204
 205    wm.wm5.program_uses_depth = key->uses_depth;
 206    wm.wm5.program_computes_depth = key->computes_depth;
 207    wm.wm5.program_uses_killpixel = key->uses_kill;
 208
 209    if (key->is_glsl)
 210       wm.wm5.enable_8_pix = 1;
 211    else
 212       wm.wm5.enable_16_pix = 1;
 213
 214    wm.wm5.max_threads = brw->wm_max_threads - 1;
 215
 216    if (key->color_write_enable ||
 217        key->uses_kill ||
 218        key->computes_depth) {
 219       wm.wm5.thread_dispatch_enable = 1;
 220    }
 221
 222    wm.wm5.legacy_line_rast = 0;
 223    wm.wm5.legacy_global_depth_bias = 0;
 224    wm.wm5.early_depth_test = 1;         /* never need to disable */
 225    wm.wm5.line_aa_region_width = 0;
 226    wm.wm5.line_endcap_aa_region_width = 1;
 227
 228    wm.wm5.polygon_stipple = key->polygon_stipple;
 229
 230    if (key->offset_enable) {
 231       wm.wm5.depth_offset = 1;
 232       /* Something wierd going on with legacy_global_depth_bias,
 233        * offset_constant, scaling and MRD.  This value passes glean
 234        * but gives some odd results elsewere (eg. the
 235        * quad-offset-units test).
 236        */
 237       wm.global_depth_offset_constant = key->offset_units * 2;
 238
 239       /* This is the only value that passes glean:
 240        */
 241       wm.global_depth_offset_scale = key->offset_factor;
 242    }
 243
 244    wm.wm5.line_stipple = key->line_stipple;
 245
 246    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || key->stats_wm)
 247       wm.wm4.stats_enable = 1;
 248
 249    bo = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
 250                          key, sizeof(*key),
 251                          reloc_bufs, 3,
 252                          &wm, sizeof(wm));
 253
 254    /* Emit WM program relocation */
 255    drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, thread0),
 256                            brw->wm.prog_bo, wm.thread0.grf_reg_count << 1,
 257                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 258
 259    /* Emit scratch space relocation */
 260    if (key->total_scratch != 0) {
 261       drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, thread2),
 262                               brw->wm.scratch_bo,
 263                               wm.thread2.per_thread_scratch_space,
 264                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 265    }
 266
 267    /* Emit sampler state relocation */
 268    if (key->sampler_count != 0) {
 269       drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, wm4),
 270                               brw->wm.sampler_bo, (wm.wm4.stats_enable |
 271                                                    (wm.wm4.sampler_count << 2)),
 272                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 273    }
 274
 275    return bo;
 276 }
 277
 278
 279 static void upload_wm_unit( struct brw_context *brw )
 280 {
 281    struct brw_wm_unit_key key;
 282    drm_intel_bo *reloc_bufs[3];
 283    wm_unit_populate_key(brw, &key);
 284
 285    reloc_bufs[0] = brw->wm.prog_bo;
 286    reloc_bufs[1] = brw->wm.scratch_bo;
 287    reloc_bufs[2] = brw->wm.sampler_bo;
 288
 289    drm_intel_bo_unreference(brw->wm.state_bo);
 290    brw->wm.state_bo = brw_search_cache(&brw->cache, BRW_WM_UNIT,
 291                                        &key, sizeof(key),
 292                                        reloc_bufs, 3,
 293                                        NULL);
 294    if (brw->wm.state_bo == NULL) {
 295       brw->wm.state_bo = wm_unit_create_from_key(brw, &key, reloc_bufs);
 296    }
 297 }
 298
 299 const struct brw_tracked_state brw_wm_unit = {
 300    .dirty = {
 301       .mesa = (_NEW_POLYGON |
 302                _NEW_POLYGONSTIPPLE |
 303                _NEW_LINE |
 304                _NEW_COLOR |
 305                _NEW_DEPTH |
 306                _NEW_BUFFERS),
 307
 308       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 309               BRW_NEW_CURBE_OFFSETS |
 310               BRW_NEW_DEPTH_BUFFER |
 311               BRW_NEW_NR_WM_SURFACES),
 312
 313       .cache = (CACHE_NEW_WM_PROG |
 314                 CACHE_NEW_SAMPLER)
 315    },
 316    .prepare = upload_wm_unit,
 317 };
 318