src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_fbo.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 bool
  45 brw_color_buffer_write_enabled(struct brw_context *brw)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    /* BRW_NEW_FRAGMENT_PROGRAM */
  49    const struct gl_fragment_program *fp = brw->fragment_program;
  50    int i;
  51
  52    /* _NEW_BUFFERS */
  53    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  54       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  55
  56       /* _NEW_COLOR */
  57       if (rb &&
  58           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  59            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  60           (ctx->Color.ColorMask[i][0] ||
  61            ctx->Color.ColorMask[i][1] ||
  62            ctx->Color.ColorMask[i][2] ||
  63            ctx->Color.ColorMask[i][3])) {
  64          return true;
  65       }
  66    }
  67
  68    return false;
  69 }
  70
  71 /**
  72  * Setup wm hardware state.  See page 225 of Volume 2
  73  */
  74 static void
  75 brw_upload_wm_unit(struct brw_context *brw)
  76 {
  77    struct gl_context *ctx = &brw->ctx;
  78    /* BRW_NEW_FRAGMENT_PROGRAM */
  79    const struct gl_fragment_program *fp = brw->fragment_program;
  80    /* BRW_NEW_FS_PROG_DATA */
  81    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  82    struct brw_wm_unit_state *wm;
  83
  84    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  85                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  86    memset(wm, 0, sizeof(*wm));
  87
  88    if (prog_data->prog_offset_16) {
  89       /* These two fields should be the same pre-gen6, which is why we
  90        * only have one hardware field to program for both dispatch
  91        * widths.
  92        */
  93       assert(prog_data->base.dispatch_grf_start_reg ==
  94              prog_data->dispatch_grf_start_reg_16);
  95    }
  96
  97    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
  98    wm->thread0.grf_reg_count = prog_data->reg_blocks;
  99    wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16;
 100
 101    wm->thread0.kernel_start_pointer =
 102       brw_program_reloc(brw,
 103                         brw->wm.base.state_offset +
 104                         offsetof(struct brw_wm_unit_state, thread0),
 105                         brw->wm.base.prog_offset +
 106                         (wm->thread0.grf_reg_count << 1)) >> 6;
 107
 108    wm->wm9.kernel_start_pointer_2 =
 109       brw_program_reloc(brw,
 110                         brw->wm.base.state_offset +
 111                         offsetof(struct brw_wm_unit_state, wm9),
 112                         brw->wm.base.prog_offset +
 113                         prog_data->prog_offset_16 +
 114                         (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 115
 116    wm->thread1.depth_coef_urb_read_offset = 1;
 117    if (prog_data->base.use_alt_mode)
 118       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 119    else
 120       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 121
 122    wm->thread1.binding_table_entry_count =
 123       prog_data->base.binding_table.size_bytes / 4;
 124
 125    if (prog_data->base.total_scratch != 0) {
 126       wm->thread2.scratch_space_base_pointer =
 127          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 128       wm->thread2.per_thread_scratch_space =
 129          ffs(prog_data->base.total_scratch) - 11;
 130    } else {
 131       wm->thread2.scratch_space_base_pointer = 0;
 132       wm->thread2.per_thread_scratch_space = 0;
 133    }
 134
 135    wm->thread3.dispatch_grf_start_reg =
 136       prog_data->base.dispatch_grf_start_reg;
 137    wm->thread3.urb_entry_read_length =
 138       prog_data->num_varying_inputs * 2;
 139    wm->thread3.urb_entry_read_offset = 0;
 140    wm->thread3.const_urb_entry_read_length =
 141       prog_data->base.curb_read_length;
 142    /* BRW_NEW_CURBE_OFFSETS */
 143    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 144
 145    if (brw->gen == 5)
 146       wm->wm4.sampler_count = 0; /* hardware requirement */
 147    else {
 148       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 149    }
 150
 151    if (brw->wm.base.sampler_count) {
 152       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 153       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 154                                        brw->wm.base.sampler_offset) >> 5;
 155    } else {
 156       wm->wm4.sampler_state_pointer = 0;
 157    }
 158
 159    /* BRW_NEW_FRAGMENT_PROGRAM */
 160    wm->wm5.program_uses_depth = (fp->Base.InputsRead &
 161                                  (1 << VARYING_SLOT_POS)) != 0;
 162    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 163                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 164    /* _NEW_BUFFERS
 165     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 166     * Depth field.
 167     */
 168    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 169       wm->wm5.program_computes_depth = 0;
 170
 171    /* _NEW_COLOR */
 172    wm->wm5.program_uses_killpixel =
 173       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 174
 175    wm->wm5.enable_8_pix = 1;
 176    if (prog_data->prog_offset_16)
 177       wm->wm5.enable_16_pix = 1;
 178
 179    wm->wm5.max_threads = brw->max_wm_threads - 1;
 180
 181    /* _NEW_BUFFERS | _NEW_COLOR */
 182    if (brw_color_buffer_write_enabled(brw) ||
 183        wm->wm5.program_uses_killpixel ||
 184        wm->wm5.program_computes_depth) {
 185       wm->wm5.thread_dispatch_enable = 1;
 186    }
 187
 188    wm->wm5.legacy_line_rast = 0;
 189    wm->wm5.legacy_global_depth_bias = 0;
 190    wm->wm5.early_depth_test = 1;                /* never need to disable */
 191    wm->wm5.line_aa_region_width = 0;
 192    wm->wm5.line_endcap_aa_region_width = 1;
 193
 194    /* _NEW_POLYGONSTIPPLE */
 195    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 196
 197    /* _NEW_POLYGON */
 198    if (ctx->Polygon.OffsetFill) {
 199       wm->wm5.depth_offset = 1;
 200       /* Something wierd going on with legacy_global_depth_bias,
 201        * offset_constant, scaling and MRD.  This value passes glean
 202        * but gives some odd results elsewere (eg. the
 203        * quad-offset-units test).
 204        */
 205       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 206
 207       /* This is the only value that passes glean:
 208        */
 209       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 210    }
 211
 212    /* _NEW_LINE */
 213    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 214
 215    /* BRW_NEW_STATS_WM */
 216    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 217       wm->wm4.stats_enable = 1;
 218
 219    /* Emit scratch space relocation */
 220    if (prog_data->base.total_scratch != 0) {
 221       drm_intel_bo_emit_reloc(brw->batch.bo,
 222                               brw->wm.base.state_offset +
 223                               offsetof(struct brw_wm_unit_state, thread2),
 224                               brw->wm.base.scratch_bo,
 225                               wm->thread2.per_thread_scratch_space,
 226                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 227    }
 228
 229    /* Emit sampler state relocation */
 230    if (brw->wm.base.sampler_count != 0) {
 231       drm_intel_bo_emit_reloc(brw->batch.bo,
 232                               brw->wm.base.state_offset +
 233                               offsetof(struct brw_wm_unit_state, wm4),
 234                               brw->batch.bo, (brw->wm.base.sampler_offset |
 235                                               wm->wm4.stats_enable |
 236                                               (wm->wm4.sampler_count << 2)),
 237                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 238    }
 239
 240    brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
 241 }
 242
 243 const struct brw_tracked_state brw_wm_unit = {
 244    .dirty = {
 245       .mesa = _NEW_BUFFERS |
 246               _NEW_COLOR |
 247               _NEW_LINE |
 248               _NEW_POLYGON |
 249               _NEW_POLYGONSTIPPLE,
 250       .brw = BRW_NEW_BATCH |
 251              BRW_NEW_CURBE_OFFSETS |
 252              BRW_NEW_FRAGMENT_PROGRAM |
 253              BRW_NEW_FS_PROG_DATA |
 254              BRW_NEW_PROGRAM_CACHE |
 255              BRW_NEW_SAMPLER_STATE_TABLE |
 256              BRW_NEW_STATS_WM,
 257    },
 258    .emit = brw_upload_wm_unit,
 259 };
 260