src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "dri_bufmgr.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 static void upload_wm_unit(struct brw_context *brw )
  45 {
  46    struct intel_context *intel = &brw->intel;
  47    struct brw_wm_unit_state wm;
  48    GLuint max_threads;
  49    GLuint per_thread;
  50
  51    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
  52       max_threads = 0;
  53    else
  54       max_threads = 31;
  55
  56
  57    memset(&wm, 0, sizeof(wm));
  58
  59    /* CACHE_NEW_WM_PROG */
  60    wm.thread0.grf_reg_count = ALIGN(brw->wm.prog_data->total_grf, 16) / 16 - 1;
  61    wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6;
  62    wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  63    wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  64    wm.thread3.const_urb_entry_read_length = brw->wm.prog_data->curb_read_length;
  65
  66    wm.wm5.max_threads = max_threads;
  67
  68    per_thread = ALIGN(brw->wm.prog_data->total_scratch, 1024);
  69    assert(per_thread <= 12 * 1024);
  70
  71    if (brw->wm.prog_data->total_scratch) {
  72       GLuint total = per_thread * (max_threads + 1);
  73
  74       /* Scratch space -- just have to make sure there is sufficient
  75        * allocated for the active program and current number of threads.
  76        */
  77       brw->wm.scratch_buffer_size = total;
  78       if (brw->wm.scratch_buffer &&
  79           brw->wm.scratch_buffer_size > brw->wm.scratch_buffer->size) {
  80          dri_bo_unreference(brw->wm.scratch_buffer);
  81          brw->wm.scratch_buffer = NULL;
  82       }
  83       if (!brw->wm.scratch_buffer) {
  84          brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr,
  85                                                "wm scratch",
  86                                                brw->wm.scratch_buffer_size,
  87                                                4096, DRM_BO_FLAG_MEM_TT);
  88       }
  89    }
  90    /* XXX: Scratch buffers are not implemented correectly.
  91     *
  92     * The scratch offset to be programmed into wm is relative to the general
  93     * state base address.  However, using dri_bo_alloc/dri_bo_emit_reloc (or
  94     * the previous bmGenBuffers scheme), we get an offset relative to the
  95     * start of framebuffer.  Even before then, it was broken in other ways,
  96     * so just fail for now if we hit that path.
  97     */
  98    assert(brw->wm.prog_data->total_scratch == 0);
  99
 100    /* CACHE_NEW_SURFACE */
 101    wm.thread1.binding_table_entry_count = brw->wm.nr_surfaces;
 102
 103    /* BRW_NEW_CURBE_OFFSETS */
 104    wm.thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 105
 106    wm.thread3.urb_entry_read_offset = 0;
 107    wm.thread1.depth_coef_urb_read_offset = 1;
 108    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 109
 110    /* CACHE_NEW_SAMPLER */
 111    wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
 112    wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
 113
 114    /* BRW_NEW_FRAGMENT_PROGRAM */
 115    {
 116       const struct gl_fragment_program *fp = brw->fragment_program;
 117
 118       if (fp->Base.InputsRead & (1<<FRAG_ATTRIB_WPOS))
 119          wm.wm5.program_uses_depth = 1; /* as far as we can tell */
 120
 121       if (fp->Base.OutputsWritten & (1<<FRAG_RESULT_DEPR))
 122          wm.wm5.program_computes_depth = 1;
 123
 124       /* _NEW_COLOR */
 125       if (fp->UsesKill ||
 126           brw->attribs.Color->AlphaEnabled)
 127          wm.wm5.program_uses_killpixel = 1;
 128
 129       if (brw_wm_is_glsl(fp))
 130           wm.wm5.enable_8_pix = 1;
 131       else
 132           wm.wm5.enable_16_pix = 1;
 133    }
 134
 135    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 136    wm.wm5.legacy_line_rast = 0;
 137    wm.wm5.legacy_global_depth_bias = 0;
 138    wm.wm5.early_depth_test = 1;         /* never need to disable */
 139    wm.wm5.line_aa_region_width = 0;
 140    wm.wm5.line_endcap_aa_region_width = 1;
 141
 142    /* _NEW_POLYGONSTIPPLE */
 143    if (brw->attribs.Polygon->StippleFlag)
 144       wm.wm5.polygon_stipple = 1;
 145
 146    /* _NEW_POLYGON */
 147    if (brw->attribs.Polygon->OffsetFill) {
 148       wm.wm5.depth_offset = 1;
 149       /* Something wierd going on with legacy_global_depth_bias,
 150        * offset_constant, scaling and MRD.  This value passes glean
 151        * but gives some odd results elsewere (eg. the
 152        * quad-offset-units test).
 153        */
 154       wm.global_depth_offset_constant = brw->attribs.Polygon->OffsetUnits * 2;
 155
 156       /* This is the only value that passes glean:
 157        */
 158       wm.global_depth_offset_scale = brw->attribs.Polygon->OffsetFactor;
 159    }
 160
 161    /* _NEW_LINE */
 162    if (brw->attribs.Line->StippleFlag) {
 163       wm.wm5.line_stipple = 1;
 164    }
 165
 166    if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
 167       wm.wm4.stats_enable = 1;
 168
 169    brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
 170
 171    if (brw->wm.prog_data->total_scratch) {
 172       /*
 173       dri_emit_reloc(brw->cache[BRW_WM_UNIT].pool->buffer,
 174                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
 175                      (per_thread / 1024) - 1,
 176                      brw->wm.state_gs_offset +
 177                      ((char *)&wm.thread2 - (char *)&wm),
 178                      brw->wm.scratch_buffer);
 179       */
 180    } else {
 181       wm.thread2.scratch_space_base_pointer = 0;
 182    }
 183 }
 184
 185 const struct brw_tracked_state brw_wm_unit = {
 186    .dirty = {
 187       .mesa = (_NEW_POLYGON |
 188                _NEW_POLYGONSTIPPLE |
 189                _NEW_LINE |
 190                _NEW_COLOR),
 191
 192       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 193               BRW_NEW_CURBE_OFFSETS |
 194               BRW_NEW_LOCK),
 195
 196       .cache = (CACHE_NEW_SURFACE |
 197                 CACHE_NEW_WM_PROG |
 198                 CACHE_NEW_SAMPLER)
 199    },
 200    .update = upload_wm_unit
 201 };
 202