2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
39 /***********************************************************************
40 * WM unit - fragment programs and rasterization
43 struct brw_wm_unit_key
{
44 unsigned int total_grf
, total_scratch
;
45 unsigned int urb_entry_read_length
;
46 unsigned int curb_entry_read_length
;
47 unsigned int dispatch_grf_start_reg
;
49 unsigned int curbe_offset
;
51 unsigned int nr_surfaces
, sampler_count
;
52 GLboolean uses_depth
, computes_depth
, uses_kill
, is_glsl
;
53 GLboolean polygon_stipple
, stats_wm
, line_stipple
, offset_enable
;
54 GLboolean color_write_enable
;
55 GLfloat offset_units
, offset_factor
;
59 brw_color_buffer_write_enabled(struct brw_context
*brw
)
61 struct gl_context
*ctx
= &brw
->intel
.ctx
;
62 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
66 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
67 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
71 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
72 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
73 (ctx
->Color
.ColorMask
[i
][0] ||
74 ctx
->Color
.ColorMask
[i
][1] ||
75 ctx
->Color
.ColorMask
[i
][2] ||
76 ctx
->Color
.ColorMask
[i
][3])) {
85 wm_unit_populate_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
)
87 struct gl_context
*ctx
= &brw
->intel
.ctx
;
88 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
89 struct intel_context
*intel
= &brw
->intel
;
91 memset(key
, 0, sizeof(*key
));
93 /* CACHE_NEW_WM_PROG */
94 key
->total_grf
= brw
->wm
.prog_data
->total_grf
;
95 key
->urb_entry_read_length
= brw
->wm
.prog_data
->urb_read_length
;
96 key
->curb_entry_read_length
= brw
->wm
.prog_data
->curb_read_length
;
97 key
->dispatch_grf_start_reg
= brw
->wm
.prog_data
->first_curbe_grf
;
98 key
->total_scratch
= brw
->wm
.prog_data
->total_scratch
;
100 /* BRW_NEW_CURBE_OFFSETS */
101 key
->curbe_offset
= brw
->curbe
.wm_start
;
103 /* BRW_NEW_NR_SURFACEs */
104 key
->nr_surfaces
= brw
->wm
.nr_surfaces
;
106 /* CACHE_NEW_SAMPLER */
107 key
->sampler_count
= brw
->wm
.sampler_count
;
109 /* _NEW_POLYGONSTIPPLE */
110 key
->polygon_stipple
= ctx
->Polygon
.StippleFlag
;
112 /* BRW_NEW_FRAGMENT_PROGRAM */
113 key
->uses_depth
= (fp
->Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
)) != 0;
115 /* as far as we can tell */
116 key
->computes_depth
=
117 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) != 0;
118 /* BRW_NEW_DEPTH_BUFFER
119 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
122 if (brw
->state
.depth_region
== NULL
)
123 key
->computes_depth
= 0;
125 /* _NEW_BUFFERS | _NEW_COLOR */
126 key
->color_write_enable
= brw_color_buffer_write_enabled(brw
);
129 key
->uses_kill
= fp
->UsesKill
|| ctx
->Color
.AlphaEnabled
;
131 /* If using the fragment shader backend, the program is always
134 if (ctx
->Shader
._CurrentFragmentProgram
) {
135 struct brw_shader
*shader
= (struct brw_shader
*)
136 ctx
->Shader
._CurrentFragmentProgram
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
138 if (shader
!= NULL
&& shader
->ir
!= NULL
) {
139 key
->is_glsl
= GL_TRUE
;
144 key
->stats_wm
= intel
->stats_wm
;
147 key
->line_stipple
= ctx
->Line
.StippleFlag
;
150 key
->offset_enable
= ctx
->Polygon
.OffsetFill
;
151 key
->offset_units
= ctx
->Polygon
.OffsetUnits
;
152 key
->offset_factor
= ctx
->Polygon
.OffsetFactor
;
156 * Setup wm hardware state. See page 225 of Volume 2
158 static drm_intel_bo
*
159 wm_unit_create_from_key(struct brw_context
*brw
, struct brw_wm_unit_key
*key
,
160 drm_intel_bo
**reloc_bufs
)
162 struct intel_context
*intel
= &brw
->intel
;
163 struct brw_wm_unit_state wm
;
166 memset(&wm
, 0, sizeof(wm
));
168 wm
.thread0
.grf_reg_count
= ALIGN(key
->total_grf
, 16) / 16 - 1;
169 wm
.thread0
.kernel_start_pointer
= brw
->wm
.prog_bo
->offset
>> 6; /* reloc */
170 wm
.thread1
.depth_coef_urb_read_offset
= 1;
171 wm
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
174 wm
.thread1
.binding_table_entry_count
= 0; /* hardware requirement */
176 wm
.thread1
.binding_table_entry_count
= key
->nr_surfaces
;
178 if (key
->total_scratch
!= 0) {
179 wm
.thread2
.scratch_space_base_pointer
=
180 brw
->wm
.scratch_bo
->offset
>> 10; /* reloc */
181 wm
.thread2
.per_thread_scratch_space
= ffs(key
->total_scratch
) - 11;
183 wm
.thread2
.scratch_space_base_pointer
= 0;
184 wm
.thread2
.per_thread_scratch_space
= 0;
187 wm
.thread3
.dispatch_grf_start_reg
= key
->dispatch_grf_start_reg
;
188 wm
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
189 wm
.thread3
.urb_entry_read_offset
= 0;
190 wm
.thread3
.const_urb_entry_read_length
= key
->curb_entry_read_length
;
191 wm
.thread3
.const_urb_entry_read_offset
= key
->curbe_offset
* 2;
194 wm
.wm4
.sampler_count
= 0; /* hardware requirement */
196 wm
.wm4
.sampler_count
= (key
->sampler_count
+ 1) / 4;
198 if (brw
->wm
.sampler_bo
!= NULL
) {
200 wm
.wm4
.sampler_state_pointer
= brw
->wm
.sampler_bo
->offset
>> 5;
202 wm
.wm4
.sampler_state_pointer
= 0;
205 wm
.wm5
.program_uses_depth
= key
->uses_depth
;
206 wm
.wm5
.program_computes_depth
= key
->computes_depth
;
207 wm
.wm5
.program_uses_killpixel
= key
->uses_kill
;
210 wm
.wm5
.enable_8_pix
= 1;
212 wm
.wm5
.enable_16_pix
= 1;
214 wm
.wm5
.max_threads
= brw
->wm_max_threads
- 1;
216 if (key
->color_write_enable
||
218 key
->computes_depth
) {
219 wm
.wm5
.thread_dispatch_enable
= 1;
222 wm
.wm5
.legacy_line_rast
= 0;
223 wm
.wm5
.legacy_global_depth_bias
= 0;
224 wm
.wm5
.early_depth_test
= 1; /* never need to disable */
225 wm
.wm5
.line_aa_region_width
= 0;
226 wm
.wm5
.line_endcap_aa_region_width
= 1;
228 wm
.wm5
.polygon_stipple
= key
->polygon_stipple
;
230 if (key
->offset_enable
) {
231 wm
.wm5
.depth_offset
= 1;
232 /* Something wierd going on with legacy_global_depth_bias,
233 * offset_constant, scaling and MRD. This value passes glean
234 * but gives some odd results elsewere (eg. the
235 * quad-offset-units test).
237 wm
.global_depth_offset_constant
= key
->offset_units
* 2;
239 /* This is the only value that passes glean:
241 wm
.global_depth_offset_scale
= key
->offset_factor
;
244 wm
.wm5
.line_stipple
= key
->line_stipple
;
246 if (unlikely(INTEL_DEBUG
& DEBUG_STATS
) || key
->stats_wm
)
247 wm
.wm4
.stats_enable
= 1;
249 bo
= brw_upload_cache(&brw
->cache
, BRW_WM_UNIT
,
254 /* Emit WM program relocation */
255 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, thread0
),
256 brw
->wm
.prog_bo
, wm
.thread0
.grf_reg_count
<< 1,
257 I915_GEM_DOMAIN_INSTRUCTION
, 0);
259 /* Emit scratch space relocation */
260 if (key
->total_scratch
!= 0) {
261 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, thread2
),
263 wm
.thread2
.per_thread_scratch_space
,
264 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
267 /* Emit sampler state relocation */
268 if (key
->sampler_count
!= 0) {
269 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_wm_unit_state
, wm4
),
270 brw
->wm
.sampler_bo
, (wm
.wm4
.stats_enable
|
271 (wm
.wm4
.sampler_count
<< 2)),
272 I915_GEM_DOMAIN_INSTRUCTION
, 0);
279 static void upload_wm_unit( struct brw_context
*brw
)
281 struct intel_context
*intel
= &brw
->intel
;
282 struct brw_wm_unit_key key
;
283 drm_intel_bo
*reloc_bufs
[3];
284 wm_unit_populate_key(brw
, &key
);
286 /* Allocate the necessary scratch space if we haven't already. Don't
287 * bother reducing the allocation later, since we use scratch so
290 if (key
.total_scratch
) {
291 GLuint total
= key
.total_scratch
* brw
->wm_max_threads
;
293 if (brw
->wm
.scratch_bo
&& total
> brw
->wm
.scratch_bo
->size
) {
294 drm_intel_bo_unreference(brw
->wm
.scratch_bo
);
295 brw
->wm
.scratch_bo
= NULL
;
297 if (brw
->wm
.scratch_bo
== NULL
) {
298 brw
->wm
.scratch_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
305 reloc_bufs
[0] = brw
->wm
.prog_bo
;
306 reloc_bufs
[1] = brw
->wm
.scratch_bo
;
307 reloc_bufs
[2] = brw
->wm
.sampler_bo
;
309 drm_intel_bo_unreference(brw
->wm
.state_bo
);
310 brw
->wm
.state_bo
= brw_search_cache(&brw
->cache
, BRW_WM_UNIT
,
314 if (brw
->wm
.state_bo
== NULL
) {
315 brw
->wm
.state_bo
= wm_unit_create_from_key(brw
, &key
, reloc_bufs
);
319 const struct brw_tracked_state brw_wm_unit
= {
321 .mesa
= (_NEW_POLYGON
|
322 _NEW_POLYGONSTIPPLE
|
328 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
329 BRW_NEW_CURBE_OFFSETS
|
330 BRW_NEW_DEPTH_BUFFER
|
331 BRW_NEW_NR_WM_SURFACES
),
333 .cache
= (CACHE_NEW_WM_PROG
|
336 .prepare
= upload_wm_unit
,