2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_defines.h"
41 /***********************************************************************
42 * WM unit - fragment programs and rasterization
46 brw_color_buffer_write_enabled(struct brw_context
*brw
)
48 struct gl_context
*ctx
= &brw
->ctx
;
49 /* BRW_NEW_FRAGMENT_PROGRAM */
50 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
54 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
55 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
59 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_COLOR
) ||
60 fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DATA0
+ i
)) &&
61 (ctx
->Color
.ColorMask
[i
][0] ||
62 ctx
->Color
.ColorMask
[i
][1] ||
63 ctx
->Color
.ColorMask
[i
][2] ||
64 ctx
->Color
.ColorMask
[i
][3])) {
73 * Setup wm hardware state. See page 225 of Volume 2
76 brw_upload_wm_unit(struct brw_context
*brw
)
78 struct gl_context
*ctx
= &brw
->ctx
;
79 /* BRW_NEW_FRAGMENT_PROGRAM */
80 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
81 /* BRW_NEW_FS_PROG_DATA */
82 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
83 struct brw_wm_unit_state
*wm
;
85 wm
= brw_state_batch(brw
, AUB_TRACE_WM_STATE
,
86 sizeof(*wm
), 32, &brw
->wm
.base
.state_offset
);
87 memset(wm
, 0, sizeof(*wm
));
89 if (prog_data
->dispatch_8
&& prog_data
->dispatch_16
) {
90 /* These two fields should be the same pre-gen6, which is why we
91 * only have one hardware field to program for both dispatch
94 assert(prog_data
->base
.dispatch_grf_start_reg
==
95 prog_data
->dispatch_grf_start_reg_2
);
98 /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
99 wm
->wm5
.enable_8_pix
= prog_data
->dispatch_8
;
100 wm
->wm5
.enable_16_pix
= prog_data
->dispatch_16
;
102 if (prog_data
->dispatch_8
|| prog_data
->dispatch_16
) {
103 wm
->thread0
.grf_reg_count
= prog_data
->reg_blocks_0
;
104 wm
->thread0
.kernel_start_pointer
=
105 brw_program_reloc(brw
,
106 brw
->wm
.base
.state_offset
+
107 offsetof(struct brw_wm_unit_state
, thread0
),
108 brw
->wm
.base
.prog_offset
+
109 (wm
->thread0
.grf_reg_count
<< 1)) >> 6;
112 if (prog_data
->prog_offset_2
) {
113 wm
->wm9
.grf_reg_count_2
= prog_data
->reg_blocks_2
;
114 wm
->wm9
.kernel_start_pointer_2
=
115 brw_program_reloc(brw
,
116 brw
->wm
.base
.state_offset
+
117 offsetof(struct brw_wm_unit_state
, wm9
),
118 brw
->wm
.base
.prog_offset
+
119 prog_data
->prog_offset_2
+
120 (wm
->wm9
.grf_reg_count_2
<< 1)) >> 6;
123 wm
->thread1
.depth_coef_urb_read_offset
= 1;
124 if (prog_data
->base
.use_alt_mode
)
125 wm
->thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
127 wm
->thread1
.floating_point_mode
= BRW_FLOATING_POINT_IEEE_754
;
129 wm
->thread1
.binding_table_entry_count
=
130 prog_data
->base
.binding_table
.size_bytes
/ 4;
132 if (prog_data
->base
.total_scratch
!= 0) {
133 wm
->thread2
.scratch_space_base_pointer
=
134 brw
->wm
.base
.scratch_bo
->offset64
>> 10; /* reloc */
135 wm
->thread2
.per_thread_scratch_space
=
136 ffs(brw
->wm
.base
.per_thread_scratch
) - 11;
138 wm
->thread2
.scratch_space_base_pointer
= 0;
139 wm
->thread2
.per_thread_scratch_space
= 0;
142 wm
->thread3
.dispatch_grf_start_reg
=
143 prog_data
->base
.dispatch_grf_start_reg
;
144 wm
->thread3
.urb_entry_read_length
=
145 prog_data
->num_varying_inputs
* 2;
146 wm
->thread3
.urb_entry_read_offset
= 0;
147 wm
->thread3
.const_urb_entry_read_length
=
148 prog_data
->base
.curb_read_length
;
149 /* BRW_NEW_CURBE_OFFSETS */
150 wm
->thread3
.const_urb_entry_read_offset
= brw
->curbe
.wm_start
* 2;
153 wm
->wm4
.sampler_count
= 0; /* hardware requirement */
155 wm
->wm4
.sampler_count
= (brw
->wm
.base
.sampler_count
+ 1) / 4;
158 if (brw
->wm
.base
.sampler_count
) {
159 /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
160 wm
->wm4
.sampler_state_pointer
= (brw
->batch
.bo
->offset64
+
161 brw
->wm
.base
.sampler_offset
) >> 5;
163 wm
->wm4
.sampler_state_pointer
= 0;
166 /* BRW_NEW_FRAGMENT_PROGRAM */
167 wm
->wm5
.program_uses_depth
= prog_data
->uses_src_depth
;
168 wm
->wm5
.program_computes_depth
= (fp
->Base
.OutputsWritten
&
169 BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) != 0;
171 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
174 if (!intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
))
175 wm
->wm5
.program_computes_depth
= 0;
178 wm
->wm5
.program_uses_killpixel
=
179 prog_data
->uses_kill
|| ctx
->Color
.AlphaEnabled
;
181 wm
->wm5
.max_threads
= brw
->max_wm_threads
- 1;
183 /* _NEW_BUFFERS | _NEW_COLOR */
184 if (brw_color_buffer_write_enabled(brw
) ||
185 wm
->wm5
.program_uses_killpixel
||
186 wm
->wm5
.program_computes_depth
) {
187 wm
->wm5
.thread_dispatch_enable
= 1;
190 wm
->wm5
.legacy_line_rast
= 0;
191 wm
->wm5
.legacy_global_depth_bias
= 0;
192 wm
->wm5
.early_depth_test
= 1; /* never need to disable */
193 wm
->wm5
.line_aa_region_width
= 0;
194 wm
->wm5
.line_endcap_aa_region_width
= 1;
196 /* _NEW_POLYGONSTIPPLE */
197 wm
->wm5
.polygon_stipple
= ctx
->Polygon
.StippleFlag
;
200 if (ctx
->Polygon
.OffsetFill
) {
201 wm
->wm5
.depth_offset
= 1;
202 /* Something weird going on with legacy_global_depth_bias,
203 * offset_constant, scaling and MRD. This value passes glean
204 * but gives some odd results elsewere (eg. the
205 * quad-offset-units test).
207 wm
->global_depth_offset_constant
= ctx
->Polygon
.OffsetUnits
* 2;
209 /* This is the only value that passes glean:
211 wm
->global_depth_offset_scale
= ctx
->Polygon
.OffsetFactor
;
215 wm
->wm5
.line_stipple
= ctx
->Line
.StippleFlag
;
217 /* BRW_NEW_STATS_WM */
218 if (unlikely(INTEL_DEBUG
& DEBUG_STATS
) || brw
->stats_wm
)
219 wm
->wm4
.stats_enable
= 1;
221 /* Emit scratch space relocation */
222 if (prog_data
->base
.total_scratch
!= 0) {
223 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
224 brw
->wm
.base
.state_offset
+
225 offsetof(struct brw_wm_unit_state
, thread2
),
226 brw
->wm
.base
.scratch_bo
,
227 wm
->thread2
.per_thread_scratch_space
,
228 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
231 /* Emit sampler state relocation */
232 if (brw
->wm
.base
.sampler_count
!= 0) {
233 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
234 brw
->wm
.base
.state_offset
+
235 offsetof(struct brw_wm_unit_state
, wm4
),
236 brw
->batch
.bo
, (brw
->wm
.base
.sampler_offset
|
237 wm
->wm4
.stats_enable
|
238 (wm
->wm4
.sampler_count
<< 2)),
239 I915_GEM_DOMAIN_INSTRUCTION
, 0);
242 brw
->ctx
.NewDriverState
|= BRW_NEW_GEN4_UNIT_STATE
;
245 if (brw
->wm
.offset_clamp
!= ctx
->Polygon
.OffsetClamp
) {
247 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
248 OUT_BATCH_F(ctx
->Polygon
.OffsetClamp
);
251 brw
->wm
.offset_clamp
= ctx
->Polygon
.OffsetClamp
;
255 const struct brw_tracked_state brw_wm_unit
= {
257 .mesa
= _NEW_BUFFERS
|
262 .brw
= BRW_NEW_BATCH
|
264 BRW_NEW_CURBE_OFFSETS
|
265 BRW_NEW_FRAGMENT_PROGRAM
|
266 BRW_NEW_FS_PROG_DATA
|
267 BRW_NEW_PROGRAM_CACHE
|
268 BRW_NEW_SAMPLER_STATE_TABLE
|
271 .emit
= brw_upload_wm_unit
,