2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "compiler/nir/nir.h"
34 #include "main/context.h"
35 #include "main/blend.h"
36 #include "main/mtypes.h"
37 #include "main/samplerobj.h"
38 #include "main/shaderimage.h"
39 #include "main/teximage.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_instruction.h"
42 #include "main/framebuffer.h"
43 #include "main/shaderapi.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_batchbuffer.h"
49 #include "intel_tex.h"
50 #include "intel_fbo.h"
51 #include "intel_buffer_objects.h"
53 #include "brw_context.h"
54 #include "brw_state.h"
55 #include "brw_defines.h"
59 INTEL_RENDERBUFFER_LAYERED
= 1 << 0,
60 INTEL_AUX_BUFFER_DISABLED
= 1 << 1,
63 uint32_t tex_mocs
[] = {
69 uint32_t rb_mocs
[] = {
76 brw_emit_surface_state(struct brw_context
*brw
,
77 struct intel_mipmap_tree
*mt
, uint32_t flags
,
78 GLenum target
, struct isl_view view
,
79 uint32_t mocs
, uint32_t *surf_offset
, int surf_index
,
80 unsigned read_domains
, unsigned write_domains
)
82 uint32_t tile_x
= mt
->level
[0].slice
[0].x_offset
;
83 uint32_t tile_y
= mt
->level
[0].slice
[0].y_offset
;
84 uint32_t offset
= mt
->offset
;
87 intel_miptree_get_isl_surf(brw
, mt
, &surf
);
89 surf
.dim
= get_isl_surf_dim(target
);
91 const enum isl_dim_layout dim_layout
=
92 get_isl_dim_layout(&brw
->screen
->devinfo
, mt
->tiling
, target
);
94 if (surf
.dim_layout
!= dim_layout
) {
95 /* The layout of the specified texture target is not compatible with the
96 * actual layout of the miptree structure in memory -- You're entering
97 * dangerous territory, this can only possibly work if you only intended
98 * to access a single level and slice of the texture, and the hardware
99 * supports the tile offset feature in order to allow non-tile-aligned
100 * base offsets, since we'll have to point the hardware to the first
101 * texel of the level instead of relying on the usual base level/layer
104 assert(brw
->has_surface_tile_offset
);
105 assert(view
.levels
== 1 && view
.array_len
== 1);
106 assert(tile_x
== 0 && tile_y
== 0);
108 offset
+= intel_miptree_get_tile_offsets(mt
, view
.base_level
,
109 view
.base_array_layer
,
112 /* Minify the logical dimensions of the texture. */
113 const unsigned l
= view
.base_level
- mt
->first_level
;
114 surf
.logical_level0_px
.width
= minify(surf
.logical_level0_px
.width
, l
);
115 surf
.logical_level0_px
.height
= surf
.dim
<= ISL_SURF_DIM_1D
? 1 :
116 minify(surf
.logical_level0_px
.height
, l
);
117 surf
.logical_level0_px
.depth
= surf
.dim
<= ISL_SURF_DIM_2D
? 1 :
118 minify(surf
.logical_level0_px
.depth
, l
);
120 /* Only the base level and layer can be addressed with the overridden
123 surf
.logical_level0_px
.array_len
= 1;
125 surf
.dim_layout
= dim_layout
;
127 /* The requested slice of the texture is now at the base level and
131 view
.base_array_layer
= 0;
134 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
136 drm_intel_bo
*aux_bo
;
137 struct isl_surf
*aux_surf
= NULL
, aux_surf_s
;
138 uint64_t aux_offset
= 0;
139 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
140 if ((mt
->mcs_buf
|| intel_miptree_sample_with_hiz(brw
, mt
)) &&
141 !(flags
& INTEL_AUX_BUFFER_DISABLED
)) {
142 intel_miptree_get_aux_isl_surf(brw
, mt
, &aux_surf_s
, &aux_usage
);
143 aux_surf
= &aux_surf_s
;
146 assert(mt
->mcs_buf
->offset
== 0);
147 aux_bo
= mt
->mcs_buf
->bo
;
148 aux_offset
= mt
->mcs_buf
->bo
->offset64
+ mt
->mcs_buf
->offset
;
150 aux_bo
= mt
->hiz_buf
->aux_base
.bo
;
151 aux_offset
= mt
->hiz_buf
->aux_base
.bo
->offset64
;
154 /* We only really need a clear color if we also have an auxiliary
155 * surface. Without one, it does nothing.
157 clear_color
= intel_miptree_get_isl_clear_color(brw
, mt
);
160 void *state
= __brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
161 brw
->isl_dev
.ss
.size
,
162 brw
->isl_dev
.ss
.align
,
163 surf_index
, surf_offset
);
165 isl_surf_fill_state(&brw
->isl_dev
, state
, .surf
= &surf
, .view
= &view
,
166 .address
= mt
->bo
->offset64
+ offset
,
167 .aux_surf
= aux_surf
, .aux_usage
= aux_usage
,
168 .aux_address
= aux_offset
,
169 .mocs
= mocs
, .clear_color
= clear_color
,
170 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
172 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
173 *surf_offset
+ brw
->isl_dev
.ss
.addr_offset
,
175 read_domains
, write_domains
);
178 /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
179 * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
180 * contain other control information. Since buffer addresses are always
181 * on 4k boundaries (and thus have their lower 12 bits zero), we can use
182 * an ordinary reloc to do the necessary address translation.
184 assert((aux_offset
& 0xfff) == 0);
185 uint32_t *aux_addr
= state
+ brw
->isl_dev
.ss
.aux_addr_offset
;
186 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
187 *surf_offset
+ brw
->isl_dev
.ss
.aux_addr_offset
,
188 aux_bo
, *aux_addr
& 0xfff,
189 read_domains
, write_domains
);
194 brw_update_renderbuffer_surface(struct brw_context
*brw
,
195 struct gl_renderbuffer
*rb
,
196 uint32_t flags
, unsigned unit
/* unused */,
199 struct gl_context
*ctx
= &brw
->ctx
;
200 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
201 struct intel_mipmap_tree
*mt
= irb
->mt
;
204 assert(!(flags
& INTEL_AUX_BUFFER_DISABLED
));
207 assert(brw_render_target_supported(brw
, rb
));
209 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
210 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
211 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
212 __func__
, _mesa_get_format_name(rb_format
));
215 const unsigned layer_multiplier
=
216 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
217 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
218 MAX2(irb
->mt
->num_samples
, 1) : 1;
220 struct isl_view view
= {
221 .format
= brw
->render_target_format
[rb_format
],
222 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
224 .base_array_layer
= irb
->mt_layer
/ layer_multiplier
,
225 .array_len
= MAX2(irb
->layer_count
, 1),
226 .swizzle
= ISL_SWIZZLE_IDENTITY
,
227 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
231 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
234 I915_GEM_DOMAIN_RENDER
,
235 I915_GEM_DOMAIN_RENDER
);
240 translate_tex_target(GLenum target
)
244 case GL_TEXTURE_1D_ARRAY_EXT
:
245 return BRW_SURFACE_1D
;
247 case GL_TEXTURE_RECTANGLE_NV
:
248 return BRW_SURFACE_2D
;
251 case GL_TEXTURE_2D_ARRAY_EXT
:
252 case GL_TEXTURE_EXTERNAL_OES
:
253 case GL_TEXTURE_2D_MULTISAMPLE
:
254 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
255 return BRW_SURFACE_2D
;
258 return BRW_SURFACE_3D
;
260 case GL_TEXTURE_CUBE_MAP
:
261 case GL_TEXTURE_CUBE_MAP_ARRAY
:
262 return BRW_SURFACE_CUBE
;
265 unreachable("not reached");
270 brw_get_surface_tiling_bits(uint32_t tiling
)
274 return BRW_SURFACE_TILED
;
276 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
284 brw_get_surface_num_multisamples(unsigned num_samples
)
287 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
289 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
293 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
297 brw_get_texture_swizzle(const struct gl_context
*ctx
,
298 const struct gl_texture_object
*t
)
300 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
302 int swizzles
[SWIZZLE_NIL
+ 1] = {
312 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
313 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
314 GLenum depth_mode
= t
->DepthMode
;
316 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
317 * with depth component data specified with a sized internal format.
318 * Otherwise, it's left at the old default, GL_LUMINANCE.
320 if (_mesa_is_gles3(ctx
) &&
321 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
322 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
326 switch (depth_mode
) {
328 swizzles
[0] = SWIZZLE_ZERO
;
329 swizzles
[1] = SWIZZLE_ZERO
;
330 swizzles
[2] = SWIZZLE_ZERO
;
331 swizzles
[3] = SWIZZLE_X
;
334 swizzles
[0] = SWIZZLE_X
;
335 swizzles
[1] = SWIZZLE_X
;
336 swizzles
[2] = SWIZZLE_X
;
337 swizzles
[3] = SWIZZLE_ONE
;
340 swizzles
[0] = SWIZZLE_X
;
341 swizzles
[1] = SWIZZLE_X
;
342 swizzles
[2] = SWIZZLE_X
;
343 swizzles
[3] = SWIZZLE_X
;
346 swizzles
[0] = SWIZZLE_X
;
347 swizzles
[1] = SWIZZLE_ZERO
;
348 swizzles
[2] = SWIZZLE_ZERO
;
349 swizzles
[3] = SWIZZLE_ONE
;
354 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
356 /* If the texture's format is alpha-only, force R, G, and B to
357 * 0.0. Similarly, if the texture's format has no alpha channel,
358 * force the alpha value read to 1.0. This allows for the
359 * implementation to use an RGBA texture for any of these formats
360 * without leaking any unexpected values.
362 switch (img
->_BaseFormat
) {
364 swizzles
[0] = SWIZZLE_ZERO
;
365 swizzles
[1] = SWIZZLE_ZERO
;
366 swizzles
[2] = SWIZZLE_ZERO
;
369 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
370 swizzles
[0] = SWIZZLE_X
;
371 swizzles
[1] = SWIZZLE_X
;
372 swizzles
[2] = SWIZZLE_X
;
373 swizzles
[3] = SWIZZLE_ONE
;
376 case GL_LUMINANCE_ALPHA
:
377 if (datatype
== GL_SIGNED_NORMALIZED
) {
378 swizzles
[0] = SWIZZLE_X
;
379 swizzles
[1] = SWIZZLE_X
;
380 swizzles
[2] = SWIZZLE_X
;
381 swizzles
[3] = SWIZZLE_W
;
385 if (datatype
== GL_SIGNED_NORMALIZED
) {
386 swizzles
[0] = SWIZZLE_X
;
387 swizzles
[1] = SWIZZLE_X
;
388 swizzles
[2] = SWIZZLE_X
;
389 swizzles
[3] = SWIZZLE_X
;
395 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
396 swizzles
[3] = SWIZZLE_ONE
;
400 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
401 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
402 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
403 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
407 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
408 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
410 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
413 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
415 * which is simply adding 4 then modding by 8 (or anding with 7).
417 * We then may need to apply workarounds for textureGather hardware bugs.
420 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
422 unsigned scs
= (swizzle
+ 4) & 7;
424 return (need_green_to_blue
&& scs
== HSW_SCS_GREEN
) ? HSW_SCS_BLUE
: scs
;
428 brw_find_matching_rb(const struct gl_framebuffer
*fb
,
429 const struct intel_mipmap_tree
*mt
)
431 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
432 const struct intel_renderbuffer
*irb
=
433 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
435 if (irb
&& irb
->mt
== mt
)
439 return fb
->_NumColorDrawBuffers
;
443 brw_texture_view_sane(const struct brw_context
*brw
,
444 const struct intel_mipmap_tree
*mt
,
445 const struct isl_view
*view
)
447 /* There are special cases only for lossless compression. */
448 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
451 if (isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
455 /* Logic elsewhere needs to take care to resolve the color buffer prior
456 * to sampling it as non-compressed.
458 if (intel_miptree_has_color_unresolved(mt
, view
->base_level
, view
->levels
,
459 view
->base_array_layer
,
463 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
464 const unsigned rb_index
= brw_find_matching_rb(fb
, mt
);
466 if (rb_index
== fb
->_NumColorDrawBuffers
)
469 /* Underlying surface is compressed but it is sampled using a format that
470 * the sampling engine doesn't support as compressed. Compression must be
471 * disabled for both sampling engine and data port in case the same surface
472 * is used also as render target.
474 return brw
->draw_aux_buffer_disabled
[rb_index
];
478 brw_disable_aux_surface(const struct brw_context
*brw
,
479 const struct intel_mipmap_tree
*mt
,
480 const struct isl_view
*view
)
482 /* Nothing to disable. */
486 const bool is_unresolved
= intel_miptree_has_color_unresolved(
487 mt
, view
->base_level
, view
->levels
,
488 view
->base_array_layer
, view
->array_len
);
490 /* There are special cases only for lossless compression. */
491 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
492 return !is_unresolved
;
494 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
495 const unsigned rb_index
= brw_find_matching_rb(fb
, mt
);
497 /* If we are drawing into this with compression enabled, then we must also
498 * enable compression when texturing from it regardless of
499 * fast_clear_state. If we don't then, after the first draw call with
500 * this setup, there will be data in the CCS which won't get picked up by
501 * subsequent texturing operations as required by ARB_texture_barrier.
502 * Since we don't want to re-emit the binding table or do a resolve
503 * operation every draw call, the easiest thing to do is just enable
504 * compression on the texturing side. This is completely safe to do
505 * since, if compressed texturing weren't allowed, we would have disabled
506 * compression of render targets in whatever_that_function_is_called().
508 if (rb_index
< fb
->_NumColorDrawBuffers
) {
509 if (brw
->draw_aux_buffer_disabled
[rb_index
]) {
510 assert(!is_unresolved
);
513 return brw
->draw_aux_buffer_disabled
[rb_index
];
516 return !is_unresolved
;
520 brw_update_texture_surface(struct gl_context
*ctx
,
522 uint32_t *surf_offset
,
526 struct brw_context
*brw
= brw_context(ctx
);
527 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
529 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
530 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
533 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
534 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
537 if (mt
->plane
[plane
- 1] == NULL
)
539 mt
= mt
->plane
[plane
- 1];
542 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
543 /* If this is a view with restricted NumLayers, then our effective depth
544 * is not just the miptree depth.
546 const unsigned view_num_layers
=
547 (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
) ? obj
->NumLayers
:
550 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
551 * texturing functions that return a float, as our code generation always
552 * selects the .x channel (which would always be 0).
554 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
555 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
556 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
557 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
558 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
559 brw_get_texture_swizzle(&brw
->ctx
, obj
));
561 mesa_format mesa_fmt
= plane
== 0 ? intel_obj
->_Format
: mt
->format
;
562 unsigned format
= translate_tex_format(brw
, mesa_fmt
,
563 sampler
->sRGBDecode
);
565 /* Implement gen6 and gen7 gather work-around */
566 bool need_green_to_blue
= false;
568 if (brw
->gen
== 7 && (format
== BRW_SURFACEFORMAT_R32G32_FLOAT
||
569 format
== BRW_SURFACEFORMAT_R32G32_SINT
||
570 format
== BRW_SURFACEFORMAT_R32G32_UINT
)) {
571 format
= BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
572 need_green_to_blue
= brw
->is_haswell
;
573 } else if (brw
->gen
== 6) {
574 /* Sandybridge's gather4 message is broken for integer formats.
575 * To work around this, we pretend the surface is UNORM for
576 * 8 or 16-bit formats, and emit shader instructions to recover
577 * the real INT/UINT value. For 32-bit formats, we pretend
578 * the surface is FLOAT, and simply reinterpret the resulting
582 case BRW_SURFACEFORMAT_R8_SINT
:
583 case BRW_SURFACEFORMAT_R8_UINT
:
584 format
= BRW_SURFACEFORMAT_R8_UNORM
;
587 case BRW_SURFACEFORMAT_R16_SINT
:
588 case BRW_SURFACEFORMAT_R16_UINT
:
589 format
= BRW_SURFACEFORMAT_R16_UNORM
;
592 case BRW_SURFACEFORMAT_R32_SINT
:
593 case BRW_SURFACEFORMAT_R32_UINT
:
594 format
= BRW_SURFACEFORMAT_R32_FLOAT
;
603 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
605 assert(mt
->r8stencil_mt
&& !mt
->stencil_mt
->r8stencil_needs_update
);
606 mt
= mt
->r8stencil_mt
;
610 format
= BRW_SURFACEFORMAT_R8_UINT
;
611 } else if (brw
->gen
<= 7 && mt
->format
== MESA_FORMAT_S_UINT8
) {
612 assert(mt
->r8stencil_mt
&& !mt
->r8stencil_needs_update
);
613 mt
= mt
->r8stencil_mt
;
614 format
= BRW_SURFACEFORMAT_R8_UINT
;
617 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
619 struct isl_view view
= {
621 .base_level
= obj
->MinLevel
+ obj
->BaseLevel
,
622 .levels
= intel_obj
->_MaxLevel
- obj
->BaseLevel
+ 1,
623 .base_array_layer
= obj
->MinLayer
,
624 .array_len
= view_num_layers
,
626 .r
= swizzle_to_scs(GET_SWZ(swizzle
, 0), need_green_to_blue
),
627 .g
= swizzle_to_scs(GET_SWZ(swizzle
, 1), need_green_to_blue
),
628 .b
= swizzle_to_scs(GET_SWZ(swizzle
, 2), need_green_to_blue
),
629 .a
= swizzle_to_scs(GET_SWZ(swizzle
, 3), need_green_to_blue
),
631 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
634 if (obj
->Target
== GL_TEXTURE_CUBE_MAP
||
635 obj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
636 view
.usage
|= ISL_SURF_USAGE_CUBE_BIT
;
638 assert(brw_texture_view_sane(brw
, mt
, &view
));
640 const int flags
= brw_disable_aux_surface(brw
, mt
, &view
) ?
641 INTEL_AUX_BUFFER_DISABLED
: 0;
642 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
644 surf_offset
, surf_index
,
645 I915_GEM_DOMAIN_SAMPLER
, 0);
650 brw_emit_buffer_surface_state(struct brw_context
*brw
,
651 uint32_t *out_offset
,
653 unsigned buffer_offset
,
654 unsigned surface_format
,
655 unsigned buffer_size
,
659 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
660 brw
->isl_dev
.ss
.size
,
661 brw
->isl_dev
.ss
.align
,
664 isl_buffer_fill_state(&brw
->isl_dev
, dw
,
665 .address
= (bo
? bo
->offset64
: 0) + buffer_offset
,
667 .format
= surface_format
,
669 .mocs
= tex_mocs
[brw
->gen
]);
672 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
673 *out_offset
+ brw
->isl_dev
.ss
.addr_offset
,
675 I915_GEM_DOMAIN_SAMPLER
,
676 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
681 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
683 uint32_t *surf_offset
)
685 struct brw_context
*brw
= brw_context(ctx
);
686 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
687 struct intel_buffer_object
*intel_obj
=
688 intel_buffer_object(tObj
->BufferObject
);
689 uint32_t size
= tObj
->BufferSize
;
690 drm_intel_bo
*bo
= NULL
;
691 mesa_format format
= tObj
->_BufferObjectFormat
;
692 uint32_t brw_format
= brw_format_for_mesa_format(format
);
693 int texel_size
= _mesa_get_format_bytes(format
);
696 size
= MIN2(size
, intel_obj
->Base
.Size
);
697 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
700 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
701 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
702 _mesa_get_format_name(format
));
705 brw_emit_buffer_surface_state(brw
, surf_offset
, bo
,
714 * Create the constant buffer surface. Vertex/fragment shader constants will be
715 * read from this buffer with Data Port Read instructions/messages.
718 brw_create_constant_surface(struct brw_context
*brw
,
722 uint32_t *out_offset
)
724 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
725 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
730 * Create the buffer surface. Shader buffer variables will be
731 * read from / write to this buffer with Data Port Read/Write
732 * instructions/messages.
735 brw_create_buffer_surface(struct brw_context
*brw
,
739 uint32_t *out_offset
)
741 /* Use a raw surface so we can reuse existing untyped read/write/atomic
742 * messages. We need these specifically for the fragment shader since they
743 * include a pixel mask header that we need to ensure correct behavior
744 * with helper invocations, which cannot write to the buffer.
746 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
747 BRW_SURFACEFORMAT_RAW
,
752 * Set up a binding table entry for use by stream output logic (transform
755 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
758 brw_update_sol_surface(struct brw_context
*brw
,
759 struct gl_buffer_object
*buffer_obj
,
760 uint32_t *out_offset
, unsigned num_vector_components
,
761 unsigned stride_dwords
, unsigned offset_dwords
)
763 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
764 uint32_t offset_bytes
= 4 * offset_dwords
;
765 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
767 buffer_obj
->Size
- offset_bytes
);
768 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
770 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
771 size_t size_dwords
= buffer_obj
->Size
/ 4;
772 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
774 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
775 * too big to map using a single binding table entry?
777 assert((size_dwords
- offset_dwords
) / stride_dwords
778 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
780 if (size_dwords
> offset_dwords
+ num_vector_components
) {
781 /* There is room for at least 1 transform feedback output in the buffer.
782 * Compute the number of additional transform feedback outputs the
783 * buffer has room for.
785 buffer_size_minus_1
=
786 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
788 /* There isn't even room for a single transform feedback output in the
789 * buffer. We can't configure the binding table entry to prevent output
790 * entirely; we'll have to rely on the geometry shader to detect
791 * overflow. But to minimize the damage in case of a bug, set up the
792 * binding table entry to just allow a single output.
794 buffer_size_minus_1
= 0;
796 width
= buffer_size_minus_1
& 0x7f;
797 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
798 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
800 switch (num_vector_components
) {
802 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
805 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
808 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
811 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
814 unreachable("Invalid vector size for transform feedback output");
817 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
818 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
819 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
820 BRW_SURFACE_RC_READ_WRITE
;
821 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
822 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
823 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
824 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
825 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
829 /* Emit relocation to surface contents. */
830 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
833 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
836 /* Creates a new WM constant buffer reflecting the current fragment program's
837 * constants, if needed by the fragment program.
839 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
843 brw_upload_wm_pull_constants(struct brw_context
*brw
)
845 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
846 /* BRW_NEW_FRAGMENT_PROGRAM */
847 struct brw_program
*fp
= (struct brw_program
*) brw
->fragment_program
;
848 /* BRW_NEW_FS_PROG_DATA */
849 struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
851 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
852 /* _NEW_PROGRAM_CONSTANTS */
853 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
,
854 stage_state
, prog_data
);
857 const struct brw_tracked_state brw_wm_pull_constants
= {
859 .mesa
= _NEW_PROGRAM_CONSTANTS
,
860 .brw
= BRW_NEW_BATCH
|
862 BRW_NEW_FRAGMENT_PROGRAM
|
863 BRW_NEW_FS_PROG_DATA
,
865 .emit
= brw_upload_wm_pull_constants
,
869 * Creates a null renderbuffer surface.
871 * This is used when the shader doesn't write to any color output. An FB
872 * write to target 0 will still be emitted, because that's how the thread is
873 * terminated (and computed depth is returned), so we need to have the
874 * hardware discard the target 0 color output..
877 brw_emit_null_surface_state(struct brw_context
*brw
,
881 uint32_t *out_offset
)
883 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
886 * A null surface will be used in instances where an actual surface is
887 * not bound. When a write message is generated to a null surface, no
888 * actual surface is written to. When a read message (including any
889 * sampling engine message) is generated to a null surface, the result
890 * is all zeros. Note that a null surface type is allowed to be used
891 * with all messages, even if it is not specificially indicated as
892 * supported. All of the remaining fields in surface state are ignored
893 * for null surfaces, with the following exceptions:
895 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
896 * depth buffer’s corresponding state for all render target surfaces,
899 * - Surface Format must be R8G8B8A8_UNORM.
901 unsigned surface_type
= BRW_SURFACE_NULL
;
902 drm_intel_bo
*bo
= NULL
;
903 unsigned pitch_minus_1
= 0;
904 uint32_t multisampling_state
= 0;
905 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
909 /* On Gen6, null render targets seem to cause GPU hangs when
910 * multisampling. So work around this problem by rendering into dummy
913 * To decrease the amount of memory needed by the workaround buffer, we
914 * set its pitch to 128 bytes (the width of a Y tile). This means that
915 * the amount of memory needed for the workaround buffer is
916 * (width_in_tiles + height_in_tiles - 1) tiles.
918 * Note that since the workaround buffer will be interpreted by the
919 * hardware as an interleaved multisampled buffer, we need to compute
920 * width_in_tiles and height_in_tiles by dividing the width and height
921 * by 16 rather than the normal Y-tile size of 32.
923 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
924 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
925 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
926 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
928 bo
= brw
->wm
.multisampled_null_render_target_bo
;
929 surface_type
= BRW_SURFACE_2D
;
931 multisampling_state
= brw_get_surface_num_multisamples(samples
);
934 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
935 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
937 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
938 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
939 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
940 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
942 surf
[1] = bo
? bo
->offset64
: 0;
943 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
944 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
946 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
949 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
951 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
952 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
953 surf
[4] = multisampling_state
;
957 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
960 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
965 * Sets up a surface state structure to point at the given region.
966 * While it is only used for the front/back buffer currently, it should be
967 * usable for further buffers when doing ARB_draw_buffer support.
970 gen4_update_renderbuffer_surface(struct brw_context
*brw
,
971 struct gl_renderbuffer
*rb
,
972 uint32_t flags
, unsigned unit
,
975 struct gl_context
*ctx
= &brw
->ctx
;
976 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
977 struct intel_mipmap_tree
*mt
= irb
->mt
;
979 uint32_t tile_x
, tile_y
;
983 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
984 /* BRW_NEW_FS_PROG_DATA */
986 assert(!(flags
& INTEL_RENDERBUFFER_LAYERED
));
987 assert(!(flags
& INTEL_AUX_BUFFER_DISABLED
));
989 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
990 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
992 if (tile_x
!= 0 || tile_y
!= 0) {
993 /* Original gen4 hardware couldn't draw to a non-tile-aligned
994 * destination in a miptree unless you actually setup your renderbuffer
995 * as a miptree and used the fragile lod/array_index/etc. controls to
996 * select the image. So, instead, we just make a new single-level
997 * miptree and render into that.
999 intel_renderbuffer_move_to_temp(brw
, irb
, false);
1004 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32, &offset
);
1006 format
= brw
->render_target_format
[rb_format
];
1007 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
1008 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
1009 __func__
, _mesa_get_format_name(rb_format
));
1012 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
1013 format
<< BRW_SURFACE_FORMAT_SHIFT
);
1016 assert(mt
->offset
% mt
->cpp
== 0);
1017 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
1018 mt
->bo
->offset64
+ mt
->offset
);
1020 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
1021 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
1023 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
1024 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
1026 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
1028 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
1029 /* Note that the low bits of these fields are missing, so
1030 * there's the possibility of getting in trouble.
1032 assert(tile_x
% 4 == 0);
1033 assert(tile_y
% 2 == 0);
1034 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
1035 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
1036 (mt
->valign
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
1040 if (!ctx
->Color
.ColorLogicOpEnabled
&& !ctx
->Color
._AdvancedBlendMode
&&
1041 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
1042 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
1044 if (!ctx
->Color
.ColorMask
[unit
][0])
1045 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
1046 if (!ctx
->Color
.ColorMask
[unit
][1])
1047 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
1048 if (!ctx
->Color
.ColorMask
[unit
][2])
1049 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
1051 /* As mentioned above, disable writes to the alpha component when the
1052 * renderbuffer is XRGB.
1054 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
1055 !ctx
->Color
.ColorMask
[unit
][3]) {
1056 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
1060 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1063 surf
[1] - mt
->bo
->offset64
,
1064 I915_GEM_DOMAIN_RENDER
,
1065 I915_GEM_DOMAIN_RENDER
);
1071 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1074 brw_update_renderbuffer_surfaces(struct brw_context
*brw
,
1075 const struct gl_framebuffer
*fb
,
1076 uint32_t render_target_start
,
1077 uint32_t *surf_offset
)
1080 const unsigned int w
= _mesa_geometric_width(fb
);
1081 const unsigned int h
= _mesa_geometric_height(fb
);
1082 const unsigned int s
= _mesa_geometric_samples(fb
);
1084 /* Update surfaces for drawing buffers */
1085 if (fb
->_NumColorDrawBuffers
>= 1) {
1086 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1087 const uint32_t surf_index
= render_target_start
+ i
;
1088 const int flags
= (_mesa_geometric_layers(fb
) > 0 ?
1089 INTEL_RENDERBUFFER_LAYERED
: 0) |
1090 (brw
->draw_aux_buffer_disabled
[i
] ?
1091 INTEL_AUX_BUFFER_DISABLED
: 0);
1093 if (intel_renderbuffer(fb
->_ColorDrawBuffers
[i
])) {
1094 surf_offset
[surf_index
] =
1095 brw
->vtbl
.update_renderbuffer_surface(
1096 brw
, fb
->_ColorDrawBuffers
[i
], flags
, i
, surf_index
);
1098 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1099 &surf_offset
[surf_index
]);
1103 const uint32_t surf_index
= render_target_start
;
1104 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1105 &surf_offset
[surf_index
]);
1110 update_renderbuffer_surfaces(struct brw_context
*brw
)
1112 const struct gl_context
*ctx
= &brw
->ctx
;
1114 /* BRW_NEW_FS_PROG_DATA */
1115 const struct brw_wm_prog_data
*wm_prog_data
=
1116 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1118 /* _NEW_BUFFERS | _NEW_COLOR */
1119 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1120 brw_update_renderbuffer_surfaces(
1122 wm_prog_data
->binding_table
.render_target_start
,
1123 brw
->wm
.base
.surf_offset
);
1124 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1127 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
1129 .mesa
= _NEW_BUFFERS
|
1131 .brw
= BRW_NEW_BATCH
|
1133 BRW_NEW_FS_PROG_DATA
,
1135 .emit
= update_renderbuffer_surfaces
,
1138 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
1140 .mesa
= _NEW_BUFFERS
,
1141 .brw
= BRW_NEW_BATCH
|
1144 .emit
= update_renderbuffer_surfaces
,
1148 update_renderbuffer_read_surfaces(struct brw_context
*brw
)
1150 const struct gl_context
*ctx
= &brw
->ctx
;
1152 /* BRW_NEW_FS_PROG_DATA */
1153 const struct brw_wm_prog_data
*wm_prog_data
=
1154 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1156 /* BRW_NEW_FRAGMENT_PROGRAM */
1157 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
1158 brw
->fragment_program
&& brw
->fragment_program
->info
.outputs_read
) {
1160 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1162 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1163 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[i
];
1164 const struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1165 const unsigned surf_index
=
1166 wm_prog_data
->binding_table
.render_target_read_start
+ i
;
1167 uint32_t *surf_offset
= &brw
->wm
.base
.surf_offset
[surf_index
];
1170 const unsigned format
= brw
->render_target_format
[
1171 _mesa_get_render_format(ctx
, intel_rb_format(irb
))];
1172 assert(isl_format_supports_sampling(&brw
->screen
->devinfo
,
1175 /* Override the target of the texture if the render buffer is a
1176 * single slice of a 3D texture (since the minimum array element
1177 * field of the surface state structure is ignored by the sampler
1178 * unit for 3D textures on some hardware), or if the render buffer
1179 * is a 1D array (since shaders always provide the array index
1180 * coordinate at the Z component to avoid state-dependent
1181 * recompiles when changing the texture target of the
1184 const GLenum target
=
1185 (irb
->mt
->target
== GL_TEXTURE_3D
&&
1186 irb
->layer_count
== 1) ? GL_TEXTURE_2D
:
1187 irb
->mt
->target
== GL_TEXTURE_1D_ARRAY
? GL_TEXTURE_2D_ARRAY
:
1190 /* intel_renderbuffer::mt_layer is expressed in sample units for
1191 * the UMS and CMS multisample layouts, but
1192 * intel_renderbuffer::layer_count is expressed in units of whole
1193 * logical layers regardless of the multisample layout.
1195 const unsigned mt_layer_unit
=
1196 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
1197 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
1198 MAX2(irb
->mt
->num_samples
, 1) : 1;
1200 const struct isl_view view
= {
1202 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
1204 .base_array_layer
= irb
->mt_layer
/ mt_layer_unit
,
1205 .array_len
= irb
->layer_count
,
1206 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1207 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
1210 const int flags
= brw
->draw_aux_buffer_disabled
[i
] ?
1211 INTEL_AUX_BUFFER_DISABLED
: 0;
1212 brw_emit_surface_state(brw
, irb
->mt
, flags
, target
, view
,
1214 surf_offset
, surf_index
,
1215 I915_GEM_DOMAIN_SAMPLER
, 0);
1218 brw
->vtbl
.emit_null_surface_state(
1219 brw
, _mesa_geometric_width(fb
), _mesa_geometric_height(fb
),
1220 _mesa_geometric_samples(fb
), surf_offset
);
1224 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1228 const struct brw_tracked_state brw_renderbuffer_read_surfaces
= {
1230 .mesa
= _NEW_BUFFERS
,
1231 .brw
= BRW_NEW_BATCH
|
1232 BRW_NEW_FRAGMENT_PROGRAM
|
1233 BRW_NEW_FS_PROG_DATA
,
1235 .emit
= update_renderbuffer_read_surfaces
,
1239 update_stage_texture_surfaces(struct brw_context
*brw
,
1240 const struct gl_program
*prog
,
1241 struct brw_stage_state
*stage_state
,
1242 bool for_gather
, uint32_t plane
)
1247 struct gl_context
*ctx
= &brw
->ctx
;
1249 uint32_t *surf_offset
= stage_state
->surf_offset
;
1251 /* BRW_NEW_*_PROG_DATA */
1253 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
1255 surf_offset
+= stage_state
->prog_data
->binding_table
.plane_start
[plane
];
1257 unsigned num_samplers
= util_last_bit(prog
->SamplersUsed
);
1258 for (unsigned s
= 0; s
< num_samplers
; s
++) {
1261 if (prog
->SamplersUsed
& (1 << s
)) {
1262 const unsigned unit
= prog
->SamplerUnits
[s
];
1265 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1266 brw_update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
, plane
);
1274 * Construct SURFACE_STATE objects for enabled textures.
1277 brw_update_texture_surfaces(struct brw_context
*brw
)
1279 /* BRW_NEW_VERTEX_PROGRAM */
1280 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
1282 /* BRW_NEW_TESS_PROGRAMS */
1283 struct gl_program
*tcs
= (struct gl_program
*) brw
->tess_ctrl_program
;
1284 struct gl_program
*tes
= (struct gl_program
*) brw
->tess_eval_program
;
1286 /* BRW_NEW_GEOMETRY_PROGRAM */
1287 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
1289 /* BRW_NEW_FRAGMENT_PROGRAM */
1290 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
1293 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false, 0);
1294 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, false, 0);
1295 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, false, 0);
1296 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false, 0);
1297 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 0);
1299 /* emit alternate set of surface state for gather. this
1300 * allows the surface format to be overriden for only the
1301 * gather4 messages. */
1303 if (vs
&& vs
->nir
->info
->uses_texture_gather
)
1304 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true, 0);
1305 if (tcs
&& tcs
->nir
->info
->uses_texture_gather
)
1306 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, true, 0);
1307 if (tes
&& tes
->nir
->info
->uses_texture_gather
)
1308 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, true, 0);
1309 if (gs
&& gs
->nir
->info
->uses_texture_gather
)
1310 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true, 0);
1311 if (fs
&& fs
->nir
->info
->uses_texture_gather
)
1312 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true, 0);
1316 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 1);
1317 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 2);
1320 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1323 const struct brw_tracked_state brw_texture_surfaces
= {
1325 .mesa
= _NEW_TEXTURE
,
1326 .brw
= BRW_NEW_BATCH
|
1328 BRW_NEW_FRAGMENT_PROGRAM
|
1329 BRW_NEW_FS_PROG_DATA
|
1330 BRW_NEW_GEOMETRY_PROGRAM
|
1331 BRW_NEW_GS_PROG_DATA
|
1332 BRW_NEW_TESS_PROGRAMS
|
1333 BRW_NEW_TCS_PROG_DATA
|
1334 BRW_NEW_TES_PROG_DATA
|
1335 BRW_NEW_TEXTURE_BUFFER
|
1336 BRW_NEW_VERTEX_PROGRAM
|
1337 BRW_NEW_VS_PROG_DATA
,
1339 .emit
= brw_update_texture_surfaces
,
1343 brw_update_cs_texture_surfaces(struct brw_context
*brw
)
1345 /* BRW_NEW_COMPUTE_PROGRAM */
1346 struct gl_program
*cs
= (struct gl_program
*) brw
->compute_program
;
1349 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, false, 0);
1351 /* emit alternate set of surface state for gather. this
1352 * allows the surface format to be overriden for only the
1356 if (cs
&& cs
->nir
->info
->uses_texture_gather
)
1357 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, true, 0);
1360 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1363 const struct brw_tracked_state brw_cs_texture_surfaces
= {
1365 .mesa
= _NEW_TEXTURE
,
1366 .brw
= BRW_NEW_BATCH
|
1368 BRW_NEW_COMPUTE_PROGRAM
,
1370 .emit
= brw_update_cs_texture_surfaces
,
1375 brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1376 struct brw_stage_state
*stage_state
,
1377 struct brw_stage_prog_data
*prog_data
)
1379 struct gl_context
*ctx
= &brw
->ctx
;
1384 uint32_t *ubo_surf_offsets
=
1385 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
1387 for (int i
= 0; i
< prog
->info
.num_ubos
; i
++) {
1388 struct gl_uniform_buffer_binding
*binding
=
1389 &ctx
->UniformBufferBindings
[prog
->sh
.UniformBlocks
[i
]->Binding
];
1391 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1392 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ubo_surf_offsets
[i
]);
1394 struct intel_buffer_object
*intel_bo
=
1395 intel_buffer_object(binding
->BufferObject
);
1396 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1397 if (!binding
->AutomaticSize
)
1398 size
= MIN2(size
, binding
->Size
);
1400 intel_bufferobj_buffer(brw
, intel_bo
,
1403 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
1405 &ubo_surf_offsets
[i
]);
1409 uint32_t *ssbo_surf_offsets
=
1410 &stage_state
->surf_offset
[prog_data
->binding_table
.ssbo_start
];
1412 for (int i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
1413 struct gl_shader_storage_buffer_binding
*binding
=
1414 &ctx
->ShaderStorageBufferBindings
[prog
->sh
.ShaderStorageBlocks
[i
]->Binding
];
1416 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1417 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ssbo_surf_offsets
[i
]);
1419 struct intel_buffer_object
*intel_bo
=
1420 intel_buffer_object(binding
->BufferObject
);
1421 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1422 if (!binding
->AutomaticSize
)
1423 size
= MIN2(size
, binding
->Size
);
1425 intel_bufferobj_buffer(brw
, intel_bo
,
1428 brw_create_buffer_surface(brw
, bo
, binding
->Offset
,
1430 &ssbo_surf_offsets
[i
]);
1434 if (prog
->info
.num_ubos
|| prog
->info
.num_ssbos
)
1435 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1439 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
1441 struct gl_context
*ctx
= &brw
->ctx
;
1443 struct gl_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
1445 /* BRW_NEW_FS_PROG_DATA */
1446 brw_upload_ubo_surfaces(brw
, prog
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1449 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
1451 .mesa
= _NEW_PROGRAM
,
1452 .brw
= BRW_NEW_BATCH
|
1454 BRW_NEW_FS_PROG_DATA
|
1455 BRW_NEW_UNIFORM_BUFFER
,
1457 .emit
= brw_upload_wm_ubo_surfaces
,
1461 brw_upload_cs_ubo_surfaces(struct brw_context
*brw
)
1463 struct gl_context
*ctx
= &brw
->ctx
;
1465 struct gl_shader_program
*prog
=
1466 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1468 if (!prog
|| !prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
])
1471 /* BRW_NEW_CS_PROG_DATA */
1472 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
]->Program
,
1473 &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1476 const struct brw_tracked_state brw_cs_ubo_surfaces
= {
1478 .mesa
= _NEW_PROGRAM
,
1479 .brw
= BRW_NEW_BATCH
|
1481 BRW_NEW_CS_PROG_DATA
|
1482 BRW_NEW_UNIFORM_BUFFER
,
1484 .emit
= brw_upload_cs_ubo_surfaces
,
1488 brw_upload_abo_surfaces(struct brw_context
*brw
,
1489 const struct gl_program
*prog
,
1490 struct brw_stage_state
*stage_state
,
1491 struct brw_stage_prog_data
*prog_data
)
1493 struct gl_context
*ctx
= &brw
->ctx
;
1494 uint32_t *surf_offsets
=
1495 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
1497 if (prog
->info
.num_abos
) {
1498 for (unsigned i
= 0; i
< prog
->info
.num_abos
; i
++) {
1499 struct gl_atomic_buffer_binding
*binding
=
1500 &ctx
->AtomicBufferBindings
[prog
->sh
.AtomicBuffers
[i
]->Binding
];
1501 struct intel_buffer_object
*intel_bo
=
1502 intel_buffer_object(binding
->BufferObject
);
1503 drm_intel_bo
*bo
= intel_bufferobj_buffer(
1504 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
1506 brw_emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
1507 binding
->Offset
, BRW_SURFACEFORMAT_RAW
,
1508 bo
->size
- binding
->Offset
, 1, true);
1511 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1516 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
1519 const struct gl_program
*wm
= brw
->fragment_program
;
1522 /* BRW_NEW_FS_PROG_DATA */
1523 brw_upload_abo_surfaces(brw
, wm
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1527 const struct brw_tracked_state brw_wm_abo_surfaces
= {
1529 .mesa
= _NEW_PROGRAM
,
1530 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1533 BRW_NEW_FS_PROG_DATA
,
1535 .emit
= brw_upload_wm_abo_surfaces
,
1539 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1542 const struct gl_program
*cp
= brw
->compute_program
;
1545 /* BRW_NEW_CS_PROG_DATA */
1546 brw_upload_abo_surfaces(brw
, cp
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1550 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1552 .mesa
= _NEW_PROGRAM
,
1553 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1556 BRW_NEW_CS_PROG_DATA
,
1558 .emit
= brw_upload_cs_abo_surfaces
,
1562 brw_upload_cs_image_surfaces(struct brw_context
*brw
)
1565 const struct gl_program
*cp
= brw
->compute_program
;
1568 /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1569 brw_upload_image_surfaces(brw
, cp
, &brw
->cs
.base
,
1570 brw
->cs
.base
.prog_data
);
1574 const struct brw_tracked_state brw_cs_image_surfaces
= {
1576 .mesa
= _NEW_TEXTURE
| _NEW_PROGRAM
,
1577 .brw
= BRW_NEW_BATCH
|
1579 BRW_NEW_CS_PROG_DATA
|
1582 .emit
= brw_upload_cs_image_surfaces
,
1586 get_image_format(struct brw_context
*brw
, mesa_format format
, GLenum access
)
1588 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1589 uint32_t hw_format
= brw_format_for_mesa_format(format
);
1590 if (access
== GL_WRITE_ONLY
) {
1592 } else if (isl_has_matching_typed_storage_image_format(devinfo
, hw_format
)) {
1593 /* Typed surface reads support a very limited subset of the shader
1594 * image formats. Translate it into the closest format the
1595 * hardware supports.
1597 return isl_lower_storage_image_format(devinfo
, hw_format
);
1599 /* The hardware doesn't actually support a typed format that we can use
1600 * so we have to fall back to untyped read/write messages.
1602 return BRW_SURFACEFORMAT_RAW
;
1607 update_default_image_param(struct brw_context
*brw
,
1608 struct gl_image_unit
*u
,
1609 unsigned surface_idx
,
1610 struct brw_image_param
*param
)
1612 memset(param
, 0, sizeof(*param
));
1613 param
->surface_idx
= surface_idx
;
1614 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1615 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1616 * detailed explanation of these parameters.
1618 param
->swizzling
[0] = 0xff;
1619 param
->swizzling
[1] = 0xff;
1623 update_buffer_image_param(struct brw_context
*brw
,
1624 struct gl_image_unit
*u
,
1625 unsigned surface_idx
,
1626 struct brw_image_param
*param
)
1628 struct gl_buffer_object
*obj
= u
->TexObj
->BufferObject
;
1629 const uint32_t size
= MIN2((uint32_t)u
->TexObj
->BufferSize
, obj
->Size
);
1630 update_default_image_param(brw
, u
, surface_idx
, param
);
1632 param
->size
[0] = size
/ _mesa_get_format_bytes(u
->_ActualFormat
);
1633 param
->stride
[0] = _mesa_get_format_bytes(u
->_ActualFormat
);
1637 update_texture_image_param(struct brw_context
*brw
,
1638 struct gl_image_unit
*u
,
1639 unsigned surface_idx
,
1640 struct brw_image_param
*param
)
1642 struct intel_mipmap_tree
*mt
= intel_texture_object(u
->TexObj
)->mt
;
1644 update_default_image_param(brw
, u
, surface_idx
, param
);
1646 param
->size
[0] = minify(mt
->logical_width0
, u
->Level
);
1647 param
->size
[1] = minify(mt
->logical_height0
, u
->Level
);
1648 param
->size
[2] = (!u
->Layered
? 1 :
1649 u
->TexObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1650 u
->TexObj
->Target
== GL_TEXTURE_3D
?
1651 minify(mt
->logical_depth0
, u
->Level
) :
1652 mt
->logical_depth0
);
1654 intel_miptree_get_image_offset(mt
, u
->Level
, u
->_Layer
,
1658 param
->stride
[0] = mt
->cpp
;
1659 param
->stride
[1] = mt
->pitch
/ mt
->cpp
;
1661 brw_miptree_get_horizontal_slice_pitch(brw
, mt
, u
->Level
);
1663 brw_miptree_get_vertical_slice_pitch(brw
, mt
, u
->Level
);
1665 if (mt
->tiling
== I915_TILING_X
) {
1666 /* An X tile is a rectangular block of 512x8 bytes. */
1667 param
->tiling
[0] = _mesa_logbase2(512 / mt
->cpp
);
1668 param
->tiling
[1] = _mesa_logbase2(8);
1670 if (brw
->has_swizzling
) {
1671 /* Right shifts required to swizzle bits 9 and 10 of the memory
1672 * address with bit 6.
1674 param
->swizzling
[0] = 3;
1675 param
->swizzling
[1] = 4;
1677 } else if (mt
->tiling
== I915_TILING_Y
) {
1678 /* The layout of a Y-tiled surface in memory isn't really fundamentally
1679 * different to the layout of an X-tiled surface, we simply pretend that
1680 * the surface is broken up in a number of smaller 16Bx32 tiles, each
1681 * one arranged in X-major order just like is the case for X-tiling.
1683 param
->tiling
[0] = _mesa_logbase2(16 / mt
->cpp
);
1684 param
->tiling
[1] = _mesa_logbase2(32);
1686 if (brw
->has_swizzling
) {
1687 /* Right shift required to swizzle bit 9 of the memory address with
1690 param
->swizzling
[0] = 3;
1694 /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
1695 * address calculation algorithm (emit_address_calculation() in
1696 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
1697 * modulus equal to the LOD.
1699 param
->tiling
[2] = (u
->TexObj
->Target
== GL_TEXTURE_3D
? u
->Level
:
1704 update_image_surface(struct brw_context
*brw
,
1705 struct gl_image_unit
*u
,
1707 unsigned surface_idx
,
1708 uint32_t *surf_offset
,
1709 struct brw_image_param
*param
)
1711 if (_mesa_is_image_unit_valid(&brw
->ctx
, u
)) {
1712 struct gl_texture_object
*obj
= u
->TexObj
;
1713 const unsigned format
= get_image_format(brw
, u
->_ActualFormat
, access
);
1715 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
1716 struct intel_buffer_object
*intel_obj
=
1717 intel_buffer_object(obj
->BufferObject
);
1718 const unsigned texel_size
= (format
== BRW_SURFACEFORMAT_RAW
? 1 :
1719 _mesa_get_format_bytes(u
->_ActualFormat
));
1721 brw_emit_buffer_surface_state(
1722 brw
, surf_offset
, intel_obj
->buffer
, obj
->BufferOffset
,
1723 format
, intel_obj
->Base
.Size
, texel_size
,
1724 access
!= GL_READ_ONLY
);
1726 update_buffer_image_param(brw
, u
, surface_idx
, param
);
1729 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
1730 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
1732 if (format
== BRW_SURFACEFORMAT_RAW
) {
1733 brw_emit_buffer_surface_state(
1734 brw
, surf_offset
, mt
->bo
, mt
->offset
,
1735 format
, mt
->bo
->size
- mt
->offset
, 1 /* pitch */,
1736 access
!= GL_READ_ONLY
);
1739 const unsigned num_layers
= (!u
->Layered
? 1 :
1740 obj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1741 mt
->logical_depth0
);
1743 struct isl_view view
= {
1745 .base_level
= obj
->MinLevel
+ u
->Level
,
1747 .base_array_layer
= obj
->MinLayer
+ u
->_Layer
,
1748 .array_len
= num_layers
,
1749 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1750 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
1753 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
1754 const bool unresolved
= intel_miptree_has_color_unresolved(
1755 mt
, view
.base_level
, view
.levels
,
1756 view
.base_array_layer
, view
.array_len
);
1757 const int flags
= unresolved
? 0 : INTEL_AUX_BUFFER_DISABLED
;
1758 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
1760 surf_offset
, surf_index
,
1761 I915_GEM_DOMAIN_SAMPLER
,
1762 access
== GL_READ_ONLY
? 0 :
1763 I915_GEM_DOMAIN_SAMPLER
);
1766 update_texture_image_param(brw
, u
, surface_idx
, param
);
1770 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, surf_offset
);
1771 update_default_image_param(brw
, u
, surface_idx
, param
);
1776 brw_upload_image_surfaces(struct brw_context
*brw
,
1777 const struct gl_program
*prog
,
1778 struct brw_stage_state
*stage_state
,
1779 struct brw_stage_prog_data
*prog_data
)
1782 struct gl_context
*ctx
= &brw
->ctx
;
1784 if (prog
->info
.num_images
) {
1785 for (unsigned i
= 0; i
< prog
->info
.num_images
; i
++) {
1786 struct gl_image_unit
*u
= &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[i
]];
1787 const unsigned surf_idx
= prog_data
->binding_table
.image_start
+ i
;
1789 update_image_surface(brw
, u
, prog
->sh
.ImageAccess
[i
],
1791 &stage_state
->surf_offset
[surf_idx
],
1792 &prog_data
->image_param
[i
]);
1795 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1796 /* This may have changed the image metadata dependent on the context
1797 * image unit state and passed to the program as uniforms, make sure
1798 * that push and pull constants are reuploaded.
1800 brw
->NewGLState
|= _NEW_PROGRAM_CONSTANTS
;
1805 brw_upload_wm_image_surfaces(struct brw_context
*brw
)
1807 /* BRW_NEW_FRAGMENT_PROGRAM */
1808 const struct gl_program
*wm
= brw
->fragment_program
;
1811 /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1812 brw_upload_image_surfaces(brw
, wm
, &brw
->wm
.base
,
1813 brw
->wm
.base
.prog_data
);
1817 const struct brw_tracked_state brw_wm_image_surfaces
= {
1819 .mesa
= _NEW_TEXTURE
,
1820 .brw
= BRW_NEW_BATCH
|
1822 BRW_NEW_FRAGMENT_PROGRAM
|
1823 BRW_NEW_FS_PROG_DATA
|
1826 .emit
= brw_upload_wm_image_surfaces
,
1830 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
1832 brw
->vtbl
.update_renderbuffer_surface
= gen4_update_renderbuffer_surface
;
1833 brw
->vtbl
.emit_null_surface_state
= brw_emit_null_surface_state
;
1837 gen6_init_vtable_surface_functions(struct brw_context
*brw
)
1839 gen4_init_vtable_surface_functions(brw
);
1840 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
1844 brw_upload_cs_work_groups_surface(struct brw_context
*brw
)
1846 struct gl_context
*ctx
= &brw
->ctx
;
1848 struct gl_shader_program
*prog
=
1849 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1850 /* BRW_NEW_CS_PROG_DATA */
1851 const struct brw_cs_prog_data
*cs_prog_data
=
1852 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
1854 if (prog
&& cs_prog_data
->uses_num_work_groups
) {
1855 const unsigned surf_idx
=
1856 cs_prog_data
->binding_table
.work_groups_start
;
1857 uint32_t *surf_offset
= &brw
->cs
.base
.surf_offset
[surf_idx
];
1861 if (brw
->compute
.num_work_groups_bo
== NULL
) {
1863 intel_upload_data(brw
,
1864 (void *)brw
->compute
.num_work_groups
,
1870 bo
= brw
->compute
.num_work_groups_bo
;
1871 bo_offset
= brw
->compute
.num_work_groups_offset
;
1874 brw_emit_buffer_surface_state(brw
, surf_offset
,
1876 BRW_SURFACEFORMAT_RAW
,
1877 3 * sizeof(GLuint
), 1, true);
1878 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1882 const struct brw_tracked_state brw_cs_work_groups_surface
= {
1884 .brw
= BRW_NEW_BLORP
|
1885 BRW_NEW_CS_PROG_DATA
|
1886 BRW_NEW_CS_WORK_GROUPS
1888 .emit
= brw_upload_cs_work_groups_surface
,