2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "program/prog_parameter.h"
39 #include "intel_mipmap_tree.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_fbo.h"
43 #include "intel_buffer_objects.h"
45 #include "brw_context.h"
46 #include "brw_state.h"
47 #include "brw_defines.h"
51 translate_tex_target(GLenum target
)
55 case GL_TEXTURE_1D_ARRAY_EXT
:
56 return BRW_SURFACE_1D
;
58 case GL_TEXTURE_RECTANGLE_NV
:
59 return BRW_SURFACE_2D
;
62 case GL_TEXTURE_2D_ARRAY_EXT
:
63 case GL_TEXTURE_EXTERNAL_OES
:
64 case GL_TEXTURE_2D_MULTISAMPLE
:
65 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
66 return BRW_SURFACE_2D
;
69 return BRW_SURFACE_3D
;
71 case GL_TEXTURE_CUBE_MAP
:
72 case GL_TEXTURE_CUBE_MAP_ARRAY
:
73 return BRW_SURFACE_CUBE
;
76 unreachable("not reached");
81 brw_get_surface_tiling_bits(uint32_t tiling
)
85 return BRW_SURFACE_TILED
;
87 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
95 brw_get_surface_num_multisamples(unsigned num_samples
)
98 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
100 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
104 brw_configure_w_tiled(const struct intel_mipmap_tree
*mt
,
105 bool is_render_target
,
106 unsigned *width
, unsigned *height
,
107 unsigned *pitch
, uint32_t *tiling
, unsigned *format
)
109 static const unsigned halign_stencil
= 8;
111 /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
112 * there are half as many rows.
113 * In addition, mip-levels are accessed manually by the program and
114 * therefore the surface is setup to cover all the mip-levels for one slice.
115 * (Hardware is still used to access individual slices).
117 *tiling
= I915_TILING_Y
;
118 *pitch
= mt
->pitch
* 2;
119 *width
= ALIGN(mt
->total_width
, halign_stencil
) * 2;
120 *height
= (mt
->total_height
/ mt
->physical_depth0
) / 2;
122 if (is_render_target
) {
123 *format
= BRW_SURFACEFORMAT_R8_UINT
;
129 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
133 brw_get_texture_swizzle(const struct gl_context
*ctx
,
134 const struct gl_texture_object
*t
)
136 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
138 int swizzles
[SWIZZLE_NIL
+ 1] = {
148 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
149 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
150 GLenum depth_mode
= t
->DepthMode
;
152 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
153 * with depth component data specified with a sized internal format.
154 * Otherwise, it's left at the old default, GL_LUMINANCE.
156 if (_mesa_is_gles3(ctx
) &&
157 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
158 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
162 switch (depth_mode
) {
164 swizzles
[0] = SWIZZLE_ZERO
;
165 swizzles
[1] = SWIZZLE_ZERO
;
166 swizzles
[2] = SWIZZLE_ZERO
;
167 swizzles
[3] = SWIZZLE_X
;
170 swizzles
[0] = SWIZZLE_X
;
171 swizzles
[1] = SWIZZLE_X
;
172 swizzles
[2] = SWIZZLE_X
;
173 swizzles
[3] = SWIZZLE_ONE
;
176 swizzles
[0] = SWIZZLE_X
;
177 swizzles
[1] = SWIZZLE_X
;
178 swizzles
[2] = SWIZZLE_X
;
179 swizzles
[3] = SWIZZLE_X
;
182 swizzles
[0] = SWIZZLE_X
;
183 swizzles
[1] = SWIZZLE_ZERO
;
184 swizzles
[2] = SWIZZLE_ZERO
;
185 swizzles
[3] = SWIZZLE_ONE
;
190 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
192 /* If the texture's format is alpha-only, force R, G, and B to
193 * 0.0. Similarly, if the texture's format has no alpha channel,
194 * force the alpha value read to 1.0. This allows for the
195 * implementation to use an RGBA texture for any of these formats
196 * without leaking any unexpected values.
198 switch (img
->_BaseFormat
) {
200 swizzles
[0] = SWIZZLE_ZERO
;
201 swizzles
[1] = SWIZZLE_ZERO
;
202 swizzles
[2] = SWIZZLE_ZERO
;
205 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
206 swizzles
[0] = SWIZZLE_X
;
207 swizzles
[1] = SWIZZLE_X
;
208 swizzles
[2] = SWIZZLE_X
;
209 swizzles
[3] = SWIZZLE_ONE
;
212 case GL_LUMINANCE_ALPHA
:
213 if (datatype
== GL_SIGNED_NORMALIZED
) {
214 swizzles
[0] = SWIZZLE_X
;
215 swizzles
[1] = SWIZZLE_X
;
216 swizzles
[2] = SWIZZLE_X
;
217 swizzles
[3] = SWIZZLE_W
;
221 if (datatype
== GL_SIGNED_NORMALIZED
) {
222 swizzles
[0] = SWIZZLE_X
;
223 swizzles
[1] = SWIZZLE_X
;
224 swizzles
[2] = SWIZZLE_X
;
225 swizzles
[3] = SWIZZLE_X
;
231 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
232 swizzles
[3] = SWIZZLE_ONE
;
236 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
237 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
238 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
239 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
243 gen4_emit_buffer_surface_state(struct brw_context
*brw
,
244 uint32_t *out_offset
,
246 unsigned buffer_offset
,
247 unsigned surface_format
,
248 unsigned buffer_size
,
252 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
253 6 * 4, 32, out_offset
);
254 memset(surf
, 0, 6 * 4);
256 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
257 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
258 (brw
->gen
>= 6 ? BRW_SURFACE_RC_READ_WRITE
: 0);
259 surf
[1] = (bo
? bo
->offset64
: 0) + buffer_offset
; /* reloc */
260 surf
[2] = (buffer_size
& 0x7f) << BRW_SURFACE_WIDTH_SHIFT
|
261 ((buffer_size
>> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT
;
262 surf
[3] = ((buffer_size
>> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT
|
263 (pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
;
265 /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
266 * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
267 * physical cache. It is mapped in hardware to the sampler cache."
270 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
272 I915_GEM_DOMAIN_SAMPLER
,
273 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
278 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
280 uint32_t *surf_offset
)
282 struct brw_context
*brw
= brw_context(ctx
);
283 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
284 struct intel_buffer_object
*intel_obj
=
285 intel_buffer_object(tObj
->BufferObject
);
286 uint32_t size
= tObj
->BufferSize
;
287 drm_intel_bo
*bo
= NULL
;
288 mesa_format format
= tObj
->_BufferObjectFormat
;
289 uint32_t brw_format
= brw_format_for_mesa_format(format
);
290 int texel_size
= _mesa_get_format_bytes(format
);
293 size
= MIN2(size
, intel_obj
->Base
.Size
);
294 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
297 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
298 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
299 _mesa_get_format_name(format
));
302 brw
->vtbl
.emit_buffer_surface_state(brw
, surf_offset
, bo
,
311 brw_update_texture_surface(struct gl_context
*ctx
,
313 uint32_t *surf_offset
,
316 struct brw_context
*brw
= brw_context(ctx
);
317 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
318 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
319 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
320 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
323 /* BRW_NEW_TEXTURE_BUFFER */
324 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
325 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
329 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
330 6 * 4, 32, surf_offset
);
332 uint32_t tex_format
= translate_tex_format(brw
, mt
->format
,
333 sampler
->sRGBDecode
);
336 /* Sandybridge's gather4 message is broken for integer formats.
337 * To work around this, we pretend the surface is UNORM for
338 * 8 or 16-bit formats, and emit shader instructions to recover
339 * the real INT/UINT value. For 32-bit formats, we pretend
340 * the surface is FLOAT, and simply reinterpret the resulting
343 switch (tex_format
) {
344 case BRW_SURFACEFORMAT_R8_SINT
:
345 case BRW_SURFACEFORMAT_R8_UINT
:
346 tex_format
= BRW_SURFACEFORMAT_R8_UNORM
;
349 case BRW_SURFACEFORMAT_R16_SINT
:
350 case BRW_SURFACEFORMAT_R16_UINT
:
351 tex_format
= BRW_SURFACEFORMAT_R16_UNORM
;
354 case BRW_SURFACEFORMAT_R32_SINT
:
355 case BRW_SURFACEFORMAT_R32_UINT
:
356 tex_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
364 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
365 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
366 BRW_SURFACE_CUBEFACE_ENABLES
|
367 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
);
369 surf
[1] = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
371 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
372 (mt
->logical_width0
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
373 (mt
->logical_height0
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
375 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
376 (mt
->logical_depth0
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
377 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
379 surf
[4] = (brw_get_surface_num_multisamples(mt
->num_samples
) |
380 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
, BRW_SURFACE_MIN_LOD
));
382 surf
[5] = mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0;
384 /* Emit relocation to surface contents */
385 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
388 surf
[1] - mt
->bo
->offset64
,
389 I915_GEM_DOMAIN_SAMPLER
, 0);
393 * Create the constant buffer surface. Vertex/fragment shader constants will be
394 * read from this buffer with Data Port Read instructions/messages.
397 brw_create_constant_surface(struct brw_context
*brw
,
401 uint32_t *out_offset
,
404 uint32_t stride
= dword_pitch
? 4 : 16;
405 uint32_t elements
= ALIGN(size
, stride
) / stride
;
407 brw
->vtbl
.emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
408 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
409 elements
, stride
, false);
413 * Set up a binding table entry for use by stream output logic (transform
416 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
419 brw_update_sol_surface(struct brw_context
*brw
,
420 struct gl_buffer_object
*buffer_obj
,
421 uint32_t *out_offset
, unsigned num_vector_components
,
422 unsigned stride_dwords
, unsigned offset_dwords
)
424 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
425 uint32_t offset_bytes
= 4 * offset_dwords
;
426 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
428 buffer_obj
->Size
- offset_bytes
);
429 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
431 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
432 size_t size_dwords
= buffer_obj
->Size
/ 4;
433 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
435 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
436 * too big to map using a single binding table entry?
438 assert((size_dwords
- offset_dwords
) / stride_dwords
439 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
441 if (size_dwords
> offset_dwords
+ num_vector_components
) {
442 /* There is room for at least 1 transform feedback output in the buffer.
443 * Compute the number of additional transform feedback outputs the
444 * buffer has room for.
446 buffer_size_minus_1
=
447 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
449 /* There isn't even room for a single transform feedback output in the
450 * buffer. We can't configure the binding table entry to prevent output
451 * entirely; we'll have to rely on the geometry shader to detect
452 * overflow. But to minimize the damage in case of a bug, set up the
453 * binding table entry to just allow a single output.
455 buffer_size_minus_1
= 0;
457 width
= buffer_size_minus_1
& 0x7f;
458 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
459 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
461 switch (num_vector_components
) {
463 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
466 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
469 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
472 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
475 unreachable("Invalid vector size for transform feedback output");
478 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
479 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
480 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
481 BRW_SURFACE_RC_READ_WRITE
;
482 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
483 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
484 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
485 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
486 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
490 /* Emit relocation to surface contents. */
491 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
494 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
497 /* Creates a new WM constant buffer reflecting the current fragment program's
498 * constants, if needed by the fragment program.
500 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
504 brw_upload_wm_pull_constants(struct brw_context
*brw
)
506 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
507 /* BRW_NEW_FRAGMENT_PROGRAM */
508 struct brw_fragment_program
*fp
=
509 (struct brw_fragment_program
*) brw
->fragment_program
;
510 /* BRW_NEW_FS_PROG_DATA */
511 struct brw_stage_prog_data
*prog_data
= &brw
->wm
.prog_data
->base
;
513 /* _NEW_PROGRAM_CONSTANTS */
514 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
.Base
,
515 stage_state
, prog_data
, true);
518 const struct brw_tracked_state brw_wm_pull_constants
= {
520 .mesa
= _NEW_PROGRAM_CONSTANTS
,
521 .brw
= BRW_NEW_BATCH
|
522 BRW_NEW_FRAGMENT_PROGRAM
|
523 BRW_NEW_FS_PROG_DATA
,
525 .emit
= brw_upload_wm_pull_constants
,
529 * Creates a null renderbuffer surface.
531 * This is used when the shader doesn't write to any color output. An FB
532 * write to target 0 will still be emitted, because that's how the thread is
533 * terminated (and computed depth is returned), so we need to have the
534 * hardware discard the target 0 color output..
537 brw_emit_null_surface_state(struct brw_context
*brw
,
541 uint32_t *out_offset
)
543 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
546 * A null surface will be used in instances where an actual surface is
547 * not bound. When a write message is generated to a null surface, no
548 * actual surface is written to. When a read message (including any
549 * sampling engine message) is generated to a null surface, the result
550 * is all zeros. Note that a null surface type is allowed to be used
551 * with all messages, even if it is not specificially indicated as
552 * supported. All of the remaining fields in surface state are ignored
553 * for null surfaces, with the following exceptions:
555 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
556 * depth buffer’s corresponding state for all render target surfaces,
559 * - Surface Format must be R8G8B8A8_UNORM.
561 unsigned surface_type
= BRW_SURFACE_NULL
;
562 drm_intel_bo
*bo
= NULL
;
563 unsigned pitch_minus_1
= 0;
564 uint32_t multisampling_state
= 0;
565 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
569 /* On Gen6, null render targets seem to cause GPU hangs when
570 * multisampling. So work around this problem by rendering into dummy
573 * To decrease the amount of memory needed by the workaround buffer, we
574 * set its pitch to 128 bytes (the width of a Y tile). This means that
575 * the amount of memory needed for the workaround buffer is
576 * (width_in_tiles + height_in_tiles - 1) tiles.
578 * Note that since the workaround buffer will be interpreted by the
579 * hardware as an interleaved multisampled buffer, we need to compute
580 * width_in_tiles and height_in_tiles by dividing the width and height
581 * by 16 rather than the normal Y-tile size of 32.
583 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
584 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
585 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
586 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
588 bo
= brw
->wm
.multisampled_null_render_target_bo
;
589 surface_type
= BRW_SURFACE_2D
;
591 multisampling_state
= brw_get_surface_num_multisamples(samples
);
594 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
595 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
597 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
598 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
599 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
600 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
602 surf
[1] = bo
? bo
->offset64
: 0;
603 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
604 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
606 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
609 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
611 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
612 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
613 surf
[4] = multisampling_state
;
617 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
620 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
625 * Sets up a surface state structure to point at the given region.
626 * While it is only used for the front/back buffer currently, it should be
627 * usable for further buffers when doing ARB_draw_buffer support.
630 brw_update_renderbuffer_surface(struct brw_context
*brw
,
631 struct gl_renderbuffer
*rb
,
632 bool layered
, unsigned unit
,
635 struct gl_context
*ctx
= &brw
->ctx
;
636 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
637 struct intel_mipmap_tree
*mt
= irb
->mt
;
639 uint32_t tile_x
, tile_y
;
643 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
644 /* BRW_NEW_FS_PROG_DATA */
648 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
649 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
651 if (tile_x
!= 0 || tile_y
!= 0) {
652 /* Original gen4 hardware couldn't draw to a non-tile-aligned
653 * destination in a miptree unless you actually setup your renderbuffer
654 * as a miptree and used the fragile lod/array_index/etc. controls to
655 * select the image. So, instead, we just make a new single-level
656 * miptree and render into that.
658 intel_renderbuffer_move_to_temp(brw
, irb
, false);
663 intel_miptree_used_for_rendering(irb
->mt
);
665 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32, &offset
);
667 format
= brw
->render_target_format
[rb_format
];
668 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
669 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
670 __func__
, _mesa_get_format_name(rb_format
));
673 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
674 format
<< BRW_SURFACE_FORMAT_SHIFT
);
677 assert(mt
->offset
% mt
->cpp
== 0);
678 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
679 mt
->bo
->offset64
+ mt
->offset
);
681 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
682 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
684 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
685 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
687 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
689 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
690 /* Note that the low bits of these fields are missing, so
691 * there's the possibility of getting in trouble.
693 assert(tile_x
% 4 == 0);
694 assert(tile_y
% 2 == 0);
695 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
696 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
697 (mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
701 if (!ctx
->Color
.ColorLogicOpEnabled
&&
702 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
703 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
705 if (!ctx
->Color
.ColorMask
[unit
][0])
706 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
707 if (!ctx
->Color
.ColorMask
[unit
][1])
708 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
709 if (!ctx
->Color
.ColorMask
[unit
][2])
710 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
712 /* As mentioned above, disable writes to the alpha component when the
713 * renderbuffer is XRGB.
715 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
716 !ctx
->Color
.ColorMask
[unit
][3]) {
717 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
721 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
724 surf
[1] - mt
->bo
->offset64
,
725 I915_GEM_DOMAIN_RENDER
,
726 I915_GEM_DOMAIN_RENDER
);
732 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
735 brw_update_renderbuffer_surfaces(struct brw_context
*brw
,
736 const struct gl_framebuffer
*fb
,
737 uint32_t render_target_start
,
738 uint32_t *surf_offset
)
742 /* Update surfaces for drawing buffers */
743 if (fb
->_NumColorDrawBuffers
>= 1) {
744 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
745 const uint32_t surf_index
= render_target_start
+ i
;
747 if (intel_renderbuffer(fb
->_ColorDrawBuffers
[i
])) {
748 surf_offset
[surf_index
] =
749 brw
->vtbl
.update_renderbuffer_surface(
750 brw
, fb
->_ColorDrawBuffers
[i
],
751 fb
->MaxNumLayers
> 0, i
, surf_index
);
753 brw
->vtbl
.emit_null_surface_state(
754 brw
, fb
->Width
, fb
->Height
, fb
->Visual
.samples
,
755 &surf_offset
[surf_index
]);
759 const uint32_t surf_index
= render_target_start
;
760 brw
->vtbl
.emit_null_surface_state(
761 brw
, fb
->Width
, fb
->Height
, fb
->Visual
.samples
,
762 &surf_offset
[surf_index
]);
767 update_renderbuffer_surfaces(struct brw_context
*brw
)
769 const struct gl_context
*ctx
= &brw
->ctx
;
771 /* _NEW_BUFFERS | _NEW_COLOR */
772 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
773 brw_update_renderbuffer_surfaces(
775 brw
->wm
.prog_data
->binding_table
.render_target_start
,
776 brw
->wm
.base
.surf_offset
);
777 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
780 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
782 .mesa
= _NEW_BUFFERS
|
784 .brw
= BRW_NEW_BATCH
|
785 BRW_NEW_FS_PROG_DATA
,
787 .emit
= update_renderbuffer_surfaces
,
790 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
792 .mesa
= _NEW_BUFFERS
,
793 .brw
= BRW_NEW_BATCH
,
795 .emit
= update_renderbuffer_surfaces
,
800 update_stage_texture_surfaces(struct brw_context
*brw
,
801 const struct gl_program
*prog
,
802 struct brw_stage_state
*stage_state
,
808 struct gl_context
*ctx
= &brw
->ctx
;
810 uint32_t *surf_offset
= stage_state
->surf_offset
;
812 /* BRW_NEW_*_PROG_DATA */
814 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
816 surf_offset
+= stage_state
->prog_data
->binding_table
.texture_start
;
818 unsigned num_samplers
= _mesa_fls(prog
->SamplersUsed
);
819 for (unsigned s
= 0; s
< num_samplers
; s
++) {
822 if (prog
->SamplersUsed
& (1 << s
)) {
823 const unsigned unit
= prog
->SamplerUnits
[s
];
826 if (ctx
->Texture
.Unit
[unit
]._Current
) {
827 brw
->vtbl
.update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
);
835 * Construct SURFACE_STATE objects for enabled textures.
838 brw_update_texture_surfaces(struct brw_context
*brw
)
840 /* BRW_NEW_VERTEX_PROGRAM */
841 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
843 /* BRW_NEW_GEOMETRY_PROGRAM */
844 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
846 /* BRW_NEW_FRAGMENT_PROGRAM */
847 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
850 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false);
851 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false);
852 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false);
854 /* emit alternate set of surface state for gather. this
855 * allows the surface format to be overriden for only the
856 * gather4 messages. */
858 if (vs
&& vs
->UsesGather
)
859 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true);
860 if (gs
&& gs
->UsesGather
)
861 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true);
862 if (fs
&& fs
->UsesGather
)
863 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true);
866 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
869 const struct brw_tracked_state brw_texture_surfaces
= {
871 .mesa
= _NEW_TEXTURE
,
872 .brw
= BRW_NEW_BATCH
|
873 BRW_NEW_FRAGMENT_PROGRAM
|
874 BRW_NEW_FS_PROG_DATA
|
875 BRW_NEW_GEOMETRY_PROGRAM
|
876 BRW_NEW_GS_PROG_DATA
|
877 BRW_NEW_TEXTURE_BUFFER
|
878 BRW_NEW_VERTEX_PROGRAM
|
879 BRW_NEW_VS_PROG_DATA
,
881 .emit
= brw_update_texture_surfaces
,
885 brw_upload_ubo_surfaces(struct brw_context
*brw
,
886 struct gl_shader
*shader
,
887 struct brw_stage_state
*stage_state
,
888 struct brw_stage_prog_data
*prog_data
,
891 struct gl_context
*ctx
= &brw
->ctx
;
896 uint32_t *surf_offsets
=
897 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
899 for (int i
= 0; i
< shader
->NumUniformBlocks
; i
++) {
900 struct gl_uniform_buffer_binding
*binding
;
901 struct intel_buffer_object
*intel_bo
;
903 binding
= &ctx
->UniformBufferBindings
[shader
->UniformBlocks
[i
].Binding
];
904 intel_bo
= intel_buffer_object(binding
->BufferObject
);
906 intel_bufferobj_buffer(brw
, intel_bo
,
908 binding
->BufferObject
->Size
- binding
->Offset
);
910 /* Because behavior for referencing outside of the binding's size in the
911 * glBindBufferRange case is undefined, we can just bind the whole buffer
912 * glBindBufferBase wants and be a correct implementation.
914 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
915 bo
->size
- binding
->Offset
,
920 if (shader
->NumUniformBlocks
)
921 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
925 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
927 struct gl_context
*ctx
= &brw
->ctx
;
929 struct gl_shader_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
934 /* BRW_NEW_FS_PROG_DATA */
935 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
936 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
, true);
939 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
941 .mesa
= _NEW_PROGRAM
,
942 .brw
= BRW_NEW_BATCH
|
943 BRW_NEW_FS_PROG_DATA
|
944 BRW_NEW_UNIFORM_BUFFER
,
946 .emit
= brw_upload_wm_ubo_surfaces
,
950 brw_upload_abo_surfaces(struct brw_context
*brw
,
951 struct gl_shader_program
*prog
,
952 struct brw_stage_state
*stage_state
,
953 struct brw_stage_prog_data
*prog_data
)
955 struct gl_context
*ctx
= &brw
->ctx
;
956 uint32_t *surf_offsets
=
957 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
959 for (int i
= 0; i
< prog
->NumAtomicBuffers
; i
++) {
960 struct gl_atomic_buffer_binding
*binding
=
961 &ctx
->AtomicBufferBindings
[prog
->AtomicBuffers
[i
].Binding
];
962 struct intel_buffer_object
*intel_bo
=
963 intel_buffer_object(binding
->BufferObject
);
964 drm_intel_bo
*bo
= intel_bufferobj_buffer(
965 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
967 brw
->vtbl
.emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
968 binding
->Offset
, BRW_SURFACEFORMAT_RAW
,
969 bo
->size
- binding
->Offset
, 1, true);
972 if (prog
->NumAtomicBuffers
)
973 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
977 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
979 struct gl_context
*ctx
= &brw
->ctx
;
981 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
984 /* BRW_NEW_FS_PROG_DATA */
985 brw_upload_abo_surfaces(brw
, prog
, &brw
->wm
.base
,
986 &brw
->wm
.prog_data
->base
);
990 const struct brw_tracked_state brw_wm_abo_surfaces
= {
992 .mesa
= _NEW_PROGRAM
,
993 .brw
= BRW_NEW_ATOMIC_BUFFER
|
995 BRW_NEW_FS_PROG_DATA
,
997 .emit
= brw_upload_wm_abo_surfaces
,
1001 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1003 struct gl_context
*ctx
= &brw
->ctx
;
1005 struct gl_shader_program
*prog
=
1006 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1009 /* BRW_NEW_CS_PROG_DATA */
1010 brw_upload_abo_surfaces(brw
, prog
, &brw
->cs
.base
,
1011 &brw
->cs
.prog_data
->base
);
1015 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1017 .mesa
= _NEW_PROGRAM
,
1018 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1020 BRW_NEW_CS_PROG_DATA
,
1022 .emit
= brw_upload_cs_abo_surfaces
,
1026 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
1028 brw
->vtbl
.update_texture_surface
= brw_update_texture_surface
;
1029 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
1030 brw
->vtbl
.emit_null_surface_state
= brw_emit_null_surface_state
;
1031 brw
->vtbl
.emit_buffer_surface_state
= gen4_emit_buffer_surface_state
;