src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( gl_format mesa_format,
  73                                     GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_AL1616:
  90       return BRW_SURFACEFORMAT_L16A16_UNORM;
  91
  92    case MESA_FORMAT_RGB888:
  93       assert(0);                /* not supported for sampling */
  94       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  95
  96    case MESA_FORMAT_ARGB8888:
  97       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  98
  99    case MESA_FORMAT_XRGB8888:
 100       return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 101
 102    case MESA_FORMAT_RGBA8888_REV:
 103       _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
 104       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 105
 106    case MESA_FORMAT_RGB565:
 107       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 108
 109    case MESA_FORMAT_ARGB1555:
 110       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 111
 112    case MESA_FORMAT_ARGB4444:
 113       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 114
 115    case MESA_FORMAT_YCBCR_REV:
 116       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 117
 118    case MESA_FORMAT_YCBCR:
 119       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 120
 121    case MESA_FORMAT_RGB_FXT1:
 122    case MESA_FORMAT_RGBA_FXT1:
 123       return BRW_SURFACEFORMAT_FXT1;
 124
 125    case MESA_FORMAT_Z16:
 126       if (depth_mode == GL_INTENSITY)
 127           return BRW_SURFACEFORMAT_I16_UNORM;
 128       else if (depth_mode == GL_ALPHA)
 129           return BRW_SURFACEFORMAT_A16_UNORM;
 130       else
 131           return BRW_SURFACEFORMAT_L16_UNORM;
 132
 133    case MESA_FORMAT_RGB_DXT1:
 134        return BRW_SURFACEFORMAT_DXT1_RGB;
 135
 136    case MESA_FORMAT_RGBA_DXT1:
 137        return BRW_SURFACEFORMAT_BC1_UNORM;
 138
 139    case MESA_FORMAT_RGBA_DXT3:
 140        return BRW_SURFACEFORMAT_BC2_UNORM;
 141
 142    case MESA_FORMAT_RGBA_DXT5:
 143        return BRW_SURFACEFORMAT_BC3_UNORM;
 144
 145    case MESA_FORMAT_SARGB8:
 146       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 147
 148    case MESA_FORMAT_SLA8:
 149       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 150
 151    case MESA_FORMAT_SL8:
 152       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 153
 154    case MESA_FORMAT_SRGB_DXT1:
 155       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 156
 157    case MESA_FORMAT_S8_Z24:
 158       /* XXX: these different surface formats don't seem to
 159        * make any difference for shadow sampler/compares.
 160        */
 161       if (depth_mode == GL_INTENSITY)
 162          return BRW_SURFACEFORMAT_I24X8_UNORM;
 163       else if (depth_mode == GL_ALPHA)
 164          return BRW_SURFACEFORMAT_A24X8_UNORM;
 165       else
 166          return BRW_SURFACEFORMAT_L24X8_UNORM;
 167
 168    case MESA_FORMAT_DUDV8:
 169       return BRW_SURFACEFORMAT_R8G8_SNORM;
 170
 171    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 172       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 173
 174    default:
 175       assert(0);
 176       return 0;
 177    }
 178 }
 179
 180 static void
 181 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 182 {
 183    switch (tiling) {
 184    case I915_TILING_NONE:
 185       surf->ss3.tiled_surface = 0;
 186       surf->ss3.tile_walk = 0;
 187       break;
 188    case I915_TILING_X:
 189       surf->ss3.tiled_surface = 1;
 190       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 191       break;
 192    case I915_TILING_Y:
 193       surf->ss3.tiled_surface = 1;
 194       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 195       break;
 196    }
 197 }
 198
 199 static void
 200 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 201 {
 202    struct brw_context *brw = brw_context(ctx);
 203    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 204    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 205    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 206    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 207    struct brw_surface_state surf;
 208    void *map;
 209
 210    memset(&surf, 0, sizeof(surf));
 211
 212    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 213    surf.ss0.surface_type = translate_tex_target(tObj->Target);
 214    surf.ss0.surface_format = translate_tex_format(firstImage->TexFormat,
 215                                                   firstImage->InternalFormat,
 216                                                   tObj->DepthMode);
 217
 218    /* This is ok for all textures with channel width 8bit or less:
 219     */
 220 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 221    surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
 222
 223    surf.ss2.mip_count = intelObj->lastLevel - intelObj->firstLevel;
 224    surf.ss2.width = firstImage->Width - 1;
 225    surf.ss2.height = firstImage->Height - 1;
 226    brw_set_surface_tiling(&surf, intelObj->mt->region->tiling);
 227    surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 228    surf.ss3.depth = firstImage->Depth - 1;
 229
 230    surf.ss4.min_lod = 0;
 231
 232    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
 233       surf.ss0.cube_pos_x = 1;
 234       surf.ss0.cube_pos_y = 1;
 235       surf.ss0.cube_pos_z = 1;
 236       surf.ss0.cube_neg_x = 1;
 237       surf.ss0.cube_neg_y = 1;
 238       surf.ss0.cube_neg_z = 1;
 239    }
 240
 241    map = brw_state_batch(brw, sizeof(surf), 32,
 242                          &brw->wm.surf_bo[surf_index],
 243                          &brw->wm.surf_offset[surf_index]);
 244    memcpy(map, &surf, sizeof(surf));
 245
 246    /* Emit relocation to surface contents */
 247    drm_intel_bo_emit_reloc(brw->wm.surf_bo[surf_index],
 248                            brw->wm.surf_offset[surf_index] +
 249                            offsetof(struct brw_surface_state, ss1),
 250                            intelObj->mt->region->buffer, 0,
 251                            I915_GEM_DOMAIN_SAMPLER, 0);
 252 }
 253
 254 /**
 255  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 256  * read from this buffer with Data Port Read instructions/messages.
 257  */
 258 void
 259 brw_create_constant_surface(struct brw_context *brw,
 260                             drm_intel_bo *bo,
 261                             int width,
 262                             drm_intel_bo **out_bo,
 263                             uint32_t *out_offset)
 264 {
 265    const GLint w = width - 1;
 266    struct brw_surface_state surf;
 267    void *map;
 268
 269    memset(&surf, 0, sizeof(surf));
 270
 271    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 272    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 273    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 274
 275    assert(bo);
 276    surf.ss1.base_addr = bo->offset; /* reloc */
 277
 278    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 279    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 280    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 281    surf.ss3.pitch = (width * 16) - 1; /* ignored?? */
 282    brw_set_surface_tiling(&surf, I915_TILING_NONE); /* tiling now allowed */
 283
 284    map = brw_state_batch(brw, sizeof(surf), 32, out_bo, out_offset);
 285    memcpy(map, &surf, sizeof(surf));
 286
 287    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 288     * bspec ("Data Cache") says that the data cache does not exist as
 289     * a separate cache and is just the sampler cache.
 290     */
 291    drm_intel_bo_emit_reloc(*out_bo, (*out_offset +
 292                                      offsetof(struct brw_surface_state, ss1)),
 293                            bo, 0,
 294                            I915_GEM_DOMAIN_SAMPLER, 0);
 295 }
 296
 297 /* Creates a new WM constant buffer reflecting the current fragment program's
 298  * constants, if needed by the fragment program.
 299  *
 300  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 301  * state atom.
 302  */
 303 static void
 304 prepare_wm_constants(struct brw_context *brw)
 305 {
 306    GLcontext *ctx = &brw->intel.ctx;
 307    struct intel_context *intel = &brw->intel;
 308    struct brw_fragment_program *fp =
 309       (struct brw_fragment_program *) brw->fragment_program;
 310    const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 311    const int size = params->NumParameters * 4 * sizeof(GLfloat);
 312
 313    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 314
 315    /* BRW_NEW_FRAGMENT_PROGRAM */
 316    if (!fp->use_const_buffer) {
 317       if (brw->wm.const_bo) {
 318          drm_intel_bo_unreference(brw->wm.const_bo);
 319          brw->wm.const_bo = NULL;
 320          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 321       }
 322       return;
 323    }
 324
 325    drm_intel_bo_unreference(brw->wm.const_bo);
 326    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "vp_const_buffer",
 327                                          size, 64);
 328
 329    /* _NEW_PROGRAM_CONSTANTS */
 330    drm_intel_bo_subdata(brw->wm.const_bo, 0, size, params->ParameterValues);
 331 }
 332
 333 const struct brw_tracked_state brw_wm_constants = {
 334    .dirty = {
 335       .mesa = (_NEW_PROGRAM_CONSTANTS),
 336       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 337       .cache = 0
 338    },
 339    .prepare = prepare_wm_constants,
 340 };
 341
 342 /**
 343  * Updates surface / buffer for fragment shader constant buffer, if
 344  * one is required.
 345  *
 346  * This consumes the state updates for the constant buffer, and produces
 347  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 348  * inclusion in the binding table.
 349  */
 350 static void upload_wm_constant_surface(struct brw_context *brw )
 351 {
 352    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 353    struct brw_fragment_program *fp =
 354       (struct brw_fragment_program *) brw->fragment_program;
 355    const struct gl_program_parameter_list *params =
 356       fp->program.Base.Parameters;
 357
 358    /* If there's no constant buffer, then no surface BO is needed to point at
 359     * it.
 360     */
 361    if (brw->wm.const_bo == 0) {
 362       if (brw->wm.surf_bo[surf] != NULL) {
 363          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 364          brw->wm.surf_bo[surf] = NULL;
 365          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 366       }
 367       return;
 368    }
 369
 370    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 371                                &brw->wm.surf_bo[surf],
 372                                &brw->wm.surf_offset[surf]);
 373    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 374 }
 375
 376 const struct brw_tracked_state brw_wm_constant_surface = {
 377    .dirty = {
 378       .mesa = 0,
 379       .brw = (BRW_NEW_WM_CONSTBUF |
 380               BRW_NEW_BATCH),
 381       .cache = 0
 382    },
 383    .emit = upload_wm_constant_surface,
 384 };
 385
 386
 387 /**
 388  * Sets up a surface state structure to point at the given region.
 389  * While it is only used for the front/back buffer currently, it should be
 390  * usable for further buffers when doing ARB_draw_buffer support.
 391  */
 392 static void
 393 brw_update_renderbuffer_surface(struct brw_context *brw,
 394                                 struct gl_renderbuffer *rb,
 395                                 unsigned int unit)
 396 {
 397    struct intel_context *intel = &brw->intel;
 398    GLcontext *ctx = &intel->ctx;
 399    drm_intel_bo *region_bo = NULL;
 400    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 401    struct intel_region *region = irb ? irb->region : NULL;
 402    struct {
 403       unsigned int surface_type;
 404       unsigned int surface_format;
 405       unsigned int width, height, pitch, cpp;
 406       GLubyte color_mask[4];
 407       GLboolean color_blend;
 408       uint32_t tiling;
 409       uint32_t draw_x;
 410       uint32_t draw_y;
 411    } key;
 412    struct brw_surface_state surf;
 413    void *map;
 414
 415    memset(&key, 0, sizeof(key));
 416
 417    if (region != NULL) {
 418       region_bo = region->buffer;
 419
 420       key.surface_type = BRW_SURFACE_2D;
 421       switch (irb->Base.Format) {
 422       /* XRGB and ARGB are treated the same here because the chips in this
 423        * family cannot render to XRGB targets.  This means that we have to
 424        * mask writes to alpha (ala glColorMask) and reconfigure the alpha
 425        * blending hardware to use GL_ONE (or GL_ZERO) for cases where
 426        * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
 427        */
 428       case MESA_FORMAT_ARGB8888:
 429       case MESA_FORMAT_XRGB8888:
 430          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 431          break;
 432       case MESA_FORMAT_RGB565:
 433          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 434          break;
 435       case MESA_FORMAT_ARGB1555:
 436          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 437          break;
 438       case MESA_FORMAT_ARGB4444:
 439          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 440          break;
 441       case MESA_FORMAT_A8:
 442          key.surface_format = BRW_SURFACEFORMAT_A8_UNORM;
 443          break;
 444       default:
 445          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
 446       }
 447       key.tiling = region->tiling;
 448       key.width = rb->Width;
 449       key.height = rb->Height;
 450       key.pitch = region->pitch;
 451       key.cpp = region->cpp;
 452       key.draw_x = region->draw_x;
 453       key.draw_y = region->draw_y;
 454    } else {
 455       key.surface_type = BRW_SURFACE_NULL;
 456       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 457       key.tiling = I915_TILING_X;
 458       key.width = 1;
 459       key.height = 1;
 460       key.cpp = 4;
 461       key.draw_x = 0;
 462       key.draw_y = 0;
 463    }
 464
 465    if (intel->gen < 6) {
 466       /* _NEW_COLOR */
 467       memcpy(key.color_mask, ctx->Color.ColorMask[unit],
 468              sizeof(key.color_mask));
 469
 470       /* As mentioned above, disable writes to the alpha component when the
 471        * renderbuffer is XRGB.
 472        */
 473       if (ctx->DrawBuffer->Visual.alphaBits == 0)
 474          key.color_mask[3] = GL_FALSE;
 475
 476       key.color_blend = (!ctx->Color._LogicOpEnabled &&
 477                          (ctx->Color.BlendEnabled & (1 << unit)));
 478    }
 479
 480    memset(&surf, 0, sizeof(surf));
 481
 482    surf.ss0.surface_format = key.surface_format;
 483    surf.ss0.surface_type = key.surface_type;
 484    if (key.tiling == I915_TILING_NONE) {
 485       surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp;
 486    } else {
 487       uint32_t tile_base, tile_x, tile_y;
 488       uint32_t pitch = key.pitch * key.cpp;
 489
 490       if (key.tiling == I915_TILING_X) {
 491          tile_x = key.draw_x % (512 / key.cpp);
 492          tile_y = key.draw_y % 8;
 493          tile_base = ((key.draw_y / 8) * (8 * pitch));
 494          tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096;
 495       } else {
 496          /* Y */
 497          tile_x = key.draw_x % (128 / key.cpp);
 498          tile_y = key.draw_y % 32;
 499          tile_base = ((key.draw_y / 32) * (32 * pitch));
 500          tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
 501       }
 502       assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 503       assert(tile_x % 4 == 0);
 504       assert(tile_y % 2 == 0);
 505       /* Note that the low bits of these fields are missing, so
 506        * there's the possibility of getting in trouble.
 507        */
 508       surf.ss1.base_addr = tile_base;
 509       surf.ss5.x_offset = tile_x / 4;
 510       surf.ss5.y_offset = tile_y / 2;
 511    }
 512    if (region_bo != NULL)
 513       surf.ss1.base_addr += region_bo->offset; /* reloc */
 514
 515    surf.ss2.width = key.width - 1;
 516    surf.ss2.height = key.height - 1;
 517    brw_set_surface_tiling(&surf, key.tiling);
 518    surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 519
 520    if (intel->gen < 6) {
 521       /* _NEW_COLOR */
 522       surf.ss0.color_blend = key.color_blend;
 523       surf.ss0.writedisable_red =   !key.color_mask[0];
 524       surf.ss0.writedisable_green = !key.color_mask[1];
 525       surf.ss0.writedisable_blue =  !key.color_mask[2];
 526       surf.ss0.writedisable_alpha = !key.color_mask[3];
 527    }
 528
 529    map = brw_state_batch(brw, sizeof(surf), 32,
 530                          &brw->wm.surf_bo[unit],
 531                          &brw->wm.surf_offset[unit]);
 532    memcpy(map, &surf, sizeof(surf));
 533
 534    if (region_bo != NULL) {
 535       drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 536                               brw->wm.surf_offset[unit] +
 537                               offsetof(struct brw_surface_state, ss1),
 538                               region_bo,
 539                               surf.ss1.base_addr - region_bo->offset,
 540                               I915_GEM_DOMAIN_RENDER,
 541                               I915_GEM_DOMAIN_RENDER);
 542    }
 543 }
 544
 545 static void
 546 prepare_wm_surfaces(struct brw_context *brw)
 547 {
 548    GLcontext *ctx = &brw->intel.ctx;
 549    int i;
 550    int nr_surfaces = 0;
 551
 552    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 553       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 554          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 555          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 556          struct intel_region *region = irb ? irb->region : NULL;
 557
 558          brw_add_validated_bo(brw, region->buffer);
 559          nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 560       }
 561    }
 562
 563    if (brw->wm.const_bo) {
 564       brw_add_validated_bo(brw, brw->wm.const_bo);
 565       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 566    }
 567
 568    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 569       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 570       struct gl_texture_object *tObj = texUnit->_Current;
 571       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 572
 573       if (texUnit->_ReallyEnabled) {
 574          brw_add_validated_bo(brw, intelObj->mt->region->buffer);
 575          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 576       }
 577    }
 578
 579    /* Have to update this in our prepare, since the unit's prepare
 580     * relies on it.
 581     */
 582    if (brw->wm.nr_surfaces != nr_surfaces) {
 583       brw->wm.nr_surfaces = nr_surfaces;
 584       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 585    }
 586 }
 587
 588 /**
 589  * Constructs the set of surface state objects pointed to by the
 590  * binding table.
 591  */
 592 static void
 593 upload_wm_surfaces(struct brw_context *brw)
 594 {
 595    GLcontext *ctx = &brw->intel.ctx;
 596    GLuint i;
 597
 598    /* _NEW_BUFFERS | _NEW_COLOR */
 599    /* Update surfaces for drawing buffers */
 600    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 601       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 602          brw_update_renderbuffer_surface(brw,
 603                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 604                                          i);
 605       }
 606    } else {
 607       brw_update_renderbuffer_surface(brw, NULL, 0);
 608    }
 609
 610    /* Update surfaces for textures */
 611    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 612       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 613       const GLuint surf = SURF_INDEX_TEXTURE(i);
 614
 615       /* _NEW_TEXTURE */
 616       if (texUnit->_ReallyEnabled) {
 617          brw_update_texture_surface(ctx, i);
 618       } else {
 619          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 620          brw->wm.surf_bo[surf] = NULL;
 621       }
 622    }
 623
 624    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 625 }
 626
 627 const struct brw_tracked_state brw_wm_surfaces = {
 628    .dirty = {
 629       .mesa = (_NEW_COLOR |
 630                _NEW_TEXTURE |
 631                _NEW_BUFFERS),
 632       .brw = (BRW_NEW_BATCH),
 633       .cache = 0
 634    },
 635    .prepare = prepare_wm_surfaces,
 636    .emit = upload_wm_surfaces,
 637 };
 638
 639 /**
 640  * Constructs the binding table for the WM surface state, which maps unit
 641  * numbers to surface state objects.
 642  */
 643 static void
 644 brw_wm_upload_binding_table(struct brw_context *brw)
 645 {
 646    uint32_t *bind;
 647    int i;
 648
 649    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 650     * space for the binding table.
 651     */
 652    bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_WM_MAX_SURF,
 653                           32, &brw->wm.bind_bo, &brw->wm.bind_bo_offset);
 654
 655    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 656       /* BRW_NEW_WM_SURFACES */
 657       bind[i] = brw->wm.surf_offset[i];
 658       if (brw->wm.surf_bo[i]) {
 659          bind[i] = brw->wm.surf_offset[i];
 660       } else {
 661          bind[i] = 0;
 662       }
 663    }
 664
 665    brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;
 666 }
 667
 668 const struct brw_tracked_state brw_wm_binding_table = {
 669    .dirty = {
 670       .mesa = 0,
 671       .brw = (BRW_NEW_BATCH |
 672               BRW_NEW_WM_SURFACES),
 673       .cache = 0
 674    },
 675    .emit = brw_wm_upload_binding_table,
 676 };