2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
48 translate_tex_target(GLenum target
)
52 case GL_TEXTURE_1D_ARRAY_EXT
:
53 return BRW_SURFACE_1D
;
55 case GL_TEXTURE_RECTANGLE_NV
:
56 return BRW_SURFACE_2D
;
59 case GL_TEXTURE_2D_ARRAY_EXT
:
60 return BRW_SURFACE_2D
;
63 return BRW_SURFACE_3D
;
65 case GL_TEXTURE_CUBE_MAP
:
66 return BRW_SURFACE_CUBE
;
75 brw_format_for_mesa_format(gl_format mesa_format
)
77 static const uint32_t table
[MESA_FORMAT_COUNT
] =
79 [MESA_FORMAT_L8
] = BRW_SURFACEFORMAT_L8_UNORM
,
80 [MESA_FORMAT_I8
] = BRW_SURFACEFORMAT_I8_UNORM
,
81 [MESA_FORMAT_A8
] = BRW_SURFACEFORMAT_A8_UNORM
,
82 [MESA_FORMAT_AL88
] = BRW_SURFACEFORMAT_L8A8_UNORM
,
83 [MESA_FORMAT_AL1616
] = BRW_SURFACEFORMAT_L16A16_UNORM
,
84 [MESA_FORMAT_R8
] = BRW_SURFACEFORMAT_R8_UNORM
,
85 [MESA_FORMAT_R16
] = BRW_SURFACEFORMAT_R16_UNORM
,
86 [MESA_FORMAT_RG88
] = BRW_SURFACEFORMAT_R8G8_UNORM
,
87 [MESA_FORMAT_RG1616
] = BRW_SURFACEFORMAT_R16G16_UNORM
,
88 [MESA_FORMAT_ARGB8888
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM
,
89 [MESA_FORMAT_XRGB8888
] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM
,
90 [MESA_FORMAT_RGB565
] = BRW_SURFACEFORMAT_B5G6R5_UNORM
,
91 [MESA_FORMAT_ARGB1555
] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM
,
92 [MESA_FORMAT_ARGB4444
] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM
,
93 [MESA_FORMAT_YCBCR_REV
] = BRW_SURFACEFORMAT_YCRCB_NORMAL
,
94 [MESA_FORMAT_YCBCR
] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY
,
95 [MESA_FORMAT_RGB_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
96 [MESA_FORMAT_RGBA_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
97 [MESA_FORMAT_RGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB
,
98 [MESA_FORMAT_RGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM
,
99 [MESA_FORMAT_RGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM
,
100 [MESA_FORMAT_RGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM
,
101 [MESA_FORMAT_SRGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB
,
102 [MESA_FORMAT_SRGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB
,
103 [MESA_FORMAT_SRGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB
,
104 [MESA_FORMAT_SRGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB
,
105 [MESA_FORMAT_SARGB8
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
,
106 [MESA_FORMAT_SLA8
] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB
,
107 [MESA_FORMAT_SL8
] = BRW_SURFACEFORMAT_L8_UNORM_SRGB
,
108 [MESA_FORMAT_DUDV8
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
109 [MESA_FORMAT_SIGNED_R8
] = BRW_SURFACEFORMAT_R8_SNORM
,
110 [MESA_FORMAT_SIGNED_RG88_REV
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
111 [MESA_FORMAT_SIGNED_RGBA8888_REV
] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM
,
112 [MESA_FORMAT_SIGNED_R16
] = BRW_SURFACEFORMAT_R16_SNORM
,
113 [MESA_FORMAT_SIGNED_GR1616
] = BRW_SURFACEFORMAT_R16G16_SNORM
,
114 [MESA_FORMAT_RGBA_FLOAT32
] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
115 [MESA_FORMAT_RG_FLOAT32
] = BRW_SURFACEFORMAT_R32G32_FLOAT
,
116 [MESA_FORMAT_R_FLOAT32
] = BRW_SURFACEFORMAT_R32_FLOAT
,
117 [MESA_FORMAT_INTENSITY_FLOAT32
] = BRW_SURFACEFORMAT_I32_FLOAT
,
118 [MESA_FORMAT_LUMINANCE_FLOAT32
] = BRW_SURFACEFORMAT_L32_FLOAT
,
119 [MESA_FORMAT_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_A32_FLOAT
,
120 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_L32A32_FLOAT
,
121 [MESA_FORMAT_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_UNORM
,
122 [MESA_FORMAT_SIGNED_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_SNORM
,
123 [MESA_FORMAT_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_UNORM
,
124 [MESA_FORMAT_SIGNED_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_SNORM
,
125 [MESA_FORMAT_RGB9_E5_FLOAT
] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP
,
126 [MESA_FORMAT_R11_G11_B10_FLOAT
] = BRW_SURFACEFORMAT_R11G11B10_FLOAT
,
128 assert(mesa_format
< MESA_FORMAT_COUNT
);
129 return table
[mesa_format
];
133 brw_render_target_supported(gl_format format
)
135 /* These are not color render targets like the table holds, but we
136 * ask the question for FBO completeness.
138 if (format
== MESA_FORMAT_S8_Z24
||
139 format
== MESA_FORMAT_X8_Z24
||
140 format
== MESA_FORMAT_S8
||
141 format
== MESA_FORMAT_Z16
) {
145 /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
147 if (format
== MESA_FORMAT_RGBA_FLOAT32
)
150 /* Not exactly true, as some of those formats are not renderable.
151 * But at least we know how to translate them.
153 return brw_format_for_mesa_format(format
) != 0;
157 translate_tex_format(gl_format mesa_format
,
158 GLenum internal_format
,
162 switch( mesa_format
) {
164 case MESA_FORMAT_Z16
:
165 if (depth_mode
== GL_INTENSITY
)
166 return BRW_SURFACEFORMAT_I16_UNORM
;
167 else if (depth_mode
== GL_ALPHA
)
168 return BRW_SURFACEFORMAT_A16_UNORM
;
169 else if (depth_mode
== GL_RED
)
170 return BRW_SURFACEFORMAT_R16_UNORM
;
172 return BRW_SURFACEFORMAT_L16_UNORM
;
174 case MESA_FORMAT_S8_Z24
:
175 case MESA_FORMAT_X8_Z24
:
176 /* XXX: these different surface formats don't seem to
177 * make any difference for shadow sampler/compares.
179 if (depth_mode
== GL_INTENSITY
)
180 return BRW_SURFACEFORMAT_I24X8_UNORM
;
181 else if (depth_mode
== GL_ALPHA
)
182 return BRW_SURFACEFORMAT_A24X8_UNORM
;
183 else if (depth_mode
== GL_RED
)
184 return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
;
186 return BRW_SURFACEFORMAT_L24X8_UNORM
;
188 case MESA_FORMAT_SARGB8
:
189 case MESA_FORMAT_SLA8
:
190 case MESA_FORMAT_SL8
:
191 if (srgb_decode
== GL_DECODE_EXT
)
192 return brw_format_for_mesa_format(mesa_format
);
193 else if (srgb_decode
== GL_SKIP_DECODE_EXT
)
194 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format
));
196 case MESA_FORMAT_RGBA8888_REV
:
197 /* This format is not renderable? */
198 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
200 case MESA_FORMAT_RGBA_FLOAT32
:
201 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
204 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
207 assert(brw_format_for_mesa_format(mesa_format
) != 0);
208 return brw_format_for_mesa_format(mesa_format
);
213 brw_get_surface_tiling_bits(uint32_t tiling
)
217 return BRW_SURFACE_TILED
;
219 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
226 brw_update_texture_surface( struct gl_context
*ctx
, GLuint unit
)
228 struct brw_context
*brw
= brw_context(ctx
);
229 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
230 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
231 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
232 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
233 const GLuint surf_index
= SURF_INDEX_TEXTURE(unit
);
235 int width
, height
, depth
;
237 intel_miptree_get_dimensions_for_image(firstImage
, &width
, &height
, &depth
);
239 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
240 6 * 4, 32, &brw
->wm
.surf_offset
[surf_index
]);
242 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
243 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
244 BRW_SURFACE_CUBEFACE_ENABLES
|
245 (translate_tex_format(firstImage
->TexFormat
,
246 firstImage
->InternalFormat
,
248 sampler
->sRGBDecode
) <<
249 BRW_SURFACE_FORMAT_SHIFT
));
251 surf
[1] = intelObj
->mt
->region
->bo
->offset
; /* reloc */
253 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
254 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
255 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
257 surf
[3] = (brw_get_surface_tiling_bits(intelObj
->mt
->region
->tiling
) |
258 (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
259 ((intelObj
->mt
->region
->pitch
* intelObj
->mt
->cpp
) - 1) <<
260 BRW_SURFACE_PITCH_SHIFT
);
265 /* Emit relocation to surface contents */
266 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
267 brw
->wm
.surf_offset
[surf_index
] + 4,
268 intelObj
->mt
->region
->bo
, 0,
269 I915_GEM_DOMAIN_SAMPLER
, 0);
273 * Create the constant buffer surface. Vertex/fragment shader constants will be
274 * read from this buffer with Data Port Read instructions/messages.
277 brw_create_constant_surface(struct brw_context
*brw
,
280 uint32_t *out_offset
)
282 struct intel_context
*intel
= &brw
->intel
;
283 const GLint w
= width
- 1;
286 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
287 6 * 4, 32, out_offset
);
289 surf
[0] = (BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
290 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
291 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_SURFACE_FORMAT_SHIFT
);
294 surf
[0] |= BRW_SURFACE_RC_READ_WRITE
;
296 surf
[1] = bo
->offset
; /* reloc */
298 surf
[2] = (((w
& 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT
|
299 (((w
>> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT
);
301 surf
[3] = ((((w
>> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT
|
302 (width
* 16 - 1) << BRW_SURFACE_PITCH_SHIFT
);
307 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
308 * bspec ("Data Cache") says that the data cache does not exist as
309 * a separate cache and is just the sampler cache.
311 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
314 I915_GEM_DOMAIN_SAMPLER
, 0);
317 /* Creates a new WM constant buffer reflecting the current fragment program's
318 * constants, if needed by the fragment program.
320 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
324 prepare_wm_pull_constants(struct brw_context
*brw
)
326 struct gl_context
*ctx
= &brw
->intel
.ctx
;
327 struct intel_context
*intel
= &brw
->intel
;
328 struct brw_fragment_program
*fp
=
329 (struct brw_fragment_program
*) brw
->fragment_program
;
330 const int size
= brw
->wm
.prog_data
->nr_pull_params
* sizeof(float);
334 _mesa_load_state_parameters(ctx
, fp
->program
.Base
.Parameters
);
336 /* BRW_NEW_FRAGMENT_PROGRAM */
337 if (brw
->wm
.prog_data
->nr_pull_params
== 0) {
338 if (brw
->wm
.const_bo
) {
339 drm_intel_bo_unreference(brw
->wm
.const_bo
);
340 brw
->wm
.const_bo
= NULL
;
341 brw
->state
.dirty
.brw
|= BRW_NEW_WM_CONSTBUF
;
346 drm_intel_bo_unreference(brw
->wm
.const_bo
);
347 brw
->wm
.const_bo
= drm_intel_bo_alloc(intel
->bufmgr
, "WM const bo",
350 /* _NEW_PROGRAM_CONSTANTS */
351 drm_intel_gem_bo_map_gtt(brw
->wm
.const_bo
);
352 constants
= brw
->wm
.const_bo
->virtual;
353 for (i
= 0; i
< brw
->wm
.prog_data
->nr_pull_params
; i
++) {
354 constants
[i
] = convert_param(brw
->wm
.prog_data
->pull_param_convert
[i
],
355 brw
->wm
.prog_data
->pull_param
[i
]);
357 drm_intel_gem_bo_unmap_gtt(brw
->wm
.const_bo
);
359 brw
->state
.dirty
.brw
|= BRW_NEW_WM_CONSTBUF
;
362 const struct brw_tracked_state brw_wm_constants
= {
364 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
365 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
),
368 .prepare
= prepare_wm_pull_constants
,
372 * Updates surface / buffer for fragment shader constant buffer, if
375 * This consumes the state updates for the constant buffer, and produces
376 * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
377 * inclusion in the binding table.
379 static void upload_wm_constant_surface(struct brw_context
*brw
)
381 GLuint surf
= SURF_INDEX_FRAG_CONST_BUFFER
;
382 struct brw_fragment_program
*fp
=
383 (struct brw_fragment_program
*) brw
->fragment_program
;
384 const struct gl_program_parameter_list
*params
=
385 fp
->program
.Base
.Parameters
;
387 /* If there's no constant buffer, then no surface BO is needed to point at
390 if (brw
->wm
.const_bo
== 0) {
391 if (brw
->wm
.surf_offset
[surf
]) {
392 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
393 brw
->wm
.surf_offset
[surf
] = 0;
398 brw_create_constant_surface(brw
, brw
->wm
.const_bo
, params
->NumParameters
,
399 &brw
->wm
.surf_offset
[surf
]);
400 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
403 const struct brw_tracked_state brw_wm_constant_surface
= {
406 .brw
= (BRW_NEW_WM_CONSTBUF
|
410 .emit
= upload_wm_constant_surface
,
414 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
416 struct intel_context
*intel
= &brw
->intel
;
419 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
420 6 * 4, 32, &brw
->wm
.surf_offset
[unit
]);
422 surf
[0] = (BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
423 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
424 if (intel
->gen
< 6) {
425 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
426 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
427 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
428 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
438 * Sets up a surface state structure to point at the given region.
439 * While it is only used for the front/back buffer currently, it should be
440 * usable for further buffers when doing ARB_draw_buffer support.
443 brw_update_renderbuffer_surface(struct brw_context
*brw
,
444 struct gl_renderbuffer
*rb
,
447 struct intel_context
*intel
= &brw
->intel
;
448 struct gl_context
*ctx
= &intel
->ctx
;
449 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
450 struct intel_region
*region
= irb
->region
;
452 uint32_t tile_x
, tile_y
;
455 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
456 6 * 4, 32, &brw
->wm
.surf_offset
[unit
]);
458 switch (irb
->Base
.Format
) {
459 case MESA_FORMAT_XRGB8888
:
460 /* XRGB is handled as ARGB because the chips in this family
461 * cannot render to XRGB targets. This means that we have to
462 * mask writes to alpha (ala glColorMask) and reconfigure the
463 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
464 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
467 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
469 case MESA_FORMAT_INTENSITY_FLOAT32
:
470 case MESA_FORMAT_LUMINANCE_FLOAT32
:
471 /* For these formats, we just need to read/write the first
472 * channel into R, which is to say that we just treat them as
475 format
= BRW_SURFACEFORMAT_R32_FLOAT
;
477 case MESA_FORMAT_SARGB8
:
478 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
479 surfaces to the blend/update as sRGB */
480 if (ctx
->Color
.sRGBEnabled
)
481 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
483 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
486 assert(brw_render_target_supported(irb
->Base
.Format
));
487 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
490 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
491 format
<< BRW_SURFACE_FORMAT_SHIFT
);
494 surf
[1] = (intel_renderbuffer_tile_offsets(irb
, &tile_x
, &tile_y
) +
497 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
498 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
500 surf
[3] = (brw_get_surface_tiling_bits(region
->tiling
) |
501 ((region
->pitch
* region
->cpp
) - 1) << BRW_SURFACE_PITCH_SHIFT
);
505 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
506 /* Note that the low bits of these fields are missing, so
507 * there's the possibility of getting in trouble.
509 assert(tile_x
% 4 == 0);
510 assert(tile_y
% 2 == 0);
511 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
512 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
);
514 if (intel
->gen
< 6) {
516 if (!ctx
->Color
.ColorLogicOpEnabled
&&
517 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
518 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
520 if (!ctx
->Color
.ColorMask
[unit
][0])
521 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
522 if (!ctx
->Color
.ColorMask
[unit
][1])
523 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
524 if (!ctx
->Color
.ColorMask
[unit
][2])
525 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
527 /* As mentioned above, disable writes to the alpha component when the
528 * renderbuffer is XRGB.
530 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
531 !ctx
->Color
.ColorMask
[unit
][3]) {
532 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
536 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
537 brw
->wm
.surf_offset
[unit
] + 4,
539 surf
[1] - region
->bo
->offset
,
540 I915_GEM_DOMAIN_RENDER
,
541 I915_GEM_DOMAIN_RENDER
);
545 prepare_wm_surfaces(struct brw_context
*brw
)
547 struct gl_context
*ctx
= &brw
->intel
.ctx
;
551 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
552 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
553 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
554 struct intel_region
*region
= irb
? irb
->region
: NULL
;
557 brw_add_validated_bo(brw
, region
->bo
);
558 nr_surfaces
= SURF_INDEX_DRAW(i
) + 1;
561 if (brw
->wm
.const_bo
) {
562 brw_add_validated_bo(brw
, brw
->wm
.const_bo
);
563 nr_surfaces
= SURF_INDEX_FRAG_CONST_BUFFER
+ 1;
566 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
567 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
569 if (texUnit
->_ReallyEnabled
) {
570 struct gl_texture_object
*tObj
= texUnit
->_Current
;
571 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
573 brw_add_validated_bo(brw
, intelObj
->mt
->region
->bo
);
574 nr_surfaces
= SURF_INDEX_TEXTURE(i
) + 1;
578 /* Have to update this in our prepare, since the unit's prepare
581 if (brw
->wm
.nr_surfaces
!= nr_surfaces
) {
582 brw
->wm
.nr_surfaces
= nr_surfaces
;
583 brw
->state
.dirty
.brw
|= BRW_NEW_NR_WM_SURFACES
;
588 * Constructs the set of surface state objects pointed to by the
592 upload_wm_surfaces(struct brw_context
*brw
)
594 struct gl_context
*ctx
= &brw
->intel
.ctx
;
597 /* _NEW_BUFFERS | _NEW_COLOR */
598 /* Update surfaces for drawing buffers */
599 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
600 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
601 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
602 brw_update_renderbuffer_surface(brw
,
603 ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
606 brw_update_null_renderbuffer_surface(brw
, i
);
610 brw_update_null_renderbuffer_surface(brw
, 0);
613 /* Update surfaces for textures */
614 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
615 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
616 const GLuint surf
= SURF_INDEX_TEXTURE(i
);
619 if (texUnit
->_ReallyEnabled
) {
620 brw_update_texture_surface(ctx
, i
);
622 brw
->wm
.surf_offset
[surf
] = 0;
626 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
629 const struct brw_tracked_state brw_wm_surfaces
= {
631 .mesa
= (_NEW_COLOR
|
634 .brw
= (BRW_NEW_BATCH
),
637 .prepare
= prepare_wm_surfaces
,
638 .emit
= upload_wm_surfaces
,
642 * Constructs the binding table for the WM surface state, which maps unit
643 * numbers to surface state objects.
646 brw_wm_upload_binding_table(struct brw_context
*brw
)
651 /* Might want to calculate nr_surfaces first, to avoid taking up so much
652 * space for the binding table.
654 bind
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
655 sizeof(uint32_t) * BRW_WM_MAX_SURF
,
656 32, &brw
->wm
.bind_bo_offset
);
658 for (i
= 0; i
< BRW_WM_MAX_SURF
; i
++) {
659 /* BRW_NEW_WM_SURFACES */
660 bind
[i
] = brw
->wm
.surf_offset
[i
];
663 brw
->state
.dirty
.brw
|= BRW_NEW_PS_BINDING_TABLE
;
666 const struct brw_tracked_state brw_wm_binding_table
= {
669 .brw
= (BRW_NEW_BATCH
|
670 BRW_NEW_WM_SURFACES
),
673 .emit
= brw_wm_upload_binding_table
,