2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "compiler/nir/nir.h"
34 #include "main/context.h"
35 #include "main/blend.h"
36 #include "main/mtypes.h"
37 #include "main/samplerobj.h"
38 #include "main/shaderimage.h"
39 #include "main/teximage.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_instruction.h"
42 #include "main/framebuffer.h"
43 #include "main/shaderapi.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_batchbuffer.h"
49 #include "intel_tex.h"
50 #include "intel_fbo.h"
51 #include "intel_buffer_objects.h"
53 #include "brw_context.h"
54 #include "brw_state.h"
55 #include "brw_defines.h"
58 uint32_t wb_mocs
[] = {
65 uint32_t pte_mocs
[] = {
73 get_tex_mocs(const struct gen_device_info
*devinfo
, struct brw_bo
*bo
)
75 return (bo
&& bo
->external
? pte_mocs
: wb_mocs
)[devinfo
->gen
];
79 get_isl_surf(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
80 GLenum target
, struct isl_view
*view
,
81 uint32_t *tile_x
, uint32_t *tile_y
,
82 uint32_t *offset
, struct isl_surf
*surf
)
86 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
87 const enum isl_dim_layout dim_layout
=
88 get_isl_dim_layout(devinfo
, mt
->surf
.tiling
, target
);
90 if (surf
->dim_layout
== dim_layout
)
93 /* The layout of the specified texture target is not compatible with the
94 * actual layout of the miptree structure in memory -- You're entering
95 * dangerous territory, this can only possibly work if you only intended
96 * to access a single level and slice of the texture, and the hardware
97 * supports the tile offset feature in order to allow non-tile-aligned
98 * base offsets, since we'll have to point the hardware to the first
99 * texel of the level instead of relying on the usual base level/layer
102 assert(devinfo
->has_surface_tile_offset
);
103 assert(view
->levels
== 1 && view
->array_len
== 1);
104 assert(*tile_x
== 0 && *tile_y
== 0);
106 *offset
+= intel_miptree_get_tile_offsets(mt
, view
->base_level
,
107 view
->base_array_layer
,
110 /* Minify the logical dimensions of the texture. */
111 const unsigned l
= view
->base_level
- mt
->first_level
;
112 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
113 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
114 minify(surf
->logical_level0_px
.height
, l
);
115 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
116 minify(surf
->logical_level0_px
.depth
, l
);
118 /* Only the base level and layer can be addressed with the overridden
121 surf
->logical_level0_px
.array_len
= 1;
123 surf
->dim_layout
= dim_layout
;
125 /* The requested slice of the texture is now at the base level and
128 view
->base_level
= 0;
129 view
->base_array_layer
= 0;
133 brw_emit_surface_state(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*mt
,
135 GLenum target
, struct isl_view view
,
136 enum isl_aux_usage aux_usage
,
137 uint32_t mocs
, uint32_t *surf_offset
, int surf_index
,
138 unsigned reloc_flags
)
140 uint32_t tile_x
= mt
->level
[0].level_x
;
141 uint32_t tile_y
= mt
->level
[0].level_y
;
142 uint32_t offset
= mt
->offset
;
144 struct isl_surf surf
;
146 get_isl_surf(brw
, mt
, target
, &view
, &tile_x
, &tile_y
, &offset
, &surf
);
148 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
150 struct brw_bo
*aux_bo
;
151 struct isl_surf
*aux_surf
= NULL
;
152 uint64_t aux_offset
= 0;
154 case ISL_AUX_USAGE_MCS
:
155 case ISL_AUX_USAGE_CCS_D
:
156 case ISL_AUX_USAGE_CCS_E
:
157 aux_surf
= &mt
->mcs_buf
->surf
;
158 aux_bo
= mt
->mcs_buf
->bo
;
159 aux_offset
= mt
->mcs_buf
->offset
;
162 case ISL_AUX_USAGE_HIZ
:
163 aux_surf
= &mt
->hiz_buf
->surf
;
164 aux_bo
= mt
->hiz_buf
->bo
;
168 case ISL_AUX_USAGE_NONE
:
172 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
173 /* We only really need a clear color if we also have an auxiliary
174 * surface. Without one, it does nothing.
176 clear_color
= mt
->fast_clear_color
;
179 void *state
= brw_state_batch(brw
,
180 brw
->isl_dev
.ss
.size
,
181 brw
->isl_dev
.ss
.align
,
184 isl_surf_fill_state(&brw
->isl_dev
, state
, .surf
= &mt
->surf
, .view
= &view
,
185 .address
= brw_state_reloc(&brw
->batch
,
186 *surf_offset
+ brw
->isl_dev
.ss
.addr_offset
,
187 mt
->bo
, offset
, reloc_flags
),
188 .aux_surf
= aux_surf
, .aux_usage
= aux_usage
,
189 .aux_address
= aux_offset
,
190 .mocs
= mocs
, .clear_color
= clear_color
,
191 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
193 /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
194 * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
195 * contain other control information. Since buffer addresses are always
196 * on 4k boundaries (and thus have their lower 12 bits zero), we can use
197 * an ordinary reloc to do the necessary address translation.
199 * FIXME: move to the point of assignment.
201 assert((aux_offset
& 0xfff) == 0);
202 uint32_t *aux_addr
= state
+ brw
->isl_dev
.ss
.aux_addr_offset
;
203 *aux_addr
= brw_state_reloc(&brw
->batch
,
205 brw
->isl_dev
.ss
.aux_addr_offset
,
212 gen6_update_renderbuffer_surface(struct brw_context
*brw
,
213 struct gl_renderbuffer
*rb
,
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
218 struct gl_context
*ctx
= &brw
->ctx
;
219 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
220 struct intel_mipmap_tree
*mt
= irb
->mt
;
222 assert(brw_render_target_supported(brw
, rb
));
224 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
225 if (unlikely(!brw
->mesa_format_supports_render
[rb_format
])) {
226 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
227 __func__
, _mesa_get_format_name(rb_format
));
229 enum isl_format isl_format
= brw
->mesa_to_isl_render_format
[rb_format
];
231 enum isl_aux_usage aux_usage
=
232 brw
->draw_aux_buffer_disabled
[unit
] ? ISL_AUX_USAGE_NONE
:
233 intel_miptree_render_aux_usage(brw
, mt
, isl_format
,
234 ctx
->Color
.BlendEnabled
& (1 << unit
));
236 struct isl_view view
= {
237 .format
= isl_format
,
238 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
240 .base_array_layer
= irb
->mt_layer
,
241 .array_len
= MAX2(irb
->layer_count
, 1),
242 .swizzle
= ISL_SWIZZLE_IDENTITY
,
243 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
247 brw_emit_surface_state(brw
, mt
, mt
->target
, view
, aux_usage
,
248 pte_mocs
[devinfo
->gen
],
255 translate_tex_target(GLenum target
)
259 case GL_TEXTURE_1D_ARRAY_EXT
:
260 return BRW_SURFACE_1D
;
262 case GL_TEXTURE_RECTANGLE_NV
:
263 return BRW_SURFACE_2D
;
266 case GL_TEXTURE_2D_ARRAY_EXT
:
267 case GL_TEXTURE_EXTERNAL_OES
:
268 case GL_TEXTURE_2D_MULTISAMPLE
:
269 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
270 return BRW_SURFACE_2D
;
273 return BRW_SURFACE_3D
;
275 case GL_TEXTURE_CUBE_MAP
:
276 case GL_TEXTURE_CUBE_MAP_ARRAY
:
277 return BRW_SURFACE_CUBE
;
280 unreachable("not reached");
285 brw_get_surface_tiling_bits(enum isl_tiling tiling
)
289 return BRW_SURFACE_TILED
;
291 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
299 brw_get_surface_num_multisamples(unsigned num_samples
)
302 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
304 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
308 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
312 brw_get_texture_swizzle(const struct gl_context
*ctx
,
313 const struct gl_texture_object
*t
)
315 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
317 int swizzles
[SWIZZLE_NIL
+ 1] = {
327 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
328 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
329 GLenum depth_mode
= t
->DepthMode
;
331 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
332 * with depth component data specified with a sized internal format.
333 * Otherwise, it's left at the old default, GL_LUMINANCE.
335 if (_mesa_is_gles3(ctx
) &&
336 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
337 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
341 switch (depth_mode
) {
343 swizzles
[0] = SWIZZLE_ZERO
;
344 swizzles
[1] = SWIZZLE_ZERO
;
345 swizzles
[2] = SWIZZLE_ZERO
;
346 swizzles
[3] = SWIZZLE_X
;
349 swizzles
[0] = SWIZZLE_X
;
350 swizzles
[1] = SWIZZLE_X
;
351 swizzles
[2] = SWIZZLE_X
;
352 swizzles
[3] = SWIZZLE_ONE
;
355 swizzles
[0] = SWIZZLE_X
;
356 swizzles
[1] = SWIZZLE_X
;
357 swizzles
[2] = SWIZZLE_X
;
358 swizzles
[3] = SWIZZLE_X
;
361 swizzles
[0] = SWIZZLE_X
;
362 swizzles
[1] = SWIZZLE_ZERO
;
363 swizzles
[2] = SWIZZLE_ZERO
;
364 swizzles
[3] = SWIZZLE_ONE
;
369 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
371 /* If the texture's format is alpha-only, force R, G, and B to
372 * 0.0. Similarly, if the texture's format has no alpha channel,
373 * force the alpha value read to 1.0. This allows for the
374 * implementation to use an RGBA texture for any of these formats
375 * without leaking any unexpected values.
377 switch (img
->_BaseFormat
) {
379 swizzles
[0] = SWIZZLE_ZERO
;
380 swizzles
[1] = SWIZZLE_ZERO
;
381 swizzles
[2] = SWIZZLE_ZERO
;
384 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
385 swizzles
[0] = SWIZZLE_X
;
386 swizzles
[1] = SWIZZLE_X
;
387 swizzles
[2] = SWIZZLE_X
;
388 swizzles
[3] = SWIZZLE_ONE
;
391 case GL_LUMINANCE_ALPHA
:
392 if (datatype
== GL_SIGNED_NORMALIZED
) {
393 swizzles
[0] = SWIZZLE_X
;
394 swizzles
[1] = SWIZZLE_X
;
395 swizzles
[2] = SWIZZLE_X
;
396 swizzles
[3] = SWIZZLE_W
;
400 if (datatype
== GL_SIGNED_NORMALIZED
) {
401 swizzles
[0] = SWIZZLE_X
;
402 swizzles
[1] = SWIZZLE_X
;
403 swizzles
[2] = SWIZZLE_X
;
404 swizzles
[3] = SWIZZLE_X
;
410 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0 ||
411 img
->TexFormat
== MESA_FORMAT_RGB_DXT1
||
412 img
->TexFormat
== MESA_FORMAT_SRGB_DXT1
)
413 swizzles
[3] = SWIZZLE_ONE
;
417 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
418 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
419 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
420 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
424 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
425 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
427 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
430 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
432 * which is simply adding 4 then modding by 8 (or anding with 7).
434 * We then may need to apply workarounds for textureGather hardware bugs.
437 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
439 unsigned scs
= (swizzle
+ 4) & 7;
441 return (need_green_to_blue
&& scs
== HSW_SCS_GREEN
) ? HSW_SCS_BLUE
: scs
;
445 brw_aux_surface_disabled(const struct brw_context
*brw
,
446 const struct intel_mipmap_tree
*mt
)
448 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
450 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
451 const struct intel_renderbuffer
*irb
=
452 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
454 if (irb
&& irb
->mt
== mt
)
455 return brw
->draw_aux_buffer_disabled
[i
];
462 brw_update_texture_surface(struct gl_context
*ctx
,
464 uint32_t *surf_offset
,
469 struct brw_context
*brw
= brw_context(ctx
);
470 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
471 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
473 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
474 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
477 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
478 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
481 if (mt
->plane
[plane
- 1] == NULL
)
483 mt
= mt
->plane
[plane
- 1];
486 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
487 /* If this is a view with restricted NumLayers, then our effective depth
488 * is not just the miptree depth.
490 unsigned view_num_layers
;
491 if (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
) {
492 view_num_layers
= obj
->NumLayers
;
494 view_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
495 mt
->surf
.logical_level0_px
.depth
:
496 mt
->surf
.logical_level0_px
.array_len
;
499 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
500 * texturing functions that return a float, as our code generation always
501 * selects the .x channel (which would always be 0).
503 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
504 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
505 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
506 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
507 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
508 brw_get_texture_swizzle(&brw
->ctx
, obj
));
510 mesa_format mesa_fmt
= plane
== 0 ? intel_obj
->_Format
: mt
->format
;
511 enum isl_format format
= translate_tex_format(brw
, mesa_fmt
,
512 for_txf
? GL_DECODE_EXT
:
513 sampler
->sRGBDecode
);
515 /* Implement gen6 and gen7 gather work-around */
516 bool need_green_to_blue
= false;
518 if (devinfo
->gen
== 7 && (format
== ISL_FORMAT_R32G32_FLOAT
||
519 format
== ISL_FORMAT_R32G32_SINT
||
520 format
== ISL_FORMAT_R32G32_UINT
)) {
521 format
= ISL_FORMAT_R32G32_FLOAT_LD
;
522 need_green_to_blue
= devinfo
->is_haswell
;
523 } else if (devinfo
->gen
== 6) {
524 /* Sandybridge's gather4 message is broken for integer formats.
525 * To work around this, we pretend the surface is UNORM for
526 * 8 or 16-bit formats, and emit shader instructions to recover
527 * the real INT/UINT value. For 32-bit formats, we pretend
528 * the surface is FLOAT, and simply reinterpret the resulting
532 case ISL_FORMAT_R8_SINT
:
533 case ISL_FORMAT_R8_UINT
:
534 format
= ISL_FORMAT_R8_UNORM
;
537 case ISL_FORMAT_R16_SINT
:
538 case ISL_FORMAT_R16_UINT
:
539 format
= ISL_FORMAT_R16_UNORM
;
542 case ISL_FORMAT_R32_SINT
:
543 case ISL_FORMAT_R32_UINT
:
544 format
= ISL_FORMAT_R32_FLOAT
;
553 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
554 if (devinfo
->gen
<= 7) {
555 assert(mt
->r8stencil_mt
&& !mt
->stencil_mt
->r8stencil_needs_update
);
556 mt
= mt
->r8stencil_mt
;
560 format
= ISL_FORMAT_R8_UINT
;
561 } else if (devinfo
->gen
<= 7 && mt
->format
== MESA_FORMAT_S_UINT8
) {
562 assert(mt
->r8stencil_mt
&& !mt
->r8stencil_needs_update
);
563 mt
= mt
->r8stencil_mt
;
564 format
= ISL_FORMAT_R8_UINT
;
567 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
569 struct isl_view view
= {
571 .base_level
= obj
->MinLevel
+ obj
->BaseLevel
,
572 .levels
= intel_obj
->_MaxLevel
- obj
->BaseLevel
+ 1,
573 .base_array_layer
= obj
->MinLayer
,
574 .array_len
= view_num_layers
,
576 .r
= swizzle_to_scs(GET_SWZ(swizzle
, 0), need_green_to_blue
),
577 .g
= swizzle_to_scs(GET_SWZ(swizzle
, 1), need_green_to_blue
),
578 .b
= swizzle_to_scs(GET_SWZ(swizzle
, 2), need_green_to_blue
),
579 .a
= swizzle_to_scs(GET_SWZ(swizzle
, 3), need_green_to_blue
),
581 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
584 if (obj
->Target
== GL_TEXTURE_CUBE_MAP
||
585 obj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
586 view
.usage
|= ISL_SURF_USAGE_CUBE_BIT
;
588 enum isl_aux_usage aux_usage
=
589 intel_miptree_texture_aux_usage(brw
, mt
, format
);
591 if (brw_aux_surface_disabled(brw
, mt
))
592 aux_usage
= ISL_AUX_USAGE_NONE
;
594 brw_emit_surface_state(brw
, mt
, mt
->target
, view
, aux_usage
,
595 get_tex_mocs(devinfo
, mt
->bo
),
596 surf_offset
, surf_index
,
602 brw_emit_buffer_surface_state(struct brw_context
*brw
,
603 uint32_t *out_offset
,
605 unsigned buffer_offset
,
606 unsigned surface_format
,
607 unsigned buffer_size
,
609 unsigned reloc_flags
)
611 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
612 uint32_t *dw
= brw_state_batch(brw
,
613 brw
->isl_dev
.ss
.size
,
614 brw
->isl_dev
.ss
.align
,
617 isl_buffer_fill_state(&brw
->isl_dev
, dw
,
618 .address
= !bo
? buffer_offset
:
619 brw_state_reloc(&brw
->batch
,
620 *out_offset
+ brw
->isl_dev
.ss
.addr_offset
,
624 .format
= surface_format
,
626 .mocs
= get_tex_mocs(devinfo
, bo
));
630 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
632 uint32_t *surf_offset
)
634 struct brw_context
*brw
= brw_context(ctx
);
635 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
636 struct intel_buffer_object
*intel_obj
=
637 intel_buffer_object(tObj
->BufferObject
);
638 uint32_t size
= tObj
->BufferSize
;
639 struct brw_bo
*bo
= NULL
;
640 mesa_format format
= tObj
->_BufferObjectFormat
;
641 const enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
642 int texel_size
= _mesa_get_format_bytes(format
);
645 size
= MIN2(size
, intel_obj
->Base
.Size
);
646 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
,
650 /* The ARB_texture_buffer_specification says:
652 * "The number of texels in the buffer texture's texel array is given by
654 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
656 * where <buffer_size> is the size of the buffer object, in basic
657 * machine units and <components> and <base_type> are the element count
658 * and base data type for elements, as specified in Table X.1. The
659 * number of texels in the texel array is then clamped to the
660 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
662 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
663 * so that when ISL divides by stride to obtain the number of texels, that
664 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
666 size
= MIN2(size
, ctx
->Const
.MaxTextureBufferSize
* (unsigned) texel_size
);
668 if (isl_format
== ISL_FORMAT_UNSUPPORTED
) {
669 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
670 _mesa_get_format_name(format
));
673 brw_emit_buffer_surface_state(brw
, surf_offset
, bo
,
682 * Create the constant buffer surface. Vertex/fragment shader constants will be
683 * read from this buffer with Data Port Read instructions/messages.
686 brw_create_constant_surface(struct brw_context
*brw
,
690 uint32_t *out_offset
)
692 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
693 ISL_FORMAT_R32G32B32A32_FLOAT
,
698 * Create the buffer surface. Shader buffer variables will be
699 * read from / write to this buffer with Data Port Read/Write
700 * instructions/messages.
703 brw_create_buffer_surface(struct brw_context
*brw
,
707 uint32_t *out_offset
)
709 /* Use a raw surface so we can reuse existing untyped read/write/atomic
710 * messages. We need these specifically for the fragment shader since they
711 * include a pixel mask header that we need to ensure correct behavior
712 * with helper invocations, which cannot write to the buffer.
714 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
716 size
, 1, RELOC_WRITE
);
720 * Set up a binding table entry for use by stream output logic (transform
723 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
726 brw_update_sol_surface(struct brw_context
*brw
,
727 struct gl_buffer_object
*buffer_obj
,
728 uint32_t *out_offset
, unsigned num_vector_components
,
729 unsigned stride_dwords
, unsigned offset_dwords
)
731 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
732 uint32_t offset_bytes
= 4 * offset_dwords
;
733 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
735 buffer_obj
->Size
- offset_bytes
,
737 uint32_t *surf
= brw_state_batch(brw
, 6 * 4, 32, out_offset
);
738 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
739 size_t size_dwords
= buffer_obj
->Size
/ 4;
740 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
742 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
743 * too big to map using a single binding table entry?
745 assert((size_dwords
- offset_dwords
) / stride_dwords
746 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
748 if (size_dwords
> offset_dwords
+ num_vector_components
) {
749 /* There is room for at least 1 transform feedback output in the buffer.
750 * Compute the number of additional transform feedback outputs the
751 * buffer has room for.
753 buffer_size_minus_1
=
754 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
756 /* There isn't even room for a single transform feedback output in the
757 * buffer. We can't configure the binding table entry to prevent output
758 * entirely; we'll have to rely on the geometry shader to detect
759 * overflow. But to minimize the damage in case of a bug, set up the
760 * binding table entry to just allow a single output.
762 buffer_size_minus_1
= 0;
764 width
= buffer_size_minus_1
& 0x7f;
765 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
766 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
768 switch (num_vector_components
) {
770 surface_format
= ISL_FORMAT_R32_FLOAT
;
773 surface_format
= ISL_FORMAT_R32G32_FLOAT
;
776 surface_format
= ISL_FORMAT_R32G32B32_FLOAT
;
779 surface_format
= ISL_FORMAT_R32G32B32A32_FLOAT
;
782 unreachable("Invalid vector size for transform feedback output");
785 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
786 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
787 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
788 BRW_SURFACE_RC_READ_WRITE
;
789 surf
[1] = brw_state_reloc(&brw
->batch
,
790 *out_offset
+ 4, bo
, offset_bytes
, RELOC_WRITE
);
791 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
792 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
793 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
794 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
799 /* Creates a new WM constant buffer reflecting the current fragment program's
800 * constants, if needed by the fragment program.
802 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
806 brw_upload_wm_pull_constants(struct brw_context
*brw
)
808 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
809 /* BRW_NEW_FRAGMENT_PROGRAM */
810 struct brw_program
*fp
=
811 (struct brw_program
*) brw
->programs
[MESA_SHADER_FRAGMENT
];
813 /* BRW_NEW_FS_PROG_DATA */
814 struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
816 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
817 /* _NEW_PROGRAM_CONSTANTS */
818 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
,
819 stage_state
, prog_data
);
822 const struct brw_tracked_state brw_wm_pull_constants
= {
824 .mesa
= _NEW_PROGRAM_CONSTANTS
,
825 .brw
= BRW_NEW_BATCH
|
826 BRW_NEW_FRAGMENT_PROGRAM
|
827 BRW_NEW_FS_PROG_DATA
,
829 .emit
= brw_upload_wm_pull_constants
,
833 * Creates a null renderbuffer surface.
835 * This is used when the shader doesn't write to any color output. An FB
836 * write to target 0 will still be emitted, because that's how the thread is
837 * terminated (and computed depth is returned), so we need to have the
838 * hardware discard the target 0 color output..
841 emit_null_surface_state(struct brw_context
*brw
,
842 const struct gl_framebuffer
*fb
,
843 uint32_t *out_offset
)
845 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
846 uint32_t *surf
= brw_state_batch(brw
,
847 brw
->isl_dev
.ss
.size
,
848 brw
->isl_dev
.ss
.align
,
851 /* Use the fb dimensions or 1x1x1 */
852 const unsigned width
= fb
? _mesa_geometric_width(fb
) : 1;
853 const unsigned height
= fb
? _mesa_geometric_height(fb
) : 1;
854 const unsigned samples
= fb
? _mesa_geometric_samples(fb
) : 1;
856 if (devinfo
->gen
!= 6 || samples
<= 1) {
857 isl_null_fill_state(&brw
->isl_dev
, surf
,
858 isl_extent3d(width
, height
, 1));
862 /* On Gen6, null render targets seem to cause GPU hangs when multisampling.
863 * So work around this problem by rendering into dummy color buffer.
865 * To decrease the amount of memory needed by the workaround buffer, we
866 * set its pitch to 128 bytes (the width of a Y tile). This means that
867 * the amount of memory needed for the workaround buffer is
868 * (width_in_tiles + height_in_tiles - 1) tiles.
870 * Note that since the workaround buffer will be interpreted by the
871 * hardware as an interleaved multisampled buffer, we need to compute
872 * width_in_tiles and height_in_tiles by dividing the width and height
873 * by 16 rather than the normal Y-tile size of 32.
875 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
876 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
877 unsigned pitch_minus_1
= 127;
878 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
879 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
882 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
883 ISL_FORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
884 surf
[1] = brw_state_reloc(&brw
->batch
, *out_offset
+ 4,
885 brw
->wm
.multisampled_null_render_target_bo
,
888 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
889 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
891 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
894 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
896 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
897 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
898 surf
[4] = BRW_SURFACE_MULTISAMPLECOUNT_4
;
903 * Sets up a surface state structure to point at the given region.
904 * While it is only used for the front/back buffer currently, it should be
905 * usable for further buffers when doing ARB_draw_buffer support.
908 gen4_update_renderbuffer_surface(struct brw_context
*brw
,
909 struct gl_renderbuffer
*rb
,
913 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
914 struct gl_context
*ctx
= &brw
->ctx
;
915 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
916 struct intel_mipmap_tree
*mt
= irb
->mt
;
918 uint32_t tile_x
, tile_y
;
919 enum isl_format format
;
922 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
923 /* BRW_NEW_FS_PROG_DATA */
925 if (rb
->TexImage
&& !devinfo
->has_surface_tile_offset
) {
926 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
928 if (tile_x
!= 0 || tile_y
!= 0) {
929 /* Original gen4 hardware couldn't draw to a non-tile-aligned
930 * destination in a miptree unless you actually setup your renderbuffer
931 * as a miptree and used the fragile lod/array_index/etc. controls to
932 * select the image. So, instead, we just make a new single-level
933 * miptree and render into that.
935 intel_renderbuffer_move_to_temp(brw
, irb
, false);
936 assert(irb
->align_wa_mt
);
937 mt
= irb
->align_wa_mt
;
941 surf
= brw_state_batch(brw
, 6 * 4, 32, &offset
);
943 format
= brw
->mesa_to_isl_render_format
[rb_format
];
944 if (unlikely(!brw
->mesa_format_supports_render
[rb_format
])) {
945 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
946 __func__
, _mesa_get_format_name(rb_format
));
949 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
950 format
<< BRW_SURFACE_FORMAT_SHIFT
);
953 assert(mt
->offset
% mt
->cpp
== 0);
954 surf
[1] = brw_state_reloc(&brw
->batch
, offset
+ 4, mt
->bo
,
956 intel_renderbuffer_get_tile_offsets(irb
,
961 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
962 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
964 surf
[3] = (brw_get_surface_tiling_bits(mt
->surf
.tiling
) |
965 (mt
->surf
.row_pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
967 surf
[4] = brw_get_surface_num_multisamples(mt
->surf
.samples
);
969 assert(devinfo
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
970 /* Note that the low bits of these fields are missing, so
971 * there's the possibility of getting in trouble.
973 assert(tile_x
% 4 == 0);
974 assert(tile_y
% 2 == 0);
975 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
976 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
977 (mt
->surf
.image_alignment_el
.height
== 4 ?
978 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
980 if (devinfo
->gen
< 6) {
982 if (!ctx
->Color
.ColorLogicOpEnabled
&& !ctx
->Color
._AdvancedBlendMode
&&
983 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
984 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
986 if (!ctx
->Color
.ColorMask
[unit
][0])
987 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
988 if (!ctx
->Color
.ColorMask
[unit
][1])
989 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
990 if (!ctx
->Color
.ColorMask
[unit
][2])
991 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
993 /* As mentioned above, disable writes to the alpha component when the
994 * renderbuffer is XRGB.
996 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
997 !ctx
->Color
.ColorMask
[unit
][3]) {
998 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
1006 update_renderbuffer_surfaces(struct brw_context
*brw
)
1008 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1009 const struct gl_context
*ctx
= &brw
->ctx
;
1011 /* _NEW_BUFFERS | _NEW_COLOR */
1012 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1014 /* Render targets always start at binding table index 0. */
1015 const unsigned rt_start
= 0;
1017 uint32_t *surf_offsets
= brw
->wm
.base
.surf_offset
;
1019 /* Update surfaces for drawing buffers */
1020 if (fb
->_NumColorDrawBuffers
>= 1) {
1021 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1022 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[i
];
1024 if (intel_renderbuffer(rb
)) {
1025 surf_offsets
[rt_start
+ i
] = devinfo
->gen
>= 6 ?
1026 gen6_update_renderbuffer_surface(brw
, rb
, i
, rt_start
+ i
) :
1027 gen4_update_renderbuffer_surface(brw
, rb
, i
, rt_start
+ i
);
1029 emit_null_surface_state(brw
, fb
, &surf_offsets
[rt_start
+ i
]);
1033 emit_null_surface_state(brw
, fb
, &surf_offsets
[rt_start
]);
1036 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1039 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
1041 .mesa
= _NEW_BUFFERS
|
1043 .brw
= BRW_NEW_BATCH
,
1045 .emit
= update_renderbuffer_surfaces
,
1048 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
1050 .mesa
= _NEW_BUFFERS
,
1051 .brw
= BRW_NEW_BATCH
|
1054 .emit
= update_renderbuffer_surfaces
,
1058 update_renderbuffer_read_surfaces(struct brw_context
*brw
)
1060 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1061 const struct gl_context
*ctx
= &brw
->ctx
;
1063 /* BRW_NEW_FS_PROG_DATA */
1064 const struct brw_wm_prog_data
*wm_prog_data
=
1065 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1067 if (wm_prog_data
->has_render_target_reads
&&
1068 !ctx
->Extensions
.MESA_shader_framebuffer_fetch
) {
1070 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1072 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1073 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[i
];
1074 const struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1075 const unsigned surf_index
=
1076 wm_prog_data
->binding_table
.render_target_read_start
+ i
;
1077 uint32_t *surf_offset
= &brw
->wm
.base
.surf_offset
[surf_index
];
1080 const enum isl_format format
= brw
->mesa_to_isl_render_format
[
1081 _mesa_get_render_format(ctx
, intel_rb_format(irb
))];
1082 assert(isl_format_supports_sampling(&brw
->screen
->devinfo
,
1085 /* Override the target of the texture if the render buffer is a
1086 * single slice of a 3D texture (since the minimum array element
1087 * field of the surface state structure is ignored by the sampler
1088 * unit for 3D textures on some hardware), or if the render buffer
1089 * is a 1D array (since shaders always provide the array index
1090 * coordinate at the Z component to avoid state-dependent
1091 * recompiles when changing the texture target of the
1094 const GLenum target
=
1095 (irb
->mt
->target
== GL_TEXTURE_3D
&&
1096 irb
->layer_count
== 1) ? GL_TEXTURE_2D
:
1097 irb
->mt
->target
== GL_TEXTURE_1D_ARRAY
? GL_TEXTURE_2D_ARRAY
:
1100 const struct isl_view view
= {
1102 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
1104 .base_array_layer
= irb
->mt_layer
,
1105 .array_len
= irb
->layer_count
,
1106 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1107 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
1110 enum isl_aux_usage aux_usage
=
1111 intel_miptree_texture_aux_usage(brw
, irb
->mt
, format
);
1112 if (brw
->draw_aux_buffer_disabled
[i
])
1113 aux_usage
= ISL_AUX_USAGE_NONE
;
1115 brw_emit_surface_state(brw
, irb
->mt
, target
, view
, aux_usage
,
1116 get_tex_mocs(devinfo
, irb
->mt
->bo
),
1117 surf_offset
, surf_index
,
1121 emit_null_surface_state(brw
, fb
, surf_offset
);
1125 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1129 const struct brw_tracked_state brw_renderbuffer_read_surfaces
= {
1131 .mesa
= _NEW_BUFFERS
,
1132 .brw
= BRW_NEW_BATCH
|
1134 BRW_NEW_FS_PROG_DATA
,
1136 .emit
= update_renderbuffer_read_surfaces
,
1140 update_stage_texture_surfaces(struct brw_context
*brw
,
1141 const struct gl_program
*prog
,
1142 struct brw_stage_state
*stage_state
,
1143 bool for_gather
, uint32_t plane
)
1148 struct gl_context
*ctx
= &brw
->ctx
;
1150 uint32_t *surf_offset
= stage_state
->surf_offset
;
1152 /* BRW_NEW_*_PROG_DATA */
1154 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
1156 surf_offset
+= stage_state
->prog_data
->binding_table
.plane_start
[plane
];
1158 unsigned num_samplers
= util_last_bit(prog
->SamplersUsed
);
1159 for (unsigned s
= 0; s
< num_samplers
; s
++) {
1162 if (prog
->SamplersUsed
& (1 << s
)) {
1163 const unsigned unit
= prog
->SamplerUnits
[s
];
1164 const bool used_by_txf
= prog
->info
.textures_used_by_txf
& (1 << s
);
1167 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1168 brw_update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
,
1169 used_by_txf
, plane
);
1177 * Construct SURFACE_STATE objects for enabled textures.
1180 brw_update_texture_surfaces(struct brw_context
*brw
)
1182 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1184 /* BRW_NEW_VERTEX_PROGRAM */
1185 struct gl_program
*vs
= brw
->programs
[MESA_SHADER_VERTEX
];
1187 /* BRW_NEW_TESS_PROGRAMS */
1188 struct gl_program
*tcs
= brw
->programs
[MESA_SHADER_TESS_CTRL
];
1189 struct gl_program
*tes
= brw
->programs
[MESA_SHADER_TESS_EVAL
];
1191 /* BRW_NEW_GEOMETRY_PROGRAM */
1192 struct gl_program
*gs
= brw
->programs
[MESA_SHADER_GEOMETRY
];
1194 /* BRW_NEW_FRAGMENT_PROGRAM */
1195 struct gl_program
*fs
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1198 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false, 0);
1199 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, false, 0);
1200 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, false, 0);
1201 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false, 0);
1202 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 0);
1204 /* emit alternate set of surface state for gather. this
1205 * allows the surface format to be overriden for only the
1206 * gather4 messages. */
1207 if (devinfo
->gen
< 8) {
1208 if (vs
&& vs
->info
.uses_texture_gather
)
1209 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true, 0);
1210 if (tcs
&& tcs
->info
.uses_texture_gather
)
1211 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, true, 0);
1212 if (tes
&& tes
->info
.uses_texture_gather
)
1213 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, true, 0);
1214 if (gs
&& gs
->info
.uses_texture_gather
)
1215 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true, 0);
1216 if (fs
&& fs
->info
.uses_texture_gather
)
1217 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true, 0);
1221 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 1);
1222 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 2);
1225 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1228 const struct brw_tracked_state brw_texture_surfaces
= {
1230 .mesa
= _NEW_TEXTURE
,
1231 .brw
= BRW_NEW_BATCH
|
1233 BRW_NEW_FRAGMENT_PROGRAM
|
1234 BRW_NEW_FS_PROG_DATA
|
1235 BRW_NEW_GEOMETRY_PROGRAM
|
1236 BRW_NEW_GS_PROG_DATA
|
1237 BRW_NEW_TESS_PROGRAMS
|
1238 BRW_NEW_TCS_PROG_DATA
|
1239 BRW_NEW_TES_PROG_DATA
|
1240 BRW_NEW_TEXTURE_BUFFER
|
1241 BRW_NEW_VERTEX_PROGRAM
|
1242 BRW_NEW_VS_PROG_DATA
,
1244 .emit
= brw_update_texture_surfaces
,
1248 brw_update_cs_texture_surfaces(struct brw_context
*brw
)
1250 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1252 /* BRW_NEW_COMPUTE_PROGRAM */
1253 struct gl_program
*cs
= brw
->programs
[MESA_SHADER_COMPUTE
];
1256 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, false, 0);
1258 /* emit alternate set of surface state for gather. this
1259 * allows the surface format to be overriden for only the
1262 if (devinfo
->gen
< 8) {
1263 if (cs
&& cs
->info
.uses_texture_gather
)
1264 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, true, 0);
1267 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1270 const struct brw_tracked_state brw_cs_texture_surfaces
= {
1272 .mesa
= _NEW_TEXTURE
,
1273 .brw
= BRW_NEW_BATCH
|
1274 BRW_NEW_COMPUTE_PROGRAM
|
1277 .emit
= brw_update_cs_texture_surfaces
,
1282 brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1283 struct brw_stage_state
*stage_state
,
1284 struct brw_stage_prog_data
*prog_data
)
1286 struct gl_context
*ctx
= &brw
->ctx
;
1291 uint32_t *ubo_surf_offsets
=
1292 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
1294 for (int i
= 0; i
< prog
->info
.num_ubos
; i
++) {
1295 struct gl_buffer_binding
*binding
=
1296 &ctx
->UniformBufferBindings
[prog
->sh
.UniformBlocks
[i
]->Binding
];
1298 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1299 emit_null_surface_state(brw
, NULL
, &ubo_surf_offsets
[i
]);
1301 struct intel_buffer_object
*intel_bo
=
1302 intel_buffer_object(binding
->BufferObject
);
1303 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1304 if (!binding
->AutomaticSize
)
1305 size
= MIN2(size
, binding
->Size
);
1307 intel_bufferobj_buffer(brw
, intel_bo
,
1310 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
1312 &ubo_surf_offsets
[i
]);
1316 uint32_t *ssbo_surf_offsets
=
1317 &stage_state
->surf_offset
[prog_data
->binding_table
.ssbo_start
];
1319 for (int i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
1320 struct gl_buffer_binding
*binding
=
1321 &ctx
->ShaderStorageBufferBindings
[prog
->sh
.ShaderStorageBlocks
[i
]->Binding
];
1323 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1324 emit_null_surface_state(brw
, NULL
, &ssbo_surf_offsets
[i
]);
1326 struct intel_buffer_object
*intel_bo
=
1327 intel_buffer_object(binding
->BufferObject
);
1328 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1329 if (!binding
->AutomaticSize
)
1330 size
= MIN2(size
, binding
->Size
);
1332 intel_bufferobj_buffer(brw
, intel_bo
,
1335 brw_create_buffer_surface(brw
, bo
, binding
->Offset
,
1337 &ssbo_surf_offsets
[i
]);
1341 stage_state
->push_constants_dirty
= true;
1343 if (prog
->info
.num_ubos
|| prog
->info
.num_ssbos
)
1344 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1348 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
1350 struct gl_context
*ctx
= &brw
->ctx
;
1352 struct gl_program
*prog
= ctx
->FragmentProgram
._Current
;
1354 /* BRW_NEW_FS_PROG_DATA */
1355 brw_upload_ubo_surfaces(brw
, prog
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1358 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
1360 .mesa
= _NEW_PROGRAM
,
1361 .brw
= BRW_NEW_BATCH
|
1362 BRW_NEW_FS_PROG_DATA
|
1363 BRW_NEW_UNIFORM_BUFFER
,
1365 .emit
= brw_upload_wm_ubo_surfaces
,
1369 brw_upload_cs_ubo_surfaces(struct brw_context
*brw
)
1371 struct gl_context
*ctx
= &brw
->ctx
;
1373 struct gl_program
*prog
=
1374 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1376 /* BRW_NEW_CS_PROG_DATA */
1377 brw_upload_ubo_surfaces(brw
, prog
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1380 const struct brw_tracked_state brw_cs_ubo_surfaces
= {
1382 .mesa
= _NEW_PROGRAM
,
1383 .brw
= BRW_NEW_BATCH
|
1384 BRW_NEW_CS_PROG_DATA
|
1385 BRW_NEW_UNIFORM_BUFFER
,
1387 .emit
= brw_upload_cs_ubo_surfaces
,
1391 brw_upload_abo_surfaces(struct brw_context
*brw
,
1392 const struct gl_program
*prog
,
1393 struct brw_stage_state
*stage_state
,
1394 struct brw_stage_prog_data
*prog_data
)
1396 struct gl_context
*ctx
= &brw
->ctx
;
1397 uint32_t *surf_offsets
=
1398 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
1400 if (prog
->info
.num_abos
) {
1401 for (unsigned i
= 0; i
< prog
->info
.num_abos
; i
++) {
1402 struct gl_buffer_binding
*binding
=
1403 &ctx
->AtomicBufferBindings
[prog
->sh
.AtomicBuffers
[i
]->Binding
];
1404 struct intel_buffer_object
*intel_bo
=
1405 intel_buffer_object(binding
->BufferObject
);
1407 intel_bufferobj_buffer(brw
, intel_bo
, binding
->Offset
,
1408 intel_bo
->Base
.Size
- binding
->Offset
,
1411 brw_emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
1412 binding
->Offset
, ISL_FORMAT_RAW
,
1413 bo
->size
- binding
->Offset
, 1,
1417 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1422 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
1425 const struct gl_program
*wm
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1428 /* BRW_NEW_FS_PROG_DATA */
1429 brw_upload_abo_surfaces(brw
, wm
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1433 const struct brw_tracked_state brw_wm_abo_surfaces
= {
1435 .mesa
= _NEW_PROGRAM
,
1436 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1438 BRW_NEW_FS_PROG_DATA
,
1440 .emit
= brw_upload_wm_abo_surfaces
,
1444 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1447 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
1450 /* BRW_NEW_CS_PROG_DATA */
1451 brw_upload_abo_surfaces(brw
, cp
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1455 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1457 .mesa
= _NEW_PROGRAM
,
1458 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1460 BRW_NEW_CS_PROG_DATA
,
1462 .emit
= brw_upload_cs_abo_surfaces
,
1466 brw_upload_cs_image_surfaces(struct brw_context
*brw
)
1469 const struct gl_program
*cp
= brw
->programs
[MESA_SHADER_COMPUTE
];
1472 /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1473 brw_upload_image_surfaces(brw
, cp
, &brw
->cs
.base
,
1474 brw
->cs
.base
.prog_data
);
1478 const struct brw_tracked_state brw_cs_image_surfaces
= {
1480 .mesa
= _NEW_TEXTURE
| _NEW_PROGRAM
,
1481 .brw
= BRW_NEW_BATCH
|
1482 BRW_NEW_CS_PROG_DATA
|
1486 .emit
= brw_upload_cs_image_surfaces
,
1490 get_image_format(struct brw_context
*brw
, mesa_format format
, GLenum access
)
1492 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1493 enum isl_format hw_format
= brw_isl_format_for_mesa_format(format
);
1494 if (access
== GL_WRITE_ONLY
) {
1496 } else if (isl_has_matching_typed_storage_image_format(devinfo
, hw_format
)) {
1497 /* Typed surface reads support a very limited subset of the shader
1498 * image formats. Translate it into the closest format the
1499 * hardware supports.
1501 return isl_lower_storage_image_format(devinfo
, hw_format
);
1503 /* The hardware doesn't actually support a typed format that we can use
1504 * so we have to fall back to untyped read/write messages.
1506 return ISL_FORMAT_RAW
;
1511 update_default_image_param(struct brw_context
*brw
,
1512 struct gl_image_unit
*u
,
1513 unsigned surface_idx
,
1514 struct brw_image_param
*param
)
1516 memset(param
, 0, sizeof(*param
));
1517 param
->surface_idx
= surface_idx
;
1518 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1519 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1520 * detailed explanation of these parameters.
1522 param
->swizzling
[0] = 0xff;
1523 param
->swizzling
[1] = 0xff;
1527 update_buffer_image_param(struct brw_context
*brw
,
1528 struct gl_image_unit
*u
,
1529 unsigned surface_idx
,
1530 struct brw_image_param
*param
)
1532 struct gl_buffer_object
*obj
= u
->TexObj
->BufferObject
;
1533 const uint32_t size
= MIN2((uint32_t)u
->TexObj
->BufferSize
, obj
->Size
);
1534 update_default_image_param(brw
, u
, surface_idx
, param
);
1536 param
->size
[0] = size
/ _mesa_get_format_bytes(u
->_ActualFormat
);
1537 param
->stride
[0] = _mesa_get_format_bytes(u
->_ActualFormat
);
1541 get_image_num_layers(const struct intel_mipmap_tree
*mt
, GLenum target
,
1544 if (target
== GL_TEXTURE_CUBE_MAP
)
1547 return target
== GL_TEXTURE_3D
?
1548 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1549 mt
->surf
.logical_level0_px
.array_len
;
1553 update_image_surface(struct brw_context
*brw
,
1554 struct gl_image_unit
*u
,
1556 unsigned surface_idx
,
1557 uint32_t *surf_offset
,
1558 struct brw_image_param
*param
)
1560 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1562 if (_mesa_is_image_unit_valid(&brw
->ctx
, u
)) {
1563 struct gl_texture_object
*obj
= u
->TexObj
;
1564 const unsigned format
= get_image_format(brw
, u
->_ActualFormat
, access
);
1566 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
1567 struct intel_buffer_object
*intel_obj
=
1568 intel_buffer_object(obj
->BufferObject
);
1569 const unsigned texel_size
= (format
== ISL_FORMAT_RAW
? 1 :
1570 _mesa_get_format_bytes(u
->_ActualFormat
));
1572 brw_emit_buffer_surface_state(
1573 brw
, surf_offset
, intel_obj
->buffer
, obj
->BufferOffset
,
1574 format
, intel_obj
->Base
.Size
, texel_size
,
1575 access
!= GL_READ_ONLY
? RELOC_WRITE
: 0);
1577 update_buffer_image_param(brw
, u
, surface_idx
, param
);
1580 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
1581 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
1582 const unsigned num_layers
= u
->Layered
?
1583 get_image_num_layers(mt
, obj
->Target
, u
->Level
) : 1;
1585 struct isl_view view
= {
1587 .base_level
= obj
->MinLevel
+ u
->Level
,
1589 .base_array_layer
= obj
->MinLayer
+ u
->_Layer
,
1590 .array_len
= num_layers
,
1591 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1592 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
1595 if (format
== ISL_FORMAT_RAW
) {
1596 brw_emit_buffer_surface_state(
1597 brw
, surf_offset
, mt
->bo
, mt
->offset
,
1598 format
, mt
->bo
->size
- mt
->offset
, 1 /* pitch */,
1599 access
!= GL_READ_ONLY
? RELOC_WRITE
: 0);
1602 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
1603 assert(!intel_miptree_has_color_unresolved(mt
,
1605 view
.base_array_layer
,
1607 brw_emit_surface_state(brw
, mt
, mt
->target
, view
,
1609 get_tex_mocs(devinfo
, mt
->bo
),
1610 surf_offset
, surf_index
,
1611 access
== GL_READ_ONLY
? 0 : RELOC_WRITE
);
1614 isl_surf_fill_image_param(&brw
->isl_dev
, param
, &mt
->surf
, &view
);
1615 param
->surface_idx
= surface_idx
;
1619 emit_null_surface_state(brw
, NULL
, surf_offset
);
1620 update_default_image_param(brw
, u
, surface_idx
, param
);
1625 brw_upload_image_surfaces(struct brw_context
*brw
,
1626 const struct gl_program
*prog
,
1627 struct brw_stage_state
*stage_state
,
1628 struct brw_stage_prog_data
*prog_data
)
1631 struct gl_context
*ctx
= &brw
->ctx
;
1633 if (prog
->info
.num_images
) {
1634 for (unsigned i
= 0; i
< prog
->info
.num_images
; i
++) {
1635 struct gl_image_unit
*u
= &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[i
]];
1636 const unsigned surf_idx
= prog_data
->binding_table
.image_start
+ i
;
1638 update_image_surface(brw
, u
, prog
->sh
.ImageAccess
[i
],
1640 &stage_state
->surf_offset
[surf_idx
],
1641 &stage_state
->image_param
[i
]);
1644 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1645 /* This may have changed the image metadata dependent on the context
1646 * image unit state and passed to the program as uniforms, make sure
1647 * that push and pull constants are reuploaded.
1649 brw
->NewGLState
|= _NEW_PROGRAM_CONSTANTS
;
1654 brw_upload_wm_image_surfaces(struct brw_context
*brw
)
1656 /* BRW_NEW_FRAGMENT_PROGRAM */
1657 const struct gl_program
*wm
= brw
->programs
[MESA_SHADER_FRAGMENT
];
1660 /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1661 brw_upload_image_surfaces(brw
, wm
, &brw
->wm
.base
,
1662 brw
->wm
.base
.prog_data
);
1666 const struct brw_tracked_state brw_wm_image_surfaces
= {
1668 .mesa
= _NEW_TEXTURE
,
1669 .brw
= BRW_NEW_BATCH
|
1671 BRW_NEW_FRAGMENT_PROGRAM
|
1672 BRW_NEW_FS_PROG_DATA
|
1675 .emit
= brw_upload_wm_image_surfaces
,
1679 brw_upload_cs_work_groups_surface(struct brw_context
*brw
)
1681 struct gl_context
*ctx
= &brw
->ctx
;
1683 struct gl_program
*prog
=
1684 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1685 /* BRW_NEW_CS_PROG_DATA */
1686 const struct brw_cs_prog_data
*cs_prog_data
=
1687 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
1689 if (prog
&& cs_prog_data
->uses_num_work_groups
) {
1690 const unsigned surf_idx
=
1691 cs_prog_data
->binding_table
.work_groups_start
;
1692 uint32_t *surf_offset
= &brw
->cs
.base
.surf_offset
[surf_idx
];
1696 if (brw
->compute
.num_work_groups_bo
== NULL
) {
1698 intel_upload_data(brw
,
1699 (void *)brw
->compute
.num_work_groups
,
1705 bo
= brw
->compute
.num_work_groups_bo
;
1706 bo_offset
= brw
->compute
.num_work_groups_offset
;
1709 brw_emit_buffer_surface_state(brw
, surf_offset
,
1712 3 * sizeof(GLuint
), 1,
1714 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1718 const struct brw_tracked_state brw_cs_work_groups_surface
= {
1720 .brw
= BRW_NEW_CS_PROG_DATA
|
1721 BRW_NEW_CS_WORK_GROUPS
1723 .emit
= brw_upload_cs_work_groups_surface
,