src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "mtypes.h"
  34 #include "texformat.h"
  35 #include "texstore.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( GLuint mesa_format, GLenum depth_mode )
  73 {
  74    switch( mesa_format ) {
  75    case MESA_FORMAT_L8:
  76       return BRW_SURFACEFORMAT_L8_UNORM;
  77
  78    case MESA_FORMAT_I8:
  79       return BRW_SURFACEFORMAT_I8_UNORM;
  80
  81    case MESA_FORMAT_A8:
  82       return BRW_SURFACEFORMAT_A8_UNORM;
  83
  84    case MESA_FORMAT_AL88:
  85       return BRW_SURFACEFORMAT_L8A8_UNORM;
  86
  87    case MESA_FORMAT_RGB888:
  88       assert(0);                /* not supported for sampling */
  89       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  90
  91    case MESA_FORMAT_ARGB8888:
  92       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  93
  94    case MESA_FORMAT_RGBA8888_REV:
  95       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
  96
  97    case MESA_FORMAT_RGB565:
  98       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
  99
 100    case MESA_FORMAT_ARGB1555:
 101       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 102
 103    case MESA_FORMAT_ARGB4444:
 104       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 105
 106    case MESA_FORMAT_YCBCR_REV:
 107       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 108
 109    case MESA_FORMAT_YCBCR:
 110       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 111
 112    case MESA_FORMAT_RGB_FXT1:
 113    case MESA_FORMAT_RGBA_FXT1:
 114       return BRW_SURFACEFORMAT_FXT1;
 115
 116    case MESA_FORMAT_Z16:
 117       if (depth_mode == GL_INTENSITY)
 118           return BRW_SURFACEFORMAT_I16_UNORM;
 119       else if (depth_mode == GL_ALPHA)
 120           return BRW_SURFACEFORMAT_A16_UNORM;
 121       else
 122           return BRW_SURFACEFORMAT_L16_UNORM;
 123
 124    case MESA_FORMAT_RGB_DXT1:
 125        return BRW_SURFACEFORMAT_DXT1_RGB;
 126
 127    case MESA_FORMAT_RGBA_DXT1:
 128        return BRW_SURFACEFORMAT_BC1_UNORM;
 129
 130    case MESA_FORMAT_RGBA_DXT3:
 131        return BRW_SURFACEFORMAT_BC2_UNORM;
 132
 133    case MESA_FORMAT_RGBA_DXT5:
 134        return BRW_SURFACEFORMAT_BC3_UNORM;
 135
 136    case MESA_FORMAT_SRGBA8:
 137       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
 138    case MESA_FORMAT_SRGB_DXT1:
 139       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 140
 141    case MESA_FORMAT_S8_Z24:
 142       return BRW_SURFACEFORMAT_I24X8_UNORM;
 143
 144    default:
 145       assert(0);
 146       return 0;
 147    }
 148 }
 149
 150 struct brw_wm_surface_key {
 151    GLenum target, depthmode;
 152    dri_bo *bo;
 153    GLint format;
 154    GLint first_level, last_level;
 155    GLint width, height, depth;
 156    GLint pitch, cpp;
 157    uint32_t tiling;
 158    GLuint offset;
 159 };
 160
 161 static void
 162 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 163 {
 164    switch (tiling) {
 165    case I915_TILING_NONE:
 166       surf->ss3.tiled_surface = 0;
 167       surf->ss3.tile_walk = 0;
 168       break;
 169    case I915_TILING_X:
 170       surf->ss3.tiled_surface = 1;
 171       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 172       break;
 173    case I915_TILING_Y:
 174       surf->ss3.tiled_surface = 1;
 175       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 176       break;
 177    }
 178 }
 179
 180 static dri_bo *
 181 brw_create_texture_surface( struct brw_context *brw,
 182                             struct brw_wm_surface_key *key )
 183 {
 184    struct brw_surface_state surf;
 185    dri_bo *bo;
 186
 187    memset(&surf, 0, sizeof(surf));
 188
 189    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 190    surf.ss0.surface_type = translate_tex_target(key->target);
 191
 192    if (key->bo)
 193       surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
 194    else {
 195      switch(key->depth) {
 196      case 32: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break;
 197      default:
 198      case 24: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; break;
 199      case 16: surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break;
 200      }
 201    }
 202
 203    /* This is ok for all textures with channel width 8bit or less:
 204     */
 205 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 206    if (key->bo)
 207      surf.ss1.base_addr = key->bo->offset; /* reloc */
 208    else
 209      surf.ss1.base_addr = key->offset;
 210
 211    surf.ss2.mip_count = key->last_level - key->first_level;
 212    surf.ss2.width = key->width - 1;
 213    surf.ss2.height = key->height - 1;
 214    brw_set_surface_tiling(&surf, key->tiling);
 215    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 216    surf.ss3.depth = key->depth - 1;
 217
 218    surf.ss4.min_lod = 0;
 219
 220    if (key->target == GL_TEXTURE_CUBE_MAP) {
 221       surf.ss0.cube_pos_x = 1;
 222       surf.ss0.cube_pos_y = 1;
 223       surf.ss0.cube_pos_z = 1;
 224       surf.ss0.cube_neg_x = 1;
 225       surf.ss0.cube_neg_y = 1;
 226       surf.ss0.cube_neg_z = 1;
 227    }
 228
 229    bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
 230                          key, sizeof(*key),
 231                          &key->bo, key->bo ? 1 : 0,
 232                          &surf, sizeof(surf),
 233                          NULL, NULL);
 234
 235    if (key->bo) {
 236       /* Emit relocation to surface contents */
 237       intel_bo_emit_reloc(bo,
 238                           I915_GEM_DOMAIN_SAMPLER, 0,
 239                           0,
 240                           offsetof(struct brw_surface_state, ss1),
 241                           key->bo);
 242    }
 243    return bo;
 244 }
 245
 246 static void
 247 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 248 {
 249    struct brw_context *brw = brw_context(ctx);
 250    struct gl_texture_object *tObj = brw->attribs.Texture->Unit[unit]._Current;
 251    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 252    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 253    struct brw_wm_surface_key key;
 254
 255    memset(&key, 0, sizeof(key));
 256
 257    if (intelObj->imageOverride) {
 258       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 259       key.depth = intelObj->depthOverride;
 260       key.bo = NULL;
 261       key.offset = intelObj->textureOffset;
 262    } else {
 263       key.format = firstImage->TexFormat->MesaFormat;
 264       key.pitch = intelObj->mt->pitch;
 265       key.depth = firstImage->Depth;
 266       key.bo = intelObj->mt->region->buffer;
 267       key.offset = 0;
 268    }
 269
 270    key.target = tObj->Target;
 271    key.depthmode = tObj->DepthMode;
 272    key.first_level = intelObj->firstLevel;
 273    key.last_level = intelObj->lastLevel;
 274    key.width = firstImage->Width;
 275    key.height = firstImage->Height;
 276    key.cpp = intelObj->mt->cpp;
 277    key.depth = firstImage->Depth;
 278    key.tiling = intelObj->mt->region->tiling;
 279
 280    dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]);
 281    brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
 282                                                                &key, sizeof(key),
 283                                                                &key.bo, key.bo ? 1 : 0,
 284                                                                NULL);
 285    if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) {
 286       brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key);
 287    }
 288 }
 289
 290 /**
 291  * Sets up a surface state structure to point at the given region.
 292  * While it is only used for the front/back buffer currently, it should be
 293  * usable for further buffers when doing ARB_draw_buffer support.
 294  */
 295 static void
 296 brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
 297                           unsigned int unit, GLboolean cached)
 298 {
 299    dri_bo *region_bo = NULL;
 300    struct {
 301       unsigned int surface_type;
 302       unsigned int surface_format;
 303       unsigned int width, height, cpp;
 304       GLubyte color_mask[4];
 305       GLboolean color_blend;
 306       uint32_t tiling;
 307    } key;
 308
 309    memset(&key, 0, sizeof(key));
 310
 311    if (region != NULL) {
 312       region_bo = region->buffer;
 313
 314       key.surface_type = BRW_SURFACE_2D;
 315       if (region->cpp == 4)
 316          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 317       else
 318          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 319       key.tiling = region->tiling;
 320       key.width = region->pitch; /* XXX: not really! */
 321       key.height = region->height;
 322       key.cpp = region->cpp;
 323    } else {
 324       key.surface_type = BRW_SURFACE_NULL;
 325       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 326       key.tiling = 0;
 327       key.width = 1;
 328       key.height = 1;
 329       key.cpp = 4;
 330    }
 331    memcpy(key.color_mask, brw->attribs.Color->ColorMask,
 332           sizeof(key.color_mask));
 333    key.color_blend = (!brw->attribs.Color->_LogicOpEnabled &&
 334                       brw->attribs.Color->BlendEnabled);
 335
 336    dri_bo_unreference(brw->wm.surf_bo[unit]);
 337    brw->wm.surf_bo[unit] = NULL;
 338    if (cached)
 339        brw->wm.surf_bo[unit] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
 340                &key, sizeof(key),
 341                &region_bo, 1,
 342                NULL);
 343
 344    if (brw->wm.surf_bo[unit] == NULL) {
 345       struct brw_surface_state surf;
 346
 347       memset(&surf, 0, sizeof(surf));
 348
 349       surf.ss0.surface_format = key.surface_format;
 350       surf.ss0.surface_type = key.surface_type;
 351       if (region_bo != NULL)
 352          surf.ss1.base_addr = region_bo->offset; /* reloc */
 353
 354       surf.ss2.width = key.width - 1;
 355       surf.ss2.height = key.height - 1;
 356       brw_set_surface_tiling(&surf, key.tiling);
 357       surf.ss3.pitch = (key.width * key.cpp) - 1;
 358
 359       /* _NEW_COLOR */
 360       surf.ss0.color_blend = key.color_blend;
 361       surf.ss0.writedisable_red =   !key.color_mask[0];
 362       surf.ss0.writedisable_green = !key.color_mask[1];
 363       surf.ss0.writedisable_blue =  !key.color_mask[2];
 364       surf.ss0.writedisable_alpha = !key.color_mask[3];
 365
 366       /* Key size will never match key size for textures, so we're safe. */
 367       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
 368                                               &key, sizeof(key),
 369                                                &region_bo, 1,
 370                                                &surf, sizeof(surf),
 371                                                NULL, NULL);
 372       if (region_bo != NULL) {
 373          /* We might sample from it, and we might render to it, so flag
 374           * them both.  We might be able to figure out from other state
 375           * a more restrictive relocation to emit.
 376           */
 377          intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 378                              I915_GEM_DOMAIN_RENDER |
 379                              I915_GEM_DOMAIN_SAMPLER,
 380                              I915_GEM_DOMAIN_RENDER,
 381                              0,
 382                              offsetof(struct brw_surface_state, ss1),
 383                              region_bo);
 384       }
 385    }
 386 }
 387
 388
 389 /**
 390  * Constructs the binding table for the WM surface state, which maps unit
 391  * numbers to surface state objects.
 392  */
 393 static dri_bo *
 394 brw_wm_get_binding_table(struct brw_context *brw)
 395 {
 396    dri_bo *bind_bo;
 397
 398    bind_bo = brw_search_cache(&brw->cache, BRW_SS_SURF_BIND,
 399                               NULL, 0,
 400                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 401                               NULL);
 402
 403    if (bind_bo == NULL) {
 404       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 405       uint32_t *data = malloc(data_size);
 406       int i;
 407
 408       for (i = 0; i < brw->wm.nr_surfaces; i++)
 409          if (brw->wm.surf_bo[i])
 410             data[i] = brw->wm.surf_bo[i]->offset;
 411          else
 412             data[i] = 0;
 413
 414       bind_bo = brw_upload_cache( &brw->cache, BRW_SS_SURF_BIND,
 415                                   NULL, 0,
 416                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 417                                   data, data_size,
 418                                   NULL, NULL);
 419
 420       /* Emit binding table relocations to surface state */
 421       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 422          if (brw->wm.surf_bo[i] != NULL) {
 423             intel_bo_emit_reloc(bind_bo,
 424                                 I915_GEM_DOMAIN_INSTRUCTION, 0,
 425                                 0,
 426                                 i * sizeof(GLuint),
 427                                 brw->wm.surf_bo[i]);
 428          }
 429       }
 430
 431       free(data);
 432    }
 433
 434    return bind_bo;
 435 }
 436
 437 static void prepare_wm_surfaces(struct brw_context *brw )
 438 {
 439    GLcontext *ctx = &brw->intel.ctx;
 440    struct intel_context *intel = &brw->intel;
 441    GLuint i;
 442
 443    if (brw->state.nr_draw_regions  > 1) {
 444       for (i = 0; i < brw->state.nr_draw_regions; i++) {
 445          brw_update_region_surface(brw, brw->state.draw_regions[i], i,
 446                                    GL_FALSE);
 447       }
 448    }else {
 449       brw_update_region_surface(brw, brw->state.draw_regions[0], 0, GL_TRUE);
 450    }
 451
 452    brw->wm.nr_surfaces = MAX_DRAW_BUFFERS;
 453
 454    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 455       struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[i];
 456
 457       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 458       if(texUnit->_ReallyEnabled) {
 459          if (texUnit->_Current == intel->frame_buffer_texobj) {
 460             dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 461             brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = brw->wm.surf_bo[0];
 462             dri_bo_reference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 463             brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1;
 464          } else {
 465             brw_update_texture_surface(ctx, i);
 466             brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1;
 467          }
 468       } else {
 469          dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]);
 470          brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = NULL;
 471       }
 472
 473    }
 474
 475    dri_bo_unreference(brw->wm.bind_bo);
 476    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 477 }
 478
 479
 480 const struct brw_tracked_state brw_wm_surfaces = {
 481    .dirty = {
 482       .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
 483       .brw = BRW_NEW_CONTEXT,
 484       .cache = 0
 485    },
 486    .prepare = prepare_wm_surfaces,
 487 };
 488
 489
 490