2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "program/prog_parameter.h"
39 #include "intel_mipmap_tree.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_fbo.h"
43 #include "intel_buffer_objects.h"
45 #include "brw_context.h"
46 #include "brw_state.h"
47 #include "brw_defines.h"
51 translate_tex_target(GLenum target
)
55 case GL_TEXTURE_1D_ARRAY_EXT
:
56 return BRW_SURFACE_1D
;
58 case GL_TEXTURE_RECTANGLE_NV
:
59 return BRW_SURFACE_2D
;
62 case GL_TEXTURE_2D_ARRAY_EXT
:
63 case GL_TEXTURE_EXTERNAL_OES
:
64 case GL_TEXTURE_2D_MULTISAMPLE
:
65 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
66 return BRW_SURFACE_2D
;
69 return BRW_SURFACE_3D
;
71 case GL_TEXTURE_CUBE_MAP
:
72 case GL_TEXTURE_CUBE_MAP_ARRAY
:
73 return BRW_SURFACE_CUBE
;
76 unreachable("not reached");
81 brw_get_surface_tiling_bits(uint32_t tiling
)
85 return BRW_SURFACE_TILED
;
87 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
95 brw_get_surface_num_multisamples(unsigned num_samples
)
98 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
100 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
104 brw_configure_w_tiled(const struct intel_mipmap_tree
*mt
,
105 bool is_render_target
,
106 unsigned *width
, unsigned *height
,
107 unsigned *pitch
, uint32_t *tiling
, unsigned *format
)
109 static const unsigned halign_stencil
= 8;
111 /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
112 * there are half as many rows.
113 * In addition, mip-levels are accessed manually by the program and
114 * therefore the surface is setup to cover all the mip-levels for one slice.
115 * (Hardware is still used to access individual slices).
117 *tiling
= I915_TILING_Y
;
118 *pitch
= mt
->pitch
* 2;
119 *width
= ALIGN(mt
->total_width
, halign_stencil
) * 2;
120 *height
= (mt
->total_height
/ mt
->physical_depth0
) / 2;
122 if (is_render_target
) {
123 *format
= BRW_SURFACEFORMAT_R8_UINT
;
129 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
133 brw_get_texture_swizzle(const struct gl_context
*ctx
,
134 const struct gl_texture_object
*t
)
136 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
138 int swizzles
[SWIZZLE_NIL
+ 1] = {
148 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
149 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
150 GLenum depth_mode
= t
->DepthMode
;
152 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
153 * with depth component data specified with a sized internal format.
154 * Otherwise, it's left at the old default, GL_LUMINANCE.
156 if (_mesa_is_gles3(ctx
) &&
157 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
158 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
162 switch (depth_mode
) {
164 swizzles
[0] = SWIZZLE_ZERO
;
165 swizzles
[1] = SWIZZLE_ZERO
;
166 swizzles
[2] = SWIZZLE_ZERO
;
167 swizzles
[3] = SWIZZLE_X
;
170 swizzles
[0] = SWIZZLE_X
;
171 swizzles
[1] = SWIZZLE_X
;
172 swizzles
[2] = SWIZZLE_X
;
173 swizzles
[3] = SWIZZLE_ONE
;
176 swizzles
[0] = SWIZZLE_X
;
177 swizzles
[1] = SWIZZLE_X
;
178 swizzles
[2] = SWIZZLE_X
;
179 swizzles
[3] = SWIZZLE_X
;
182 swizzles
[0] = SWIZZLE_X
;
183 swizzles
[1] = SWIZZLE_ZERO
;
184 swizzles
[2] = SWIZZLE_ZERO
;
185 swizzles
[3] = SWIZZLE_ONE
;
190 /* If the texture's format is alpha-only, force R, G, and B to
191 * 0.0. Similarly, if the texture's format has no alpha channel,
192 * force the alpha value read to 1.0. This allows for the
193 * implementation to use an RGBA texture for any of these formats
194 * without leaking any unexpected values.
196 switch (img
->_BaseFormat
) {
198 swizzles
[0] = SWIZZLE_ZERO
;
199 swizzles
[1] = SWIZZLE_ZERO
;
200 swizzles
[2] = SWIZZLE_ZERO
;
205 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
206 swizzles
[3] = SWIZZLE_ONE
;
210 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
211 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
212 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
213 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
217 gen4_emit_buffer_surface_state(struct brw_context
*brw
,
218 uint32_t *out_offset
,
220 unsigned buffer_offset
,
221 unsigned surface_format
,
222 unsigned buffer_size
,
227 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
228 6 * 4, 32, out_offset
);
229 memset(surf
, 0, 6 * 4);
231 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
232 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
233 (brw
->gen
>= 6 ? BRW_SURFACE_RC_READ_WRITE
: 0);
234 surf
[1] = (bo
? bo
->offset64
: 0) + buffer_offset
; /* reloc */
235 surf
[2] = (buffer_size
& 0x7f) << BRW_SURFACE_WIDTH_SHIFT
|
236 ((buffer_size
>> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT
;
237 surf
[3] = ((buffer_size
>> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT
|
238 (pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
;
240 /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
241 * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
242 * physical cache. It is mapped in hardware to the sampler cache."
245 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
247 I915_GEM_DOMAIN_SAMPLER
,
248 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
253 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
255 uint32_t *surf_offset
)
257 struct brw_context
*brw
= brw_context(ctx
);
258 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
259 struct intel_buffer_object
*intel_obj
=
260 intel_buffer_object(tObj
->BufferObject
);
261 uint32_t size
= tObj
->BufferSize
;
262 drm_intel_bo
*bo
= NULL
;
263 mesa_format format
= tObj
->_BufferObjectFormat
;
264 uint32_t brw_format
= brw_format_for_mesa_format(format
);
265 int texel_size
= _mesa_get_format_bytes(format
);
268 size
= MIN2(size
, intel_obj
->Base
.Size
);
269 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
272 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
273 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
274 _mesa_get_format_name(format
));
277 brw
->vtbl
.emit_buffer_surface_state(brw
, surf_offset
, bo
,
287 brw_update_texture_surface(struct gl_context
*ctx
,
289 uint32_t *surf_offset
,
292 struct brw_context
*brw
= brw_context(ctx
);
293 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
294 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
295 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
296 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
299 /* BRW_NEW_UNIFORM_BUFFER */
300 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
301 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
305 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
306 6 * 4, 32, surf_offset
);
308 uint32_t tex_format
= translate_tex_format(brw
, mt
->format
,
309 sampler
->sRGBDecode
);
312 /* Sandybridge's gather4 message is broken for integer formats.
313 * To work around this, we pretend the surface is UNORM for
314 * 8 or 16-bit formats, and emit shader instructions to recover
315 * the real INT/UINT value. For 32-bit formats, we pretend
316 * the surface is FLOAT, and simply reinterpret the resulting
319 switch (tex_format
) {
320 case BRW_SURFACEFORMAT_R8_SINT
:
321 case BRW_SURFACEFORMAT_R8_UINT
:
322 tex_format
= BRW_SURFACEFORMAT_R8_UNORM
;
325 case BRW_SURFACEFORMAT_R16_SINT
:
326 case BRW_SURFACEFORMAT_R16_UINT
:
327 tex_format
= BRW_SURFACEFORMAT_R16_UNORM
;
330 case BRW_SURFACEFORMAT_R32_SINT
:
331 case BRW_SURFACEFORMAT_R32_UINT
:
332 tex_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
340 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
341 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
342 BRW_SURFACE_CUBEFACE_ENABLES
|
343 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
);
345 surf
[1] = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
347 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
348 (mt
->logical_width0
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
349 (mt
->logical_height0
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
351 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
352 (mt
->logical_depth0
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
353 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
355 surf
[4] = (brw_get_surface_num_multisamples(mt
->num_samples
) |
356 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
, BRW_SURFACE_MIN_LOD
));
358 surf
[5] = mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0;
360 /* Emit relocation to surface contents */
361 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
364 surf
[1] - mt
->bo
->offset64
,
365 I915_GEM_DOMAIN_SAMPLER
, 0);
369 * Create the constant buffer surface. Vertex/fragment shader constants will be
370 * read from this buffer with Data Port Read instructions/messages.
373 brw_create_constant_surface(struct brw_context
*brw
,
377 uint32_t *out_offset
,
380 uint32_t stride
= dword_pitch
? 4 : 16;
381 uint32_t elements
= ALIGN(size
, stride
) / stride
;
383 brw
->vtbl
.emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
384 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
385 elements
, stride
, 0, false);
389 * Set up a binding table entry for use by stream output logic (transform
392 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
395 brw_update_sol_surface(struct brw_context
*brw
,
396 struct gl_buffer_object
*buffer_obj
,
397 uint32_t *out_offset
, unsigned num_vector_components
,
398 unsigned stride_dwords
, unsigned offset_dwords
)
400 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
401 uint32_t offset_bytes
= 4 * offset_dwords
;
402 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
404 buffer_obj
->Size
- offset_bytes
);
405 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
407 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
408 size_t size_dwords
= buffer_obj
->Size
/ 4;
409 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
411 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
412 * too big to map using a single binding table entry?
414 assert((size_dwords
- offset_dwords
) / stride_dwords
415 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
417 if (size_dwords
> offset_dwords
+ num_vector_components
) {
418 /* There is room for at least 1 transform feedback output in the buffer.
419 * Compute the number of additional transform feedback outputs the
420 * buffer has room for.
422 buffer_size_minus_1
=
423 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
425 /* There isn't even room for a single transform feedback output in the
426 * buffer. We can't configure the binding table entry to prevent output
427 * entirely; we'll have to rely on the geometry shader to detect
428 * overflow. But to minimize the damage in case of a bug, set up the
429 * binding table entry to just allow a single output.
431 buffer_size_minus_1
= 0;
433 width
= buffer_size_minus_1
& 0x7f;
434 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
435 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
437 switch (num_vector_components
) {
439 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
442 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
445 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
448 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
451 unreachable("Invalid vector size for transform feedback output");
454 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
455 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
456 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
457 BRW_SURFACE_RC_READ_WRITE
;
458 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
459 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
460 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
461 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
462 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
466 /* Emit relocation to surface contents. */
467 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
470 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
473 /* Creates a new WM constant buffer reflecting the current fragment program's
474 * constants, if needed by the fragment program.
476 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
480 brw_upload_wm_pull_constants(struct brw_context
*brw
)
482 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
483 /* BRW_NEW_FRAGMENT_PROGRAM */
484 struct brw_fragment_program
*fp
=
485 (struct brw_fragment_program
*) brw
->fragment_program
;
486 /* CACHE_NEW_WM_PROG */
487 struct brw_stage_prog_data
*prog_data
= &brw
->wm
.prog_data
->base
;
489 /* _NEW_PROGRAM_CONSTANTS */
490 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
.Base
,
491 stage_state
, prog_data
, true);
494 const struct brw_tracked_state brw_wm_pull_constants
= {
496 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
497 .brw
= (BRW_NEW_BATCH
| BRW_NEW_FRAGMENT_PROGRAM
),
498 .cache
= CACHE_NEW_WM_PROG
,
500 .emit
= brw_upload_wm_pull_constants
,
504 * Creates a null renderbuffer surface.
506 * This is used when the shader doesn't write to any color output. An FB
507 * write to target 0 will still be emitted, because that's how the thread is
508 * terminated (and computed depth is returned), so we need to have the
509 * hardware discard the target 0 color output..
512 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
514 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
517 * A null surface will be used in instances where an actual surface is
518 * not bound. When a write message is generated to a null surface, no
519 * actual surface is written to. When a read message (including any
520 * sampling engine message) is generated to a null surface, the result
521 * is all zeros. Note that a null surface type is allowed to be used
522 * with all messages, even if it is not specificially indicated as
523 * supported. All of the remaining fields in surface state are ignored
524 * for null surfaces, with the following exceptions:
526 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
527 * depth buffer’s corresponding state for all render target surfaces,
530 * - Surface Format must be R8G8B8A8_UNORM.
532 struct gl_context
*ctx
= &brw
->ctx
;
534 unsigned surface_type
= BRW_SURFACE_NULL
;
535 drm_intel_bo
*bo
= NULL
;
536 unsigned pitch_minus_1
= 0;
537 uint32_t multisampling_state
= 0;
538 uint32_t surf_index
=
539 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
542 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
544 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
545 &brw
->wm
.base
.surf_offset
[surf_index
]);
547 if (fb
->Visual
.samples
> 1) {
548 /* On Gen6, null render targets seem to cause GPU hangs when
549 * multisampling. So work around this problem by rendering into dummy
552 * To decrease the amount of memory needed by the workaround buffer, we
553 * set its pitch to 128 bytes (the width of a Y tile). This means that
554 * the amount of memory needed for the workaround buffer is
555 * (width_in_tiles + height_in_tiles - 1) tiles.
557 * Note that since the workaround buffer will be interpreted by the
558 * hardware as an interleaved multisampled buffer, we need to compute
559 * width_in_tiles and height_in_tiles by dividing the width and height
560 * by 16 rather than the normal Y-tile size of 32.
562 unsigned width_in_tiles
= ALIGN(fb
->Width
, 16) / 16;
563 unsigned height_in_tiles
= ALIGN(fb
->Height
, 16) / 16;
564 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
565 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
567 bo
= brw
->wm
.multisampled_null_render_target_bo
;
568 surface_type
= BRW_SURFACE_2D
;
570 multisampling_state
=
571 brw_get_surface_num_multisamples(fb
->Visual
.samples
);
574 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
575 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
577 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
578 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
579 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
580 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
582 surf
[1] = bo
? bo
->offset64
: 0;
583 surf
[2] = ((fb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
584 (fb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
586 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
589 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
591 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
592 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
593 surf
[4] = multisampling_state
;
597 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
598 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
600 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
605 * Sets up a surface state structure to point at the given region.
606 * While it is only used for the front/back buffer currently, it should be
607 * usable for further buffers when doing ARB_draw_buffer support.
610 brw_update_renderbuffer_surface(struct brw_context
*brw
,
611 struct gl_renderbuffer
*rb
,
615 struct gl_context
*ctx
= &brw
->ctx
;
616 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
617 struct intel_mipmap_tree
*mt
= irb
->mt
;
619 uint32_t tile_x
, tile_y
;
622 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
623 uint32_t surf_index
=
624 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
628 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
629 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
631 if (tile_x
!= 0 || tile_y
!= 0) {
632 /* Original gen4 hardware couldn't draw to a non-tile-aligned
633 * destination in a miptree unless you actually setup your renderbuffer
634 * as a miptree and used the fragile lod/array_index/etc. controls to
635 * select the image. So, instead, we just make a new single-level
636 * miptree and render into that.
638 intel_renderbuffer_move_to_temp(brw
, irb
, false);
643 intel_miptree_used_for_rendering(irb
->mt
);
645 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
646 &brw
->wm
.base
.surf_offset
[surf_index
]);
648 format
= brw
->render_target_format
[rb_format
];
649 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
650 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
651 __FUNCTION__
, _mesa_get_format_name(rb_format
));
654 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
655 format
<< BRW_SURFACE_FORMAT_SHIFT
);
658 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
661 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
662 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
664 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
665 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
667 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
669 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
670 /* Note that the low bits of these fields are missing, so
671 * there's the possibility of getting in trouble.
673 assert(tile_x
% 4 == 0);
674 assert(tile_y
% 2 == 0);
675 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
676 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
677 (mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
681 if (!ctx
->Color
.ColorLogicOpEnabled
&&
682 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
683 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
685 if (!ctx
->Color
.ColorMask
[unit
][0])
686 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
687 if (!ctx
->Color
.ColorMask
[unit
][1])
688 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
689 if (!ctx
->Color
.ColorMask
[unit
][2])
690 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
692 /* As mentioned above, disable writes to the alpha component when the
693 * renderbuffer is XRGB.
695 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
696 !ctx
->Color
.ColorMask
[unit
][3]) {
697 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
701 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
702 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
704 surf
[1] - mt
->bo
->offset64
,
705 I915_GEM_DOMAIN_RENDER
,
706 I915_GEM_DOMAIN_RENDER
);
710 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
713 brw_update_renderbuffer_surfaces(struct brw_context
*brw
)
715 struct gl_context
*ctx
= &brw
->ctx
;
718 /* _NEW_BUFFERS | _NEW_COLOR */
719 /* Update surfaces for drawing buffers */
720 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
721 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
722 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
723 brw
->vtbl
.update_renderbuffer_surface(brw
, ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
724 ctx
->DrawBuffer
->MaxNumLayers
> 0, i
);
726 brw
->vtbl
.update_null_renderbuffer_surface(brw
, i
);
730 brw
->vtbl
.update_null_renderbuffer_surface(brw
, 0);
732 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
735 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
737 .mesa
= (_NEW_COLOR
|
739 .brw
= BRW_NEW_BATCH
,
742 .emit
= brw_update_renderbuffer_surfaces
,
745 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
747 .mesa
= _NEW_BUFFERS
,
748 .brw
= BRW_NEW_BATCH
,
751 .emit
= brw_update_renderbuffer_surfaces
,
756 update_stage_texture_surfaces(struct brw_context
*brw
,
757 const struct gl_program
*prog
,
758 struct brw_stage_state
*stage_state
,
764 struct gl_context
*ctx
= &brw
->ctx
;
766 uint32_t *surf_offset
= stage_state
->surf_offset
;
768 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
770 surf_offset
+= stage_state
->prog_data
->binding_table
.texture_start
;
772 unsigned num_samplers
= _mesa_fls(prog
->SamplersUsed
);
773 for (unsigned s
= 0; s
< num_samplers
; s
++) {
776 if (prog
->SamplersUsed
& (1 << s
)) {
777 const unsigned unit
= prog
->SamplerUnits
[s
];
780 if (ctx
->Texture
.Unit
[unit
]._Current
) {
781 brw
->vtbl
.update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
);
789 * Construct SURFACE_STATE objects for enabled textures.
792 brw_update_texture_surfaces(struct brw_context
*brw
)
794 /* BRW_NEW_VERTEX_PROGRAM */
795 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
797 /* BRW_NEW_GEOMETRY_PROGRAM */
798 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
800 /* BRW_NEW_FRAGMENT_PROGRAM */
801 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
804 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false);
805 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false);
806 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false);
808 /* emit alternate set of surface state for gather. this
809 * allows the surface format to be overriden for only the
810 * gather4 messages. */
812 if (vs
&& vs
->UsesGather
)
813 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true);
814 if (gs
&& gs
->UsesGather
)
815 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true);
816 if (fs
&& fs
->UsesGather
)
817 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true);
820 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
823 const struct brw_tracked_state brw_texture_surfaces
= {
825 .mesa
= _NEW_TEXTURE
,
826 .brw
= BRW_NEW_BATCH
|
827 BRW_NEW_UNIFORM_BUFFER
|
828 BRW_NEW_VERTEX_PROGRAM
|
829 BRW_NEW_GEOMETRY_PROGRAM
|
830 BRW_NEW_FRAGMENT_PROGRAM
,
833 .emit
= brw_update_texture_surfaces
,
837 brw_upload_ubo_surfaces(struct brw_context
*brw
,
838 struct gl_shader
*shader
,
839 struct brw_stage_state
*stage_state
,
840 struct brw_stage_prog_data
*prog_data
)
842 struct gl_context
*ctx
= &brw
->ctx
;
847 uint32_t *surf_offsets
=
848 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
850 for (int i
= 0; i
< shader
->NumUniformBlocks
; i
++) {
851 struct gl_uniform_buffer_binding
*binding
;
852 struct intel_buffer_object
*intel_bo
;
854 binding
= &ctx
->UniformBufferBindings
[shader
->UniformBlocks
[i
].Binding
];
855 intel_bo
= intel_buffer_object(binding
->BufferObject
);
857 intel_bufferobj_buffer(brw
, intel_bo
,
859 binding
->BufferObject
->Size
- binding
->Offset
);
861 /* Because behavior for referencing outside of the binding's size in the
862 * glBindBufferRange case is undefined, we can just bind the whole buffer
863 * glBindBufferBase wants and be a correct implementation.
865 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
866 bo
->size
- binding
->Offset
,
868 shader
->Stage
== MESA_SHADER_FRAGMENT
);
871 if (shader
->NumUniformBlocks
)
872 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
876 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
878 struct gl_context
*ctx
= &brw
->ctx
;
880 struct gl_shader_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
885 /* CACHE_NEW_WM_PROG */
886 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
887 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
890 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
892 .mesa
= _NEW_PROGRAM
,
893 .brw
= BRW_NEW_BATCH
| BRW_NEW_UNIFORM_BUFFER
,
894 .cache
= CACHE_NEW_WM_PROG
,
896 .emit
= brw_upload_wm_ubo_surfaces
,
900 brw_upload_abo_surfaces(struct brw_context
*brw
,
901 struct gl_shader_program
*prog
,
902 struct brw_stage_state
*stage_state
,
903 struct brw_stage_prog_data
*prog_data
)
905 struct gl_context
*ctx
= &brw
->ctx
;
906 uint32_t *surf_offsets
=
907 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
909 for (int i
= 0; i
< prog
->NumAtomicBuffers
; i
++) {
910 struct gl_atomic_buffer_binding
*binding
=
911 &ctx
->AtomicBufferBindings
[prog
->AtomicBuffers
[i
].Binding
];
912 struct intel_buffer_object
*intel_bo
=
913 intel_buffer_object(binding
->BufferObject
);
914 drm_intel_bo
*bo
= intel_bufferobj_buffer(
915 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
917 brw
->vtbl
.create_raw_surface(brw
, bo
, binding
->Offset
,
918 bo
->size
- binding
->Offset
,
919 &surf_offsets
[i
], true);
922 if (prog
->NumUniformBlocks
)
923 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
927 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
929 struct gl_context
*ctx
= &brw
->ctx
;
931 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
934 /* CACHE_NEW_WM_PROG */
935 brw_upload_abo_surfaces(brw
, prog
, &brw
->wm
.base
,
936 &brw
->wm
.prog_data
->base
);
940 const struct brw_tracked_state brw_wm_abo_surfaces
= {
942 .mesa
= _NEW_PROGRAM
,
943 .brw
= BRW_NEW_BATCH
| BRW_NEW_ATOMIC_BUFFER
,
944 .cache
= CACHE_NEW_WM_PROG
,
946 .emit
= brw_upload_wm_abo_surfaces
,
950 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
952 brw
->vtbl
.update_texture_surface
= brw_update_texture_surface
;
953 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
954 brw
->vtbl
.update_null_renderbuffer_surface
=
955 brw_update_null_renderbuffer_surface
;
956 brw
->vtbl
.emit_buffer_surface_state
= gen4_emit_buffer_surface_state
;