2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/texstore.h"
35 #include "program/prog_parameter.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
47 static GLuint
translate_tex_target( GLenum target
)
51 return BRW_SURFACE_1D
;
53 case GL_TEXTURE_RECTANGLE_NV
:
54 return BRW_SURFACE_2D
;
57 return BRW_SURFACE_2D
;
60 return BRW_SURFACE_3D
;
62 case GL_TEXTURE_CUBE_MAP
:
63 return BRW_SURFACE_CUBE
;
72 static GLuint
translate_tex_format( gl_format mesa_format
,
73 GLenum internal_format
,
76 switch( mesa_format
) {
78 return BRW_SURFACEFORMAT_L8_UNORM
;
81 return BRW_SURFACEFORMAT_I8_UNORM
;
84 return BRW_SURFACEFORMAT_A8_UNORM
;
86 case MESA_FORMAT_AL88
:
87 return BRW_SURFACEFORMAT_L8A8_UNORM
;
89 case MESA_FORMAT_AL1616
:
90 return BRW_SURFACEFORMAT_L16A16_UNORM
;
93 return BRW_SURFACEFORMAT_R8_UNORM
;
96 return BRW_SURFACEFORMAT_R16_UNORM
;
98 case MESA_FORMAT_RG88
:
99 return BRW_SURFACEFORMAT_R8G8_UNORM
;
101 case MESA_FORMAT_RG1616
:
102 return BRW_SURFACEFORMAT_R16G16_UNORM
;
104 case MESA_FORMAT_RGB888
:
105 assert(0); /* not supported for sampling */
106 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
108 case MESA_FORMAT_ARGB8888
:
109 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
111 case MESA_FORMAT_XRGB8888
:
112 return BRW_SURFACEFORMAT_B8G8R8X8_UNORM
;
114 case MESA_FORMAT_RGBA8888_REV
:
115 _mesa_problem(NULL
, "unexpected format in i965:translate_tex_format()");
116 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
118 case MESA_FORMAT_RGB565
:
119 return BRW_SURFACEFORMAT_B5G6R5_UNORM
;
121 case MESA_FORMAT_ARGB1555
:
122 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
124 case MESA_FORMAT_ARGB4444
:
125 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
127 case MESA_FORMAT_YCBCR_REV
:
128 return BRW_SURFACEFORMAT_YCRCB_NORMAL
;
130 case MESA_FORMAT_YCBCR
:
131 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY
;
133 case MESA_FORMAT_RGB_FXT1
:
134 case MESA_FORMAT_RGBA_FXT1
:
135 return BRW_SURFACEFORMAT_FXT1
;
137 case MESA_FORMAT_Z16
:
138 if (depth_mode
== GL_INTENSITY
)
139 return BRW_SURFACEFORMAT_I16_UNORM
;
140 else if (depth_mode
== GL_ALPHA
)
141 return BRW_SURFACEFORMAT_A16_UNORM
;
143 return BRW_SURFACEFORMAT_L16_UNORM
;
145 case MESA_FORMAT_RGB_DXT1
:
146 return BRW_SURFACEFORMAT_DXT1_RGB
;
148 case MESA_FORMAT_RGBA_DXT1
:
149 return BRW_SURFACEFORMAT_BC1_UNORM
;
151 case MESA_FORMAT_RGBA_DXT3
:
152 return BRW_SURFACEFORMAT_BC2_UNORM
;
154 case MESA_FORMAT_RGBA_DXT5
:
155 return BRW_SURFACEFORMAT_BC3_UNORM
;
157 case MESA_FORMAT_SARGB8
:
158 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
;
160 case MESA_FORMAT_SLA8
:
161 return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB
;
163 case MESA_FORMAT_SL8
:
164 return BRW_SURFACEFORMAT_L8_UNORM_SRGB
;
166 case MESA_FORMAT_SRGB_DXT1
:
167 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB
;
169 case MESA_FORMAT_S8_Z24
:
170 /* XXX: these different surface formats don't seem to
171 * make any difference for shadow sampler/compares.
173 if (depth_mode
== GL_INTENSITY
)
174 return BRW_SURFACEFORMAT_I24X8_UNORM
;
175 else if (depth_mode
== GL_ALPHA
)
176 return BRW_SURFACEFORMAT_A24X8_UNORM
;
178 return BRW_SURFACEFORMAT_L24X8_UNORM
;
180 case MESA_FORMAT_DUDV8
:
181 return BRW_SURFACEFORMAT_R8G8_SNORM
;
183 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
184 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM
;
193 brw_set_surface_tiling(struct brw_surface_state
*surf
, uint32_t tiling
)
196 case I915_TILING_NONE
:
197 surf
->ss3
.tiled_surface
= 0;
198 surf
->ss3
.tile_walk
= 0;
201 surf
->ss3
.tiled_surface
= 1;
202 surf
->ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
205 surf
->ss3
.tiled_surface
= 1;
206 surf
->ss3
.tile_walk
= BRW_TILEWALK_YMAJOR
;
212 brw_update_texture_surface( struct gl_context
*ctx
, GLuint unit
)
214 struct brw_context
*brw
= brw_context(ctx
);
215 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
216 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
217 struct gl_texture_image
*firstImage
= tObj
->Image
[0][intelObj
->firstLevel
];
218 const GLuint surf_index
= SURF_INDEX_TEXTURE(unit
);
219 struct brw_surface_state surf
;
222 memset(&surf
, 0, sizeof(surf
));
224 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
225 surf
.ss0
.surface_type
= translate_tex_target(tObj
->Target
);
226 surf
.ss0
.surface_format
= translate_tex_format(firstImage
->TexFormat
,
227 firstImage
->InternalFormat
,
230 /* This is ok for all textures with channel width 8bit or less:
232 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
233 surf
.ss1
.base_addr
= intelObj
->mt
->region
->buffer
->offset
; /* reloc */
235 surf
.ss2
.mip_count
= intelObj
->lastLevel
- intelObj
->firstLevel
;
236 surf
.ss2
.width
= firstImage
->Width
- 1;
237 surf
.ss2
.height
= firstImage
->Height
- 1;
238 brw_set_surface_tiling(&surf
, intelObj
->mt
->region
->tiling
);
239 surf
.ss3
.pitch
= (intelObj
->mt
->region
->pitch
* intelObj
->mt
->cpp
) - 1;
240 surf
.ss3
.depth
= firstImage
->Depth
- 1;
242 surf
.ss4
.min_lod
= 0;
244 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
245 surf
.ss0
.cube_pos_x
= 1;
246 surf
.ss0
.cube_pos_y
= 1;
247 surf
.ss0
.cube_pos_z
= 1;
248 surf
.ss0
.cube_neg_x
= 1;
249 surf
.ss0
.cube_neg_y
= 1;
250 surf
.ss0
.cube_neg_z
= 1;
253 map
= brw_state_batch(brw
, sizeof(surf
), 32,
254 &brw
->wm
.surf_bo
[surf_index
],
255 &brw
->wm
.surf_offset
[surf_index
]);
256 memcpy(map
, &surf
, sizeof(surf
));
258 /* Emit relocation to surface contents */
259 drm_intel_bo_emit_reloc(brw
->wm
.surf_bo
[surf_index
],
260 brw
->wm
.surf_offset
[surf_index
] +
261 offsetof(struct brw_surface_state
, ss1
),
262 intelObj
->mt
->region
->buffer
, 0,
263 I915_GEM_DOMAIN_SAMPLER
, 0);
267 * Create the constant buffer surface. Vertex/fragment shader constants will be
268 * read from this buffer with Data Port Read instructions/messages.
271 brw_create_constant_surface(struct brw_context
*brw
,
274 drm_intel_bo
**out_bo
,
275 uint32_t *out_offset
)
277 const GLint w
= width
- 1;
278 struct brw_surface_state surf
;
281 memset(&surf
, 0, sizeof(surf
));
283 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
284 surf
.ss0
.surface_type
= BRW_SURFACE_BUFFER
;
285 surf
.ss0
.surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
288 surf
.ss1
.base_addr
= bo
->offset
; /* reloc */
290 surf
.ss2
.width
= w
& 0x7f; /* bits 6:0 of size or width */
291 surf
.ss2
.height
= (w
>> 7) & 0x1fff; /* bits 19:7 of size or width */
292 surf
.ss3
.depth
= (w
>> 20) & 0x7f; /* bits 26:20 of size or width */
293 surf
.ss3
.pitch
= (width
* 16) - 1; /* ignored?? */
294 brw_set_surface_tiling(&surf
, I915_TILING_NONE
); /* tiling now allowed */
296 map
= brw_state_batch(brw
, sizeof(surf
), 32, out_bo
, out_offset
);
297 memcpy(map
, &surf
, sizeof(surf
));
299 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
300 * bspec ("Data Cache") says that the data cache does not exist as
301 * a separate cache and is just the sampler cache.
303 drm_intel_bo_emit_reloc(*out_bo
, (*out_offset
+
304 offsetof(struct brw_surface_state
, ss1
)),
306 I915_GEM_DOMAIN_SAMPLER
, 0);
309 /* Creates a new WM constant buffer reflecting the current fragment program's
310 * constants, if needed by the fragment program.
312 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
316 prepare_wm_constants(struct brw_context
*brw
)
318 struct gl_context
*ctx
= &brw
->intel
.ctx
;
319 struct intel_context
*intel
= &brw
->intel
;
320 struct brw_fragment_program
*fp
=
321 (struct brw_fragment_program
*) brw
->fragment_program
;
322 const struct gl_program_parameter_list
*params
= fp
->program
.Base
.Parameters
;
323 const int size
= params
->NumParameters
* 4 * sizeof(GLfloat
);
325 _mesa_load_state_parameters(ctx
, fp
->program
.Base
.Parameters
);
327 /* BRW_NEW_FRAGMENT_PROGRAM */
328 if (!fp
->use_const_buffer
) {
329 if (brw
->wm
.const_bo
) {
330 drm_intel_bo_unreference(brw
->wm
.const_bo
);
331 brw
->wm
.const_bo
= NULL
;
332 brw
->state
.dirty
.brw
|= BRW_NEW_WM_CONSTBUF
;
337 drm_intel_bo_unreference(brw
->wm
.const_bo
);
338 brw
->wm
.const_bo
= drm_intel_bo_alloc(intel
->bufmgr
, "vp_const_buffer",
341 /* _NEW_PROGRAM_CONSTANTS */
342 drm_intel_bo_subdata(brw
->wm
.const_bo
, 0, size
, params
->ParameterValues
);
345 const struct brw_tracked_state brw_wm_constants
= {
347 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
348 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
),
351 .prepare
= prepare_wm_constants
,
355 * Updates surface / buffer for fragment shader constant buffer, if
358 * This consumes the state updates for the constant buffer, and produces
359 * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
360 * inclusion in the binding table.
362 static void upload_wm_constant_surface(struct brw_context
*brw
)
364 GLuint surf
= SURF_INDEX_FRAG_CONST_BUFFER
;
365 struct brw_fragment_program
*fp
=
366 (struct brw_fragment_program
*) brw
->fragment_program
;
367 const struct gl_program_parameter_list
*params
=
368 fp
->program
.Base
.Parameters
;
370 /* If there's no constant buffer, then no surface BO is needed to point at
373 if (brw
->wm
.const_bo
== 0) {
374 if (brw
->wm
.surf_bo
[surf
] != NULL
) {
375 drm_intel_bo_unreference(brw
->wm
.surf_bo
[surf
]);
376 brw
->wm
.surf_bo
[surf
] = NULL
;
377 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
382 brw_create_constant_surface(brw
, brw
->wm
.const_bo
, params
->NumParameters
,
383 &brw
->wm
.surf_bo
[surf
],
384 &brw
->wm
.surf_offset
[surf
]);
385 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
388 const struct brw_tracked_state brw_wm_constant_surface
= {
391 .brw
= (BRW_NEW_WM_CONSTBUF
|
395 .emit
= upload_wm_constant_surface
,
400 * Sets up a surface state structure to point at the given region.
401 * While it is only used for the front/back buffer currently, it should be
402 * usable for further buffers when doing ARB_draw_buffer support.
405 brw_update_renderbuffer_surface(struct brw_context
*brw
,
406 struct gl_renderbuffer
*rb
,
409 struct intel_context
*intel
= &brw
->intel
;
410 struct gl_context
*ctx
= &intel
->ctx
;
411 drm_intel_bo
*region_bo
= NULL
;
412 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
413 struct intel_region
*region
= irb
? irb
->region
: NULL
;
415 unsigned int surface_type
;
416 unsigned int surface_format
;
417 unsigned int width
, height
, pitch
, cpp
;
418 GLubyte color_mask
[4];
419 GLboolean color_blend
;
424 struct brw_surface_state surf
;
427 memset(&key
, 0, sizeof(key
));
429 if (region
!= NULL
) {
430 region_bo
= region
->buffer
;
432 key
.surface_type
= BRW_SURFACE_2D
;
433 switch (irb
->Base
.Format
) {
434 /* XRGB and ARGB are treated the same here because the chips in this
435 * family cannot render to XRGB targets. This means that we have to
436 * mask writes to alpha (ala glColorMask) and reconfigure the alpha
437 * blending hardware to use GL_ONE (or GL_ZERO) for cases where
438 * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
440 case MESA_FORMAT_ARGB8888
:
441 case MESA_FORMAT_XRGB8888
:
442 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
444 case MESA_FORMAT_SARGB8
:
445 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
;
447 case MESA_FORMAT_RGB565
:
448 key
.surface_format
= BRW_SURFACEFORMAT_B5G6R5_UNORM
;
450 case MESA_FORMAT_ARGB1555
:
451 key
.surface_format
= BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
453 case MESA_FORMAT_ARGB4444
:
454 key
.surface_format
= BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
457 key
.surface_format
= BRW_SURFACEFORMAT_A8_UNORM
;
460 key
.surface_format
= BRW_SURFACEFORMAT_R8_UNORM
;
462 case MESA_FORMAT_R16
:
463 key
.surface_format
= BRW_SURFACEFORMAT_R16_UNORM
;
465 case MESA_FORMAT_RG88
:
466 key
.surface_format
= BRW_SURFACEFORMAT_R8G8_UNORM
;
468 case MESA_FORMAT_RG1616
:
469 key
.surface_format
= BRW_SURFACEFORMAT_R16G16_UNORM
;
472 _mesa_problem(ctx
, "Bad renderbuffer format: %d\n", irb
->Base
.Format
);
474 key
.tiling
= region
->tiling
;
475 key
.width
= rb
->Width
;
476 key
.height
= rb
->Height
;
477 key
.pitch
= region
->pitch
;
478 key
.cpp
= region
->cpp
;
479 key
.draw_x
= region
->draw_x
;
480 key
.draw_y
= region
->draw_y
;
482 key
.surface_type
= BRW_SURFACE_NULL
;
483 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
484 key
.tiling
= I915_TILING_X
;
492 if (intel
->gen
< 6) {
494 memcpy(key
.color_mask
, ctx
->Color
.ColorMask
[unit
],
495 sizeof(key
.color_mask
));
497 /* As mentioned above, disable writes to the alpha component when the
498 * renderbuffer is XRGB.
500 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0)
501 key
.color_mask
[3] = GL_FALSE
;
503 key
.color_blend
= (!ctx
->Color
._LogicOpEnabled
&&
504 (ctx
->Color
.BlendEnabled
& (1 << unit
)));
507 memset(&surf
, 0, sizeof(surf
));
509 surf
.ss0
.surface_format
= key
.surface_format
;
510 surf
.ss0
.surface_type
= key
.surface_type
;
511 if (key
.tiling
== I915_TILING_NONE
) {
512 surf
.ss1
.base_addr
= (key
.draw_x
+ key
.draw_y
* key
.pitch
) * key
.cpp
;
514 uint32_t tile_base
, tile_x
, tile_y
;
515 uint32_t pitch
= key
.pitch
* key
.cpp
;
517 if (key
.tiling
== I915_TILING_X
) {
518 tile_x
= key
.draw_x
% (512 / key
.cpp
);
519 tile_y
= key
.draw_y
% 8;
520 tile_base
= ((key
.draw_y
/ 8) * (8 * pitch
));
521 tile_base
+= (key
.draw_x
- tile_x
) / (512 / key
.cpp
) * 4096;
524 tile_x
= key
.draw_x
% (128 / key
.cpp
);
525 tile_y
= key
.draw_y
% 32;
526 tile_base
= ((key
.draw_y
/ 32) * (32 * pitch
));
527 tile_base
+= (key
.draw_x
- tile_x
) / (128 / key
.cpp
) * 4096;
529 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
530 assert(tile_x
% 4 == 0);
531 assert(tile_y
% 2 == 0);
532 /* Note that the low bits of these fields are missing, so
533 * there's the possibility of getting in trouble.
535 surf
.ss1
.base_addr
= tile_base
;
536 surf
.ss5
.x_offset
= tile_x
/ 4;
537 surf
.ss5
.y_offset
= tile_y
/ 2;
539 if (region_bo
!= NULL
)
540 surf
.ss1
.base_addr
+= region_bo
->offset
; /* reloc */
542 surf
.ss2
.width
= key
.width
- 1;
543 surf
.ss2
.height
= key
.height
- 1;
544 brw_set_surface_tiling(&surf
, key
.tiling
);
545 surf
.ss3
.pitch
= (key
.pitch
* key
.cpp
) - 1;
547 if (intel
->gen
< 6) {
549 surf
.ss0
.color_blend
= key
.color_blend
;
550 surf
.ss0
.writedisable_red
= !key
.color_mask
[0];
551 surf
.ss0
.writedisable_green
= !key
.color_mask
[1];
552 surf
.ss0
.writedisable_blue
= !key
.color_mask
[2];
553 surf
.ss0
.writedisable_alpha
= !key
.color_mask
[3];
556 map
= brw_state_batch(brw
, sizeof(surf
), 32,
557 &brw
->wm
.surf_bo
[unit
],
558 &brw
->wm
.surf_offset
[unit
]);
559 memcpy(map
, &surf
, sizeof(surf
));
561 if (region_bo
!= NULL
) {
562 drm_intel_bo_emit_reloc(brw
->wm
.surf_bo
[unit
],
563 brw
->wm
.surf_offset
[unit
] +
564 offsetof(struct brw_surface_state
, ss1
),
566 surf
.ss1
.base_addr
- region_bo
->offset
,
567 I915_GEM_DOMAIN_RENDER
,
568 I915_GEM_DOMAIN_RENDER
);
573 prepare_wm_surfaces(struct brw_context
*brw
)
575 struct gl_context
*ctx
= &brw
->intel
.ctx
;
579 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
580 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
581 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
582 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
583 struct intel_region
*region
= irb
? irb
->region
: NULL
;
585 brw_add_validated_bo(brw
, region
->buffer
);
586 nr_surfaces
= SURF_INDEX_DRAW(i
) + 1;
590 if (brw
->wm
.const_bo
) {
591 brw_add_validated_bo(brw
, brw
->wm
.const_bo
);
592 nr_surfaces
= SURF_INDEX_FRAG_CONST_BUFFER
+ 1;
595 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
596 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
597 struct gl_texture_object
*tObj
= texUnit
->_Current
;
598 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
600 if (texUnit
->_ReallyEnabled
) {
601 brw_add_validated_bo(brw
, intelObj
->mt
->region
->buffer
);
602 nr_surfaces
= SURF_INDEX_TEXTURE(i
) + 1;
606 /* Have to update this in our prepare, since the unit's prepare
609 if (brw
->wm
.nr_surfaces
!= nr_surfaces
) {
610 brw
->wm
.nr_surfaces
= nr_surfaces
;
611 brw
->state
.dirty
.brw
|= BRW_NEW_NR_WM_SURFACES
;
616 * Constructs the set of surface state objects pointed to by the
620 upload_wm_surfaces(struct brw_context
*brw
)
622 struct gl_context
*ctx
= &brw
->intel
.ctx
;
625 /* _NEW_BUFFERS | _NEW_COLOR */
626 /* Update surfaces for drawing buffers */
627 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
628 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
629 brw_update_renderbuffer_surface(brw
,
630 ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
634 brw_update_renderbuffer_surface(brw
, NULL
, 0);
637 /* Update surfaces for textures */
638 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
639 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
640 const GLuint surf
= SURF_INDEX_TEXTURE(i
);
643 if (texUnit
->_ReallyEnabled
) {
644 brw_update_texture_surface(ctx
, i
);
646 drm_intel_bo_unreference(brw
->wm
.surf_bo
[surf
]);
647 brw
->wm
.surf_bo
[surf
] = NULL
;
651 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
654 const struct brw_tracked_state brw_wm_surfaces
= {
656 .mesa
= (_NEW_COLOR
|
659 .brw
= (BRW_NEW_BATCH
),
662 .prepare
= prepare_wm_surfaces
,
663 .emit
= upload_wm_surfaces
,
667 * Constructs the binding table for the WM surface state, which maps unit
668 * numbers to surface state objects.
671 brw_wm_upload_binding_table(struct brw_context
*brw
)
676 /* Might want to calculate nr_surfaces first, to avoid taking up so much
677 * space for the binding table.
679 bind
= brw_state_batch(brw
, sizeof(uint32_t) * BRW_WM_MAX_SURF
,
680 32, &brw
->wm
.bind_bo
, &brw
->wm
.bind_bo_offset
);
682 for (i
= 0; i
< BRW_WM_MAX_SURF
; i
++) {
683 /* BRW_NEW_WM_SURFACES */
684 bind
[i
] = brw
->wm
.surf_offset
[i
];
685 if (brw
->wm
.surf_bo
[i
]) {
686 bind
[i
] = brw
->wm
.surf_offset
[i
];
692 brw
->state
.dirty
.brw
|= BRW_NEW_BINDING_TABLE
;
695 const struct brw_tracked_state brw_wm_binding_table
= {
698 .brw
= (BRW_NEW_BATCH
|
699 BRW_NEW_WM_SURFACES
),
702 .emit
= brw_wm_upload_binding_table
,