src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45 #include "brw_wm.h"
  46
  47 GLuint
  48 translate_tex_target(GLenum target)
  49 {
  50    switch (target) {
  51    case GL_TEXTURE_1D:
  52    case GL_TEXTURE_1D_ARRAY_EXT:
  53       return BRW_SURFACE_1D;
  54
  55    case GL_TEXTURE_RECTANGLE_NV:
  56       return BRW_SURFACE_2D;
  57
  58    case GL_TEXTURE_2D:
  59    case GL_TEXTURE_2D_ARRAY_EXT:
  60       return BRW_SURFACE_2D;
  61
  62    case GL_TEXTURE_3D:
  63       return BRW_SURFACE_3D;
  64
  65    case GL_TEXTURE_CUBE_MAP:
  66       return BRW_SURFACE_CUBE;
  67
  68    default:
  69       assert(0);
  70       return 0;
  71    }
  72 }
  73
  74 uint32_t
  75 brw_format_for_mesa_format(gl_format mesa_format)
  76 {
  77    static const uint32_t table[MESA_FORMAT_COUNT] =
  78    {
  79       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
  80       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
  81       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
  82       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
  83       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
  84       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
  85       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
  86       [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
  87       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
  88       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
  89       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
  90       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
  91       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
  92       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
  93       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
  94       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
  95       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
  96       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
  97       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
  98       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
  99       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 100       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 101       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 102       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 103       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 104       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 105       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 106       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 107       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 108       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 109       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 110       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 111       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 112       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 113       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 114       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 115       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 116       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 117       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 118       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 119       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 120       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 121       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 122       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 123       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 124       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 125       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 126       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 127    };
 128    assert(mesa_format < MESA_FORMAT_COUNT);
 129    return table[mesa_format];
 130 }
 131
 132 bool
 133 brw_render_target_supported(gl_format format)
 134 {
 135    /* These are not color render targets like the table holds, but we
 136     * ask the question for FBO completeness.
 137     */
 138    if (format == MESA_FORMAT_S8_Z24 ||
 139        format == MESA_FORMAT_X8_Z24 ||
 140        format == MESA_FORMAT_S8 ||
 141        format == MESA_FORMAT_Z16) {
 142       return true;
 143    }
 144
 145    /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
 146     */
 147    if (format == MESA_FORMAT_RGBA_FLOAT32)
 148       return true;
 149
 150    /* Not exactly true, as some of those formats are not renderable.
 151     * But at least we know how to translate them.
 152     */
 153    return brw_format_for_mesa_format(format) != 0;
 154 }
 155
 156 GLuint
 157 translate_tex_format(gl_format mesa_format,
 158                      GLenum internal_format,
 159                      GLenum depth_mode,
 160                      GLenum srgb_decode)
 161 {
 162    switch( mesa_format ) {
 163
 164    case MESA_FORMAT_Z16:
 165       if (depth_mode == GL_INTENSITY)
 166           return BRW_SURFACEFORMAT_I16_UNORM;
 167       else if (depth_mode == GL_ALPHA)
 168           return BRW_SURFACEFORMAT_A16_UNORM;
 169       else if (depth_mode == GL_RED)
 170           return BRW_SURFACEFORMAT_R16_UNORM;
 171       else
 172           return BRW_SURFACEFORMAT_L16_UNORM;
 173
 174    case MESA_FORMAT_S8_Z24:
 175    case MESA_FORMAT_X8_Z24:
 176       /* XXX: these different surface formats don't seem to
 177        * make any difference for shadow sampler/compares.
 178        */
 179       if (depth_mode == GL_INTENSITY)
 180          return BRW_SURFACEFORMAT_I24X8_UNORM;
 181       else if (depth_mode == GL_ALPHA)
 182          return BRW_SURFACEFORMAT_A24X8_UNORM;
 183       else if (depth_mode == GL_RED)
 184          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 185       else
 186          return BRW_SURFACEFORMAT_L24X8_UNORM;
 187
 188    case MESA_FORMAT_SARGB8:
 189    case MESA_FORMAT_SLA8:
 190    case MESA_FORMAT_SL8:
 191       if (srgb_decode == GL_DECODE_EXT)
 192          return brw_format_for_mesa_format(mesa_format);
 193       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 194          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 195
 196    case MESA_FORMAT_RGBA8888_REV:
 197       /* This format is not renderable? */
 198       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 199
 200    case MESA_FORMAT_RGBA_FLOAT32:
 201       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 202        * assertion below.
 203        */
 204       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 205
 206    default:
 207       assert(brw_format_for_mesa_format(mesa_format) != 0);
 208       return brw_format_for_mesa_format(mesa_format);
 209    }
 210 }
 211
 212 static uint32_t
 213 brw_get_surface_tiling_bits(uint32_t tiling)
 214 {
 215    switch (tiling) {
 216    case I915_TILING_X:
 217       return BRW_SURFACE_TILED;
 218    case I915_TILING_Y:
 219       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 220    default:
 221       return 0;
 222    }
 223 }
 224
 225 static void
 226 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 227 {
 228    struct brw_context *brw = brw_context(ctx);
 229    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 230    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 231    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 232    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 233    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 234    uint32_t *surf;
 235    int width, height, depth;
 236
 237    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 238
 239    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 240                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 241
 242    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 243               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 244               BRW_SURFACE_CUBEFACE_ENABLES |
 245               (translate_tex_format(firstImage->TexFormat,
 246                                     firstImage->InternalFormat,
 247                                     sampler->DepthMode,
 248                                     sampler->sRGBDecode) <<
 249                BRW_SURFACE_FORMAT_SHIFT));
 250
 251    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 252
 253    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 254               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 255               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 256
 257    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 258               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 259               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 260               BRW_SURFACE_PITCH_SHIFT);
 261
 262    surf[4] = 0;
 263    surf[5] = 0;
 264
 265    /* Emit relocation to surface contents */
 266    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 267                            brw->wm.surf_offset[surf_index] + 4,
 268                            intelObj->mt->region->bo, 0,
 269                            I915_GEM_DOMAIN_SAMPLER, 0);
 270 }
 271
 272 /**
 273  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 274  * read from this buffer with Data Port Read instructions/messages.
 275  */
 276 void
 277 brw_create_constant_surface(struct brw_context *brw,
 278                             drm_intel_bo *bo,
 279                             int width,
 280                             uint32_t *out_offset)
 281 {
 282    struct intel_context *intel = &brw->intel;
 283    const GLint w = width - 1;
 284    uint32_t *surf;
 285
 286    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 287                           6 * 4, 32, out_offset);
 288
 289    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 290               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 291               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 292
 293    if (intel->gen >= 6)
 294       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 295
 296    surf[1] = bo->offset; /* reloc */
 297
 298    surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
 299               (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 300
 301    surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
 302               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 303
 304    surf[4] = 0;
 305    surf[5] = 0;
 306
 307    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 308     * bspec ("Data Cache") says that the data cache does not exist as
 309     * a separate cache and is just the sampler cache.
 310     */
 311    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 312                            *out_offset + 4,
 313                            bo, 0,
 314                            I915_GEM_DOMAIN_SAMPLER, 0);
 315 }
 316
 317 /* Creates a new WM constant buffer reflecting the current fragment program's
 318  * constants, if needed by the fragment program.
 319  *
 320  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 321  * state atom.
 322  */
 323 static void
 324 prepare_wm_pull_constants(struct brw_context *brw)
 325 {
 326    struct gl_context *ctx = &brw->intel.ctx;
 327    struct intel_context *intel = &brw->intel;
 328    struct brw_fragment_program *fp =
 329       (struct brw_fragment_program *) brw->fragment_program;
 330    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 331    float *constants;
 332    unsigned int i;
 333
 334    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 335
 336    /* BRW_NEW_FRAGMENT_PROGRAM */
 337    if (brw->wm.prog_data->nr_pull_params == 0) {
 338       if (brw->wm.const_bo) {
 339          drm_intel_bo_unreference(brw->wm.const_bo);
 340          brw->wm.const_bo = NULL;
 341          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 342       }
 343       return;
 344    }
 345
 346    drm_intel_bo_unreference(brw->wm.const_bo);
 347    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 348                                          size, 64);
 349
 350    /* _NEW_PROGRAM_CONSTANTS */
 351    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 352    constants = brw->wm.const_bo->virtual;
 353    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 354       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 355                                    brw->wm.prog_data->pull_param[i]);
 356    }
 357    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 358
 359    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 360 }
 361
 362 const struct brw_tracked_state brw_wm_constants = {
 363    .dirty = {
 364       .mesa = (_NEW_PROGRAM_CONSTANTS),
 365       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 366       .cache = 0
 367    },
 368    .prepare = prepare_wm_pull_constants,
 369 };
 370
 371 /**
 372  * Updates surface / buffer for fragment shader constant buffer, if
 373  * one is required.
 374  *
 375  * This consumes the state updates for the constant buffer, and produces
 376  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 377  * inclusion in the binding table.
 378  */
 379 static void upload_wm_constant_surface(struct brw_context *brw )
 380 {
 381    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 382    struct brw_fragment_program *fp =
 383       (struct brw_fragment_program *) brw->fragment_program;
 384    const struct gl_program_parameter_list *params =
 385       fp->program.Base.Parameters;
 386
 387    /* If there's no constant buffer, then no surface BO is needed to point at
 388     * it.
 389     */
 390    if (brw->wm.const_bo == 0) {
 391       if (brw->wm.surf_offset[surf]) {
 392          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 393          brw->wm.surf_offset[surf] = 0;
 394       }
 395       return;
 396    }
 397
 398    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 399                                &brw->wm.surf_offset[surf]);
 400    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 401 }
 402
 403 const struct brw_tracked_state brw_wm_constant_surface = {
 404    .dirty = {
 405       .mesa = 0,
 406       .brw = (BRW_NEW_WM_CONSTBUF |
 407               BRW_NEW_BATCH),
 408       .cache = 0
 409    },
 410    .emit = upload_wm_constant_surface,
 411 };
 412
 413 static void
 414 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 415 {
 416    struct intel_context *intel = &brw->intel;
 417    uint32_t *surf;
 418
 419    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 420                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 421
 422    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 423               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 424    if (intel->gen < 6) {
 425       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 426                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 427                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 428                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 429    }
 430    surf[1] = 0;
 431    surf[2] = 0;
 432    surf[3] = 0;
 433    surf[4] = 0;
 434    surf[5] = 0;
 435 }
 436
 437 /**
 438  * Sets up a surface state structure to point at the given region.
 439  * While it is only used for the front/back buffer currently, it should be
 440  * usable for further buffers when doing ARB_draw_buffer support.
 441  */
 442 static void
 443 brw_update_renderbuffer_surface(struct brw_context *brw,
 444                                 struct gl_renderbuffer *rb,
 445                                 unsigned int unit)
 446 {
 447    struct intel_context *intel = &brw->intel;
 448    struct gl_context *ctx = &intel->ctx;
 449    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 450    struct intel_region *region = irb->region;
 451    uint32_t *surf;
 452    uint32_t tile_x, tile_y;
 453    uint32_t format = 0;
 454
 455    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 456                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 457
 458    switch (irb->Base.Format) {
 459    case MESA_FORMAT_XRGB8888:
 460       /* XRGB is handled as ARGB because the chips in this family
 461        * cannot render to XRGB targets.  This means that we have to
 462        * mask writes to alpha (ala glColorMask) and reconfigure the
 463        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 464        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 465        * used.
 466        */
 467       format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 468       break;
 469    case MESA_FORMAT_INTENSITY_FLOAT32:
 470    case MESA_FORMAT_LUMINANCE_FLOAT32:
 471       /* For these formats, we just need to read/write the first
 472        * channel into R, which is to say that we just treat them as
 473        * GL_RED.
 474        */
 475       format = BRW_SURFACEFORMAT_R32_FLOAT;
 476       break;
 477    case MESA_FORMAT_SARGB8:
 478       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 479          surfaces to the blend/update as sRGB */
 480       if (ctx->Color.sRGBEnabled)
 481          format = brw_format_for_mesa_format(irb->Base.Format);
 482       else
 483          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 484       break;
 485    default:
 486       assert(brw_render_target_supported(irb->Base.Format));
 487       format = brw_format_for_mesa_format(irb->Base.Format);
 488    }
 489
 490    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 491               format << BRW_SURFACE_FORMAT_SHIFT);
 492
 493    /* reloc */
 494    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 495               region->bo->offset);
 496
 497    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 498               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 499
 500    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 501               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 502
 503    surf[4] = 0;
 504
 505    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 506    /* Note that the low bits of these fields are missing, so
 507     * there's the possibility of getting in trouble.
 508     */
 509    assert(tile_x % 4 == 0);
 510    assert(tile_y % 2 == 0);
 511    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 512               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT);
 513
 514    if (intel->gen < 6) {
 515       /* _NEW_COLOR */
 516       if (!ctx->Color.ColorLogicOpEnabled &&
 517           (ctx->Color.BlendEnabled & (1 << unit)))
 518          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 519
 520       if (!ctx->Color.ColorMask[unit][0])
 521          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 522       if (!ctx->Color.ColorMask[unit][1])
 523          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 524       if (!ctx->Color.ColorMask[unit][2])
 525          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 526
 527       /* As mentioned above, disable writes to the alpha component when the
 528        * renderbuffer is XRGB.
 529        */
 530       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 531           !ctx->Color.ColorMask[unit][3]) {
 532          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 533       }
 534    }
 535
 536    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 537                            brw->wm.surf_offset[unit] + 4,
 538                            region->bo,
 539                            surf[1] - region->bo->offset,
 540                            I915_GEM_DOMAIN_RENDER,
 541                            I915_GEM_DOMAIN_RENDER);
 542 }
 543
 544 /**
 545  * Constructs the set of surface state objects pointed to by the
 546  * binding table.
 547  */
 548 static void
 549 brw_upload_wm_surfaces(struct brw_context *brw)
 550 {
 551    struct gl_context *ctx = &brw->intel.ctx;
 552    GLuint i;
 553    int nr_surfaces = 0;
 554
 555    /* _NEW_BUFFERS | _NEW_COLOR */
 556    /* Update surfaces for drawing buffers */
 557    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 558       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 559          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 560             brw_update_renderbuffer_surface(brw,
 561                                             ctx->DrawBuffer->_ColorDrawBuffers[i],
 562                                             i);
 563          } else {
 564             brw_update_null_renderbuffer_surface(brw, i);
 565          }
 566       }
 567       nr_surfaces = SURF_INDEX_DRAW(ctx->DrawBuffer->_NumColorDrawBuffers);
 568    } else {
 569       brw_update_null_renderbuffer_surface(brw, 0);
 570       nr_surfaces = SURF_INDEX_DRAW(0) + 1;
 571    }
 572
 573    /* BRW_NEW_WM_CONSTBUF */
 574    if (brw->wm.const_bo) {
 575       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 576    }
 577
 578    /* Update surfaces for textures */
 579    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 580       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 581       const GLuint surf = SURF_INDEX_TEXTURE(i);
 582
 583       /* _NEW_TEXTURE */
 584       if (texUnit->_ReallyEnabled) {
 585          brw_update_texture_surface(ctx, i);
 586          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 587       } else {
 588          brw->wm.surf_offset[surf] = 0;
 589       }
 590    }
 591
 592    if (brw->wm.nr_surfaces != nr_surfaces) {
 593       brw->wm.nr_surfaces = nr_surfaces;
 594       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 595    }
 596
 597    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 598 }
 599
 600 const struct brw_tracked_state brw_wm_surfaces = {
 601    .dirty = {
 602       .mesa = (_NEW_COLOR |
 603                _NEW_TEXTURE |
 604                _NEW_BUFFERS),
 605       .brw = (BRW_NEW_BATCH |
 606               BRW_NEW_WM_CONSTBUF),
 607       .cache = 0
 608    },
 609    .emit = brw_upload_wm_surfaces,
 610 };
 611
 612 /**
 613  * Constructs the binding table for the WM surface state, which maps unit
 614  * numbers to surface state objects.
 615  */
 616 static void
 617 brw_wm_upload_binding_table(struct brw_context *brw)
 618 {
 619    uint32_t *bind;
 620    int i;
 621
 622    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 623     * space for the binding table.
 624     */
 625    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 626                           sizeof(uint32_t) * BRW_WM_MAX_SURF,
 627                           32, &brw->wm.bind_bo_offset);
 628
 629    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 630       /* BRW_NEW_WM_SURFACES */
 631       bind[i] = brw->wm.surf_offset[i];
 632    }
 633
 634    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 635 }
 636
 637 const struct brw_tracked_state brw_wm_binding_table = {
 638    .dirty = {
 639       .mesa = 0,
 640       .brw = (BRW_NEW_BATCH |
 641               BRW_NEW_WM_SURFACES),
 642       .cache = 0
 643    },
 644    .emit = brw_wm_upload_binding_table,
 645 };