src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "main/texstore.h"
  36 #include "program/prog_parameter.h"
  37
  38 #include "intel_mipmap_tree.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_fbo.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53       return BRW_SURFACE_1D;
  54
  55    case GL_TEXTURE_RECTANGLE_NV:
  56       return BRW_SURFACE_2D;
  57
  58    case GL_TEXTURE_2D:
  59       return BRW_SURFACE_2D;
  60
  61    case GL_TEXTURE_3D:
  62       return BRW_SURFACE_3D;
  63
  64    case GL_TEXTURE_CUBE_MAP:
  65       return BRW_SURFACE_CUBE;
  66
  67    default:
  68       assert(0);
  69       return 0;
  70    }
  71 }
  72
  73 uint32_t
  74 brw_format_for_mesa_format(gl_format mesa_format)
  75 {
  76    static const uint32_t table[MESA_FORMAT_COUNT] =
  77    {
  78       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
  79       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
  80       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
  81       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
  82       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
  83       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
  84       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
  85       [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
  86       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
  87       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
  88       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
  89       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
  90       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
  91       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
  92       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
  93       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
  94       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
  95       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
  96       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
  97       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
  98       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
  99       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 100       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 101       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 102       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 103       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 104       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 105       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 106       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 107       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 108       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 109       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 110       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 111       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 112       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 113       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 114       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 115       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 116       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 117       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 118       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 119       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 120       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 121       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 122       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 123       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 124       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 125       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 126    };
 127    assert(mesa_format < MESA_FORMAT_COUNT);
 128    return table[mesa_format];
 129 }
 130
 131 bool
 132 brw_render_target_supported(gl_format format)
 133 {
 134    /* These are not color render targets like the table holds, but we
 135     * ask the question for FBO completeness.
 136     */
 137    if (format == MESA_FORMAT_S8_Z24 ||
 138        format == MESA_FORMAT_X8_Z24 ||
 139        format == MESA_FORMAT_S8 ||
 140        format == MESA_FORMAT_Z16) {
 141       return true;
 142    }
 143
 144    /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
 145     */
 146    if (format == MESA_FORMAT_RGBA_FLOAT32)
 147       return true;
 148
 149    /* Not exactly true, as some of those formats are not renderable.
 150     * But at least we know how to translate them.
 151     */
 152    return brw_format_for_mesa_format(format) != 0;
 153 }
 154
 155 GLuint
 156 translate_tex_format(gl_format mesa_format,
 157                      GLenum internal_format,
 158                      GLenum depth_mode,
 159                      GLenum srgb_decode)
 160 {
 161    switch( mesa_format ) {
 162
 163    case MESA_FORMAT_Z16:
 164       if (depth_mode == GL_INTENSITY)
 165           return BRW_SURFACEFORMAT_I16_UNORM;
 166       else if (depth_mode == GL_ALPHA)
 167           return BRW_SURFACEFORMAT_A16_UNORM;
 168       else if (depth_mode == GL_RED)
 169           return BRW_SURFACEFORMAT_R16_UNORM;
 170       else
 171           return BRW_SURFACEFORMAT_L16_UNORM;
 172
 173    case MESA_FORMAT_S8_Z24:
 174    case MESA_FORMAT_X8_Z24:
 175       /* XXX: these different surface formats don't seem to
 176        * make any difference for shadow sampler/compares.
 177        */
 178       if (depth_mode == GL_INTENSITY)
 179          return BRW_SURFACEFORMAT_I24X8_UNORM;
 180       else if (depth_mode == GL_ALPHA)
 181          return BRW_SURFACEFORMAT_A24X8_UNORM;
 182       else if (depth_mode == GL_RED)
 183          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 184       else
 185          return BRW_SURFACEFORMAT_L24X8_UNORM;
 186
 187    case MESA_FORMAT_SARGB8:
 188    case MESA_FORMAT_SLA8:
 189    case MESA_FORMAT_SL8:
 190       if (srgb_decode == GL_DECODE_EXT)
 191          return brw_format_for_mesa_format(mesa_format);
 192       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 193          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 194
 195    case MESA_FORMAT_RGBA8888_REV:
 196       /* This format is not renderable? */
 197       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 198
 199    case MESA_FORMAT_RGBA_FLOAT32:
 200       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 201        * assertion below.
 202        */
 203       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 204
 205    default:
 206       assert(brw_format_for_mesa_format(mesa_format) != 0);
 207       return brw_format_for_mesa_format(mesa_format);
 208    }
 209 }
 210
 211 static uint32_t
 212 brw_get_surface_tiling_bits(uint32_t tiling)
 213 {
 214    switch (tiling) {
 215    case I915_TILING_X:
 216       return BRW_SURFACE_TILED;
 217    case I915_TILING_Y:
 218       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 219    default:
 220       return 0;
 221    }
 222 }
 223
 224 static void
 225 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 226 {
 227    struct brw_context *brw = brw_context(ctx);
 228    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 229    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 230    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 231    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 232    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 233    uint32_t *surf;
 234
 235    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 236                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 237
 238    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 239               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 240               BRW_SURFACE_CUBEFACE_ENABLES |
 241               (translate_tex_format(firstImage->TexFormat,
 242                                     firstImage->InternalFormat,
 243                                     sampler->DepthMode,
 244                                     sampler->sRGBDecode) <<
 245                BRW_SURFACE_FORMAT_SHIFT));
 246
 247    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 248
 249    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 250               (firstImage->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 251               (firstImage->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 252
 253    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 254               (firstImage->Depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 255               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 256               BRW_SURFACE_PITCH_SHIFT);
 257
 258    surf[4] = 0;
 259    surf[5] = 0;
 260
 261    /* Emit relocation to surface contents */
 262    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 263                            brw->wm.surf_offset[surf_index] + 4,
 264                            intelObj->mt->region->bo, 0,
 265                            I915_GEM_DOMAIN_SAMPLER, 0);
 266 }
 267
 268 /**
 269  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 270  * read from this buffer with Data Port Read instructions/messages.
 271  */
 272 void
 273 brw_create_constant_surface(struct brw_context *brw,
 274                             drm_intel_bo *bo,
 275                             int width,
 276                             uint32_t *out_offset)
 277 {
 278    struct intel_context *intel = &brw->intel;
 279    const GLint w = width - 1;
 280    uint32_t *surf;
 281
 282    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 283                           6 * 4, 32, out_offset);
 284
 285    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 286               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 287               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 288
 289    if (intel->gen >= 6)
 290       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 291
 292    surf[1] = bo->offset; /* reloc */
 293
 294    surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
 295               (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 296
 297    surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
 298               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 299
 300    surf[4] = 0;
 301    surf[5] = 0;
 302
 303    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 304     * bspec ("Data Cache") says that the data cache does not exist as
 305     * a separate cache and is just the sampler cache.
 306     */
 307    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 308                            *out_offset + 4,
 309                            bo, 0,
 310                            I915_GEM_DOMAIN_SAMPLER, 0);
 311 }
 312
 313 /* Creates a new WM constant buffer reflecting the current fragment program's
 314  * constants, if needed by the fragment program.
 315  *
 316  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 317  * state atom.
 318  */
 319 static void
 320 prepare_wm_pull_constants(struct brw_context *brw)
 321 {
 322    struct gl_context *ctx = &brw->intel.ctx;
 323    struct intel_context *intel = &brw->intel;
 324    struct brw_fragment_program *fp =
 325       (struct brw_fragment_program *) brw->fragment_program;
 326    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 327    float *constants;
 328    unsigned int i;
 329
 330    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 331
 332    /* BRW_NEW_FRAGMENT_PROGRAM */
 333    if (brw->wm.prog_data->nr_pull_params == 0) {
 334       if (brw->wm.const_bo) {
 335          drm_intel_bo_unreference(brw->wm.const_bo);
 336          brw->wm.const_bo = NULL;
 337          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 338       }
 339       return;
 340    }
 341
 342    drm_intel_bo_unreference(brw->wm.const_bo);
 343    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 344                                          size, 64);
 345
 346    /* _NEW_PROGRAM_CONSTANTS */
 347    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 348    constants = brw->wm.const_bo->virtual;
 349    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 350       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 351                                    brw->wm.prog_data->pull_param[i]);
 352    }
 353    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 354
 355    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 356 }
 357
 358 const struct brw_tracked_state brw_wm_constants = {
 359    .dirty = {
 360       .mesa = (_NEW_PROGRAM_CONSTANTS),
 361       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 362       .cache = 0
 363    },
 364    .prepare = prepare_wm_pull_constants,
 365 };
 366
 367 /**
 368  * Updates surface / buffer for fragment shader constant buffer, if
 369  * one is required.
 370  *
 371  * This consumes the state updates for the constant buffer, and produces
 372  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 373  * inclusion in the binding table.
 374  */
 375 static void upload_wm_constant_surface(struct brw_context *brw )
 376 {
 377    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 378    struct brw_fragment_program *fp =
 379       (struct brw_fragment_program *) brw->fragment_program;
 380    const struct gl_program_parameter_list *params =
 381       fp->program.Base.Parameters;
 382
 383    /* If there's no constant buffer, then no surface BO is needed to point at
 384     * it.
 385     */
 386    if (brw->wm.const_bo == 0) {
 387       if (brw->wm.surf_offset[surf]) {
 388          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 389          brw->wm.surf_offset[surf] = 0;
 390       }
 391       return;
 392    }
 393
 394    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 395                                &brw->wm.surf_offset[surf]);
 396    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 397 }
 398
 399 const struct brw_tracked_state brw_wm_constant_surface = {
 400    .dirty = {
 401       .mesa = 0,
 402       .brw = (BRW_NEW_WM_CONSTBUF |
 403               BRW_NEW_BATCH),
 404       .cache = 0
 405    },
 406    .emit = upload_wm_constant_surface,
 407 };
 408
 409 static void
 410 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 411 {
 412    struct intel_context *intel = &brw->intel;
 413    uint32_t *surf;
 414
 415    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 416                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 417
 418    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 419               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 420    if (intel->gen < 6) {
 421       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 422                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 423                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 424                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 425    }
 426    surf[1] = 0;
 427    surf[2] = 0;
 428    surf[3] = 0;
 429    surf[4] = 0;
 430    surf[5] = 0;
 431 }
 432
 433 /**
 434  * Sets up a surface state structure to point at the given region.
 435  * While it is only used for the front/back buffer currently, it should be
 436  * usable for further buffers when doing ARB_draw_buffer support.
 437  */
 438 static void
 439 brw_update_renderbuffer_surface(struct brw_context *brw,
 440                                 struct gl_renderbuffer *rb,
 441                                 unsigned int unit)
 442 {
 443    struct intel_context *intel = &brw->intel;
 444    struct gl_context *ctx = &intel->ctx;
 445    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 446    struct intel_region *region = irb->region;
 447    uint32_t *surf;
 448    uint32_t tile_x, tile_y;
 449    uint32_t format = 0;
 450
 451    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 452                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 453
 454    switch (irb->Base.Format) {
 455    case MESA_FORMAT_XRGB8888:
 456       /* XRGB is handled as ARGB because the chips in this family
 457        * cannot render to XRGB targets.  This means that we have to
 458        * mask writes to alpha (ala glColorMask) and reconfigure the
 459        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 460        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 461        * used.
 462        */
 463       format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 464       break;
 465    case MESA_FORMAT_INTENSITY_FLOAT32:
 466    case MESA_FORMAT_LUMINANCE_FLOAT32:
 467       /* For these formats, we just need to read/write the first
 468        * channel into R, which is to say that we just treat them as
 469        * GL_RED.
 470        */
 471       format = BRW_SURFACEFORMAT_R32_FLOAT;
 472       break;
 473    case MESA_FORMAT_SARGB8:
 474       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 475          surfaces to the blend/update as sRGB */
 476       if (ctx->Color.sRGBEnabled)
 477          format = brw_format_for_mesa_format(irb->Base.Format);
 478       else
 479          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 480       break;
 481    default:
 482       assert(brw_render_target_supported(irb->Base.Format));
 483       format = brw_format_for_mesa_format(irb->Base.Format);
 484    }
 485
 486    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 487               format << BRW_SURFACE_FORMAT_SHIFT);
 488
 489    /* reloc */
 490    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 491               region->bo->offset);
 492
 493    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 494               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 495
 496    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 497               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 498
 499    surf[4] = 0;
 500
 501    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 502    /* Note that the low bits of these fields are missing, so
 503     * there's the possibility of getting in trouble.
 504     */
 505    assert(tile_x % 4 == 0);
 506    assert(tile_y % 2 == 0);
 507    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 508               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT);
 509
 510    if (intel->gen < 6) {
 511       /* _NEW_COLOR */
 512       if (!ctx->Color.ColorLogicOpEnabled &&
 513           (ctx->Color.BlendEnabled & (1 << unit)))
 514          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 515
 516       if (!ctx->Color.ColorMask[unit][0])
 517          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 518       if (!ctx->Color.ColorMask[unit][1])
 519          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 520       if (!ctx->Color.ColorMask[unit][2])
 521          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 522
 523       /* As mentioned above, disable writes to the alpha component when the
 524        * renderbuffer is XRGB.
 525        */
 526       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 527           !ctx->Color.ColorMask[unit][3]) {
 528          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 529       }
 530    }
 531
 532    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 533                            brw->wm.surf_offset[unit] + 4,
 534                            region->bo,
 535                            surf[1] - region->bo->offset,
 536                            I915_GEM_DOMAIN_RENDER,
 537                            I915_GEM_DOMAIN_RENDER);
 538 }
 539
 540 static void
 541 prepare_wm_surfaces(struct brw_context *brw)
 542 {
 543    struct gl_context *ctx = &brw->intel.ctx;
 544    int i;
 545    int nr_surfaces = 0;
 546
 547    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 548       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 549       struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 550       struct intel_region *region = irb ? irb->region : NULL;
 551
 552       if (region)
 553          brw_add_validated_bo(brw, region->bo);
 554       nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 555    }
 556
 557    if (brw->wm.const_bo) {
 558       brw_add_validated_bo(brw, brw->wm.const_bo);
 559       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 560    }
 561
 562    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 563       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 564
 565       if (texUnit->_ReallyEnabled) {
 566          struct gl_texture_object *tObj = texUnit->_Current;
 567          struct intel_texture_object *intelObj = intel_texture_object(tObj);
 568
 569          brw_add_validated_bo(brw, intelObj->mt->region->bo);
 570          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 571       }
 572    }
 573
 574    /* Have to update this in our prepare, since the unit's prepare
 575     * relies on it.
 576     */
 577    if (brw->wm.nr_surfaces != nr_surfaces) {
 578       brw->wm.nr_surfaces = nr_surfaces;
 579       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 580    }
 581 }
 582
 583 /**
 584  * Constructs the set of surface state objects pointed to by the
 585  * binding table.
 586  */
 587 static void
 588 upload_wm_surfaces(struct brw_context *brw)
 589 {
 590    struct gl_context *ctx = &brw->intel.ctx;
 591    GLuint i;
 592
 593    /* _NEW_BUFFERS | _NEW_COLOR */
 594    /* Update surfaces for drawing buffers */
 595    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 596       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 597          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 598             brw_update_renderbuffer_surface(brw,
 599                                             ctx->DrawBuffer->_ColorDrawBuffers[i],
 600                                             i);
 601          } else {
 602             brw_update_null_renderbuffer_surface(brw, i);
 603          }
 604       }
 605    } else {
 606       brw_update_null_renderbuffer_surface(brw, 0);
 607    }
 608
 609    /* Update surfaces for textures */
 610    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 611       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 612       const GLuint surf = SURF_INDEX_TEXTURE(i);
 613
 614       /* _NEW_TEXTURE */
 615       if (texUnit->_ReallyEnabled) {
 616          brw_update_texture_surface(ctx, i);
 617       } else {
 618          brw->wm.surf_offset[surf] = 0;
 619       }
 620    }
 621
 622    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 623 }
 624
 625 const struct brw_tracked_state brw_wm_surfaces = {
 626    .dirty = {
 627       .mesa = (_NEW_COLOR |
 628                _NEW_TEXTURE |
 629                _NEW_BUFFERS),
 630       .brw = (BRW_NEW_BATCH),
 631       .cache = 0
 632    },
 633    .prepare = prepare_wm_surfaces,
 634    .emit = upload_wm_surfaces,
 635 };
 636
 637 /**
 638  * Constructs the binding table for the WM surface state, which maps unit
 639  * numbers to surface state objects.
 640  */
 641 static void
 642 brw_wm_upload_binding_table(struct brw_context *brw)
 643 {
 644    uint32_t *bind;
 645    int i;
 646
 647    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 648     * space for the binding table.
 649     */
 650    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 651                           sizeof(uint32_t) * BRW_WM_MAX_SURF,
 652                           32, &brw->wm.bind_bo_offset);
 653
 654    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 655       /* BRW_NEW_WM_SURFACES */
 656       bind[i] = brw->wm.surf_offset[i];
 657    }
 658
 659    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 660 }
 661
 662 const struct brw_tracked_state brw_wm_binding_table = {
 663    .dirty = {
 664       .mesa = 0,
 665       .brw = (BRW_NEW_BATCH |
 666               BRW_NEW_WM_SURFACES),
 667       .cache = 0
 668    },
 669    .emit = brw_wm_upload_binding_table,
 670 };