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i965: Refactor texture swizzle generation into a helper.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
36
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
41 #include "intel_buffer_objects.h"
42
43 #include "brw_context.h"
44 #include "brw_state.h"
45 #include "brw_defines.h"
46 #include "brw_wm.h"
47
48 GLuint
49 translate_tex_target(GLenum target)
50 {
51 switch (target) {
52 case GL_TEXTURE_1D:
53 case GL_TEXTURE_1D_ARRAY_EXT:
54 return BRW_SURFACE_1D;
55
56 case GL_TEXTURE_RECTANGLE_NV:
57 return BRW_SURFACE_2D;
58
59 case GL_TEXTURE_2D:
60 case GL_TEXTURE_2D_ARRAY_EXT:
61 case GL_TEXTURE_EXTERNAL_OES:
62 return BRW_SURFACE_2D;
63
64 case GL_TEXTURE_3D:
65 return BRW_SURFACE_3D;
66
67 case GL_TEXTURE_CUBE_MAP:
68 return BRW_SURFACE_CUBE;
69
70 default:
71 assert(0);
72 return 0;
73 }
74 }
75
76 struct surface_format_info {
77 bool exists;
78 int sampling;
79 int filtering;
80 int shadow_compare;
81 int chroma_key;
82 int render_target;
83 int alpha_blend;
84 int input_vb;
85 int streamed_output_vb;
86 int color_processing;
87 };
88
89 /* This macro allows us to write the table almost as it appears in the PRM,
90 * while restructuring it to turn it into the C code we want.
91 */
92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
93 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
94
95 #define Y 0
96 #define x 999
97 /**
98 * This is the table of support for surface (texture, renderbuffer, and vertex
99 * buffer, but not depthbuffer) formats across the various hardware generations.
100 *
101 * The table is formatted to match the documentation, except that the docs have
102 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
103 * it in our table, here's the mapping:
104 *
105 * Y*: 45
106 * Y+: 45 (g45/gm45)
107 * Y~: 50 (gen5)
108 * Y^: 60 (gen6)
109 * Y#: 70 (gen7)
110 *
111 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
112 */
113 const struct surface_format_info surface_formats[] = {
114 /* smpl filt shad CK RT AB VB SO color */
115 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
116 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
117 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
119 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
120 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
121 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
122 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
123 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
124 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
125 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
126 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
129 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
130 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
131 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
132 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
133 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
134 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
135 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
136 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
137 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
138 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
139 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
140 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
141 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
144 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
145 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
146 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
148 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
149 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
152 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
153 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
154 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
155 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
156 /* smpl filt shad CK RT AB VB SO color */
157 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
158 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
159 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
160 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
161 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
162 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
163 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
164 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
165 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
166 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
167 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
168 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
169 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
170 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
171 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
172 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
173 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
174 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
175 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
176 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
177 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
178 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
179 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
184 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
185 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
186 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
191 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
192 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
193 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
194 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
195 /* smpl filt shad CK RT AB VB SO color */
196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
201 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
202 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
203 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
204 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
205 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
206 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
207 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
208 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
209 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
210 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
211 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
212 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
213 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
214 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
215 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
216 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
217 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
219 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
220 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
221 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
223 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
224 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
225 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
226 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
227 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
228 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
229 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
231 /* smpl filt shad CK RT AB VB SO color */
232 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
233 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
234 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
235 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
236 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
237 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
238 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
239 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
240 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
241 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
242 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
243 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
244 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
245 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
246 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
247 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
248 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
249 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
251 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
252 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
256 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
257 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
258 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
259 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
260 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
261 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
262 /* smpl filt shad CK RT AB VB SO color */
263 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
268 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
269 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
271 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
274 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
275 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
276 };
277 #undef x
278 #undef Y
279
280 uint32_t
281 brw_format_for_mesa_format(gl_format mesa_format)
282 {
283 /* This table is ordered according to the enum ordering in formats.h. We do
284 * expect that enum to be extended without our explicit initialization
285 * staying in sync, so we initialize to 0 even though
286 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
287 */
288 static const uint32_t table[MESA_FORMAT_COUNT] =
289 {
290 [MESA_FORMAT_RGBA8888] = 0,
291 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
292 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
293 [MESA_FORMAT_ARGB8888_REV] = 0,
294 [MESA_FORMAT_RGBX8888] = 0,
295 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
296 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
297 [MESA_FORMAT_XRGB8888_REV] = 0,
298 [MESA_FORMAT_RGB888] = 0,
299 [MESA_FORMAT_BGR888] = 0,
300 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
301 [MESA_FORMAT_RGB565_REV] = 0,
302 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
303 [MESA_FORMAT_ARGB4444_REV] = 0,
304 [MESA_FORMAT_RGBA5551] = 0,
305 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
306 [MESA_FORMAT_ARGB1555_REV] = 0,
307 [MESA_FORMAT_AL44] = 0,
308 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
309 [MESA_FORMAT_AL88_REV] = 0,
310 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
311 [MESA_FORMAT_AL1616_REV] = 0,
312 [MESA_FORMAT_RGB332] = 0,
313 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
314 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
315 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
316 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
317 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
318 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
319 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
320 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
321 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
322 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
323 [MESA_FORMAT_RG88] = 0,
324 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
325 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
326 [MESA_FORMAT_RG1616_REV] = 0,
327 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
328 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
329 [MESA_FORMAT_Z24_S8] = 0,
330 [MESA_FORMAT_S8_Z24] = 0,
331 [MESA_FORMAT_Z16] = 0,
332 [MESA_FORMAT_X8_Z24] = 0,
333 [MESA_FORMAT_Z24_X8] = 0,
334 [MESA_FORMAT_Z32] = 0,
335 [MESA_FORMAT_S8] = 0,
336
337 [MESA_FORMAT_SRGB8] = 0,
338 [MESA_FORMAT_SRGBA8] = 0,
339 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
340 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
341 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
342 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
343 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
344 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
345 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
346
347 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
348 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
349 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
350 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
351 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
352 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
353
354 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
355 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
356 [MESA_FORMAT_RGB_FLOAT32] = 0,
357 [MESA_FORMAT_RGB_FLOAT16] = 0,
358 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
359 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
360 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
361 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
362 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
363 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
364 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
365 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
366 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
367 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
368 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
369 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
370
371 [MESA_FORMAT_ALPHA_UINT8] = 0,
372 [MESA_FORMAT_ALPHA_UINT16] = 0,
373 [MESA_FORMAT_ALPHA_UINT32] = 0,
374 [MESA_FORMAT_ALPHA_INT8] = 0,
375 [MESA_FORMAT_ALPHA_INT16] = 0,
376 [MESA_FORMAT_ALPHA_INT32] = 0,
377
378 [MESA_FORMAT_INTENSITY_UINT8] = 0,
379 [MESA_FORMAT_INTENSITY_UINT16] = 0,
380 [MESA_FORMAT_INTENSITY_UINT32] = 0,
381 [MESA_FORMAT_INTENSITY_INT8] = 0,
382 [MESA_FORMAT_INTENSITY_INT16] = 0,
383 [MESA_FORMAT_INTENSITY_INT32] = 0,
384
385 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
386 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
387 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
388 [MESA_FORMAT_LUMINANCE_INT8] = 0,
389 [MESA_FORMAT_LUMINANCE_INT16] = 0,
390 [MESA_FORMAT_LUMINANCE_INT32] = 0,
391
392 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
393 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
394 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
395 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
396 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
397 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
398
399 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
400 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
401 [MESA_FORMAT_RGB_INT8] = 0,
402 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
403 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
404 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
405 [MESA_FORMAT_RGB_INT16] = 0,
406 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
407 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
408 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
409 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
410 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
411
412 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
413 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
414 [MESA_FORMAT_RGB_UINT8] = 0,
415 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
416 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
417 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
418 [MESA_FORMAT_RGB_UINT16] = 0,
419 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
420 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
421 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
422 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
423 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
424
425 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
426 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
427 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
428 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
429 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
430 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
431 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
432 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
433 [MESA_FORMAT_SIGNED_RGB_16] = 0,
434 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
435 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
436
437 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
438 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
439 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
440 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
441
442 [MESA_FORMAT_L_LATC1] = 0,
443 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
444 [MESA_FORMAT_LA_LATC2] = 0,
445 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
446
447 [MESA_FORMAT_SIGNED_A8] = 0,
448 [MESA_FORMAT_SIGNED_L8] = 0,
449 [MESA_FORMAT_SIGNED_AL88] = 0,
450 [MESA_FORMAT_SIGNED_I8] = 0,
451 [MESA_FORMAT_SIGNED_A16] = 0,
452 [MESA_FORMAT_SIGNED_L16] = 0,
453 [MESA_FORMAT_SIGNED_AL1616] = 0,
454 [MESA_FORMAT_SIGNED_I16] = 0,
455
456 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
457 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
458
459 [MESA_FORMAT_Z32_FLOAT] = 0,
460 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
461 };
462 assert(mesa_format < MESA_FORMAT_COUNT);
463 return table[mesa_format];
464 }
465
466 void
467 brw_init_surface_formats(struct brw_context *brw)
468 {
469 struct intel_context *intel = &brw->intel;
470 struct gl_context *ctx = &intel->ctx;
471 int gen;
472 gl_format format;
473
474 gen = intel->gen * 10;
475 if (intel->is_g4x)
476 gen += 5;
477
478 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
479 uint32_t texture, render;
480 const struct surface_format_info *rinfo, *tinfo;
481 bool is_integer = _mesa_is_format_integer_color(format);
482
483 render = texture = brw_format_for_mesa_format(format);
484 tinfo = &surface_formats[texture];
485
486 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
487 * it.
488 */
489 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
490 continue;
491
492 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
493 ctx->TextureFormatSupported[format] = true;
494
495 /* Re-map some render target formats to make them supported when they
496 * wouldn't be using their format for texturing.
497 */
498 switch (render) {
499 /* For these formats, we just need to read/write the first
500 * channel into R, which is to say that we just treat them as
501 * GL_RED.
502 */
503 case BRW_SURFACEFORMAT_I32_FLOAT:
504 case BRW_SURFACEFORMAT_L32_FLOAT:
505 render = BRW_SURFACEFORMAT_R32_FLOAT;
506 break;
507 case BRW_SURFACEFORMAT_I16_FLOAT:
508 case BRW_SURFACEFORMAT_L16_FLOAT:
509 render = BRW_SURFACEFORMAT_R16_FLOAT;
510 break;
511 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
512 /* XRGB is handled as ARGB because the chips in this family
513 * cannot render to XRGB targets. This means that we have to
514 * mask writes to alpha (ala glColorMask) and reconfigure the
515 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
516 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
517 * used.
518 */
519 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
520 break;
521 }
522
523 rinfo = &surface_formats[render];
524
525 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
526 * integer, so we don't need hardware support for blending on it. Other
527 * than that, GL in general requires alpha blending for render targets,
528 * even though we don't support it for some formats.
529 */
530 if (gen >= rinfo->render_target &&
531 (gen >= rinfo->alpha_blend || is_integer)) {
532 brw->render_target_format[format] = render;
533 brw->format_supported_as_render_target[format] = true;
534 }
535 }
536
537 /* We will check this table for FBO completeness, but the surface format
538 * table above only covered color rendering.
539 */
540 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
541 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
542 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
543 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
544 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
545 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
546
547 /* We remap depth formats to a supported texturing format in
548 * translate_tex_format().
549 */
550 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
551 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
552 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
553 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
554 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
555
556 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
557 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
558 */
559 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
560 }
561
562 bool
563 brw_render_target_supported(struct intel_context *intel,
564 struct gl_renderbuffer *rb)
565 {
566 struct brw_context *brw = brw_context(&intel->ctx);
567 gl_format format = rb->Format;
568
569 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
570 * we would consider them renderable even though we don't have surface
571 * support for their alpha behavior and don't have the blending unit
572 * available to fake it like we do for XRGB8888. Force them to being
573 * unsupported.
574 */
575 if ((rb->_BaseFormat != GL_RGBA &&
576 rb->_BaseFormat != GL_RG &&
577 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
578 return false;
579
580 /* Under some conditions, MSAA is not supported for formats whose width is
581 * more than 64 bits.
582 */
583 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
584 /* Gen6: MSAA on >64 bit formats is unsupported. */
585 if (intel->gen <= 6)
586 return false;
587
588 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
589 if (rb->NumSamples >= 8)
590 return false;
591 }
592
593 return brw->format_supported_as_render_target[format];
594 }
595
596 GLuint
597 translate_tex_format(gl_format mesa_format,
598 GLenum internal_format,
599 GLenum depth_mode,
600 GLenum srgb_decode)
601 {
602 if (srgb_decode == GL_SKIP_DECODE_EXT)
603 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
604
605 switch( mesa_format ) {
606
607 case MESA_FORMAT_Z16:
608 return BRW_SURFACEFORMAT_I16_UNORM;
609
610 case MESA_FORMAT_S8_Z24:
611 case MESA_FORMAT_X8_Z24:
612 return BRW_SURFACEFORMAT_I24X8_UNORM;
613
614 case MESA_FORMAT_Z32_FLOAT:
615 return BRW_SURFACEFORMAT_I32_FLOAT;
616
617 case MESA_FORMAT_Z32_FLOAT_X24S8:
618 return BRW_SURFACEFORMAT_R32G32_FLOAT;
619
620 case MESA_FORMAT_RGBA_FLOAT32:
621 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
622 * assertion below.
623 */
624 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
625
626 default:
627 assert(brw_format_for_mesa_format(mesa_format) != 0);
628 return brw_format_for_mesa_format(mesa_format);
629 }
630 }
631
632 uint32_t
633 brw_get_surface_tiling_bits(uint32_t tiling)
634 {
635 switch (tiling) {
636 case I915_TILING_X:
637 return BRW_SURFACE_TILED;
638 case I915_TILING_Y:
639 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
640 default:
641 return 0;
642 }
643 }
644
645
646 uint32_t
647 brw_get_surface_num_multisamples(unsigned num_samples)
648 {
649 if (num_samples > 1)
650 return BRW_SURFACE_MULTISAMPLECOUNT_4;
651 else
652 return BRW_SURFACE_MULTISAMPLECOUNT_1;
653 }
654
655
656 /**
657 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
658 * swizzling.
659 */
660 int
661 brw_get_texture_swizzle(const struct gl_texture_object *t)
662 {
663 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
664
665 int swizzles[SWIZZLE_NIL + 1] = {
666 SWIZZLE_X,
667 SWIZZLE_Y,
668 SWIZZLE_Z,
669 SWIZZLE_W,
670 SWIZZLE_ZERO,
671 SWIZZLE_ONE,
672 SWIZZLE_NIL
673 };
674
675 if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
676 img->_BaseFormat == GL_DEPTH_STENCIL) {
677 switch (t->DepthMode) {
678 case GL_ALPHA:
679 swizzles[0] = SWIZZLE_ZERO;
680 swizzles[1] = SWIZZLE_ZERO;
681 swizzles[2] = SWIZZLE_ZERO;
682 swizzles[3] = SWIZZLE_X;
683 break;
684 case GL_LUMINANCE:
685 swizzles[0] = SWIZZLE_X;
686 swizzles[1] = SWIZZLE_X;
687 swizzles[2] = SWIZZLE_X;
688 swizzles[3] = SWIZZLE_ONE;
689 break;
690 case GL_INTENSITY:
691 swizzles[0] = SWIZZLE_X;
692 swizzles[1] = SWIZZLE_X;
693 swizzles[2] = SWIZZLE_X;
694 swizzles[3] = SWIZZLE_X;
695 break;
696 case GL_RED:
697 swizzles[0] = SWIZZLE_X;
698 swizzles[1] = SWIZZLE_ZERO;
699 swizzles[2] = SWIZZLE_ZERO;
700 swizzles[3] = SWIZZLE_ONE;
701 break;
702 }
703 }
704
705 return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
706 swizzles[GET_SWZ(t->_Swizzle, 1)],
707 swizzles[GET_SWZ(t->_Swizzle, 2)],
708 swizzles[GET_SWZ(t->_Swizzle, 3)]);
709 }
710
711
712 static void
713 brw_update_buffer_texture_surface(struct gl_context *ctx,
714 unsigned unit,
715 uint32_t *binding_table,
716 unsigned surf_index)
717 {
718 struct brw_context *brw = brw_context(ctx);
719 struct intel_context *intel = &brw->intel;
720 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
721 uint32_t *surf;
722 struct intel_buffer_object *intel_obj =
723 intel_buffer_object(tObj->BufferObject);
724 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
725 gl_format format = tObj->_BufferObjectFormat;
726 uint32_t brw_format = brw_format_for_mesa_format(format);
727 int texel_size = _mesa_get_format_bytes(format);
728
729 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
730 _mesa_problem(NULL, "bad format %s for texture buffer\n",
731 _mesa_get_format_name(format));
732 }
733
734 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
735 6 * 4, 32, &binding_table[surf_index]);
736
737 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
738 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
739
740 if (intel->gen >= 6)
741 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
742
743 if (bo) {
744 surf[1] = bo->offset; /* reloc */
745
746 /* Emit relocation to surface contents. */
747 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
748 binding_table[surf_index] + 4,
749 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
750
751 int w = intel_obj->Base.Size / texel_size;
752 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
753 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
754 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
755 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
756 } else {
757 surf[1] = 0;
758 surf[2] = 0;
759 surf[3] = 0;
760 }
761
762 surf[4] = 0;
763 surf[5] = 0;
764 }
765
766 static void
767 brw_update_texture_surface(struct gl_context *ctx,
768 unsigned unit,
769 uint32_t *binding_table,
770 unsigned surf_index)
771 {
772 struct brw_context *brw = brw_context(ctx);
773 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
774 struct intel_texture_object *intelObj = intel_texture_object(tObj);
775 struct intel_mipmap_tree *mt = intelObj->mt;
776 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
777 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
778 uint32_t *surf;
779 int width, height, depth;
780
781 if (tObj->Target == GL_TEXTURE_BUFFER) {
782 brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
783 return;
784 }
785
786 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
787
788 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
789 6 * 4, 32, &binding_table[surf_index]);
790
791 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
792 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
793 BRW_SURFACE_CUBEFACE_ENABLES |
794 (translate_tex_format(mt->format,
795 firstImage->InternalFormat,
796 tObj->DepthMode,
797 sampler->sRGBDecode) <<
798 BRW_SURFACE_FORMAT_SHIFT));
799
800 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
801
802 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
803 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
804 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
805
806 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
807 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
808 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
809 BRW_SURFACE_PITCH_SHIFT);
810
811 surf[4] = 0;
812
813 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
814
815 /* Emit relocation to surface contents */
816 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
817 binding_table[surf_index] + 4,
818 intelObj->mt->region->bo,
819 intelObj->mt->offset,
820 I915_GEM_DOMAIN_SAMPLER, 0);
821 }
822
823 /**
824 * Create the constant buffer surface. Vertex/fragment shader constants will be
825 * read from this buffer with Data Port Read instructions/messages.
826 */
827 void
828 brw_create_constant_surface(struct brw_context *brw,
829 drm_intel_bo *bo,
830 uint32_t offset,
831 int width,
832 uint32_t *out_offset)
833 {
834 struct intel_context *intel = &brw->intel;
835 const GLint w = width - 1;
836 uint32_t *surf;
837
838 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
839 6 * 4, 32, out_offset);
840
841 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
842 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
843 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
844
845 if (intel->gen >= 6)
846 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
847
848 surf[1] = bo->offset + offset; /* reloc */
849
850 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
851 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
852
853 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
854 (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
855
856 surf[4] = 0;
857 surf[5] = 0;
858
859 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
860 * bspec ("Data Cache") says that the data cache does not exist as
861 * a separate cache and is just the sampler cache.
862 */
863 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
864 *out_offset + 4,
865 bo, offset,
866 I915_GEM_DOMAIN_SAMPLER, 0);
867 }
868
869 /**
870 * Set up a binding table entry for use by stream output logic (transform
871 * feedback).
872 *
873 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
874 */
875 void
876 brw_update_sol_surface(struct brw_context *brw,
877 struct gl_buffer_object *buffer_obj,
878 uint32_t *out_offset, unsigned num_vector_components,
879 unsigned stride_dwords, unsigned offset_dwords)
880 {
881 struct intel_context *intel = &brw->intel;
882 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
883 drm_intel_bo *bo =
884 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
885 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
886 out_offset);
887 uint32_t pitch_minus_1 = 4*stride_dwords - 1;
888 uint32_t offset_bytes = 4 * offset_dwords;
889 size_t size_dwords = buffer_obj->Size / 4;
890 uint32_t buffer_size_minus_1, width, height, depth, surface_format;
891
892 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
893 * too big to map using a single binding table entry?
894 */
895 assert((size_dwords - offset_dwords) / stride_dwords
896 <= BRW_MAX_NUM_BUFFER_ENTRIES);
897
898 if (size_dwords > offset_dwords + num_vector_components) {
899 /* There is room for at least 1 transform feedback output in the buffer.
900 * Compute the number of additional transform feedback outputs the
901 * buffer has room for.
902 */
903 buffer_size_minus_1 =
904 (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
905 } else {
906 /* There isn't even room for a single transform feedback output in the
907 * buffer. We can't configure the binding table entry to prevent output
908 * entirely; we'll have to rely on the geometry shader to detect
909 * overflow. But to minimize the damage in case of a bug, set up the
910 * binding table entry to just allow a single output.
911 */
912 buffer_size_minus_1 = 0;
913 }
914 width = buffer_size_minus_1 & 0x7f;
915 height = (buffer_size_minus_1 & 0xfff80) >> 7;
916 depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
917
918 switch (num_vector_components) {
919 case 1:
920 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
921 break;
922 case 2:
923 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
924 break;
925 case 3:
926 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
927 break;
928 case 4:
929 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
930 break;
931 default:
932 assert(!"Invalid vector size for transform feedback output");
933 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
934 break;
935 }
936
937 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
938 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
939 surface_format << BRW_SURFACE_FORMAT_SHIFT |
940 BRW_SURFACE_RC_READ_WRITE;
941 surf[1] = bo->offset + offset_bytes; /* reloc */
942 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
943 height << BRW_SURFACE_HEIGHT_SHIFT);
944 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
945 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
946 surf[4] = 0;
947 surf[5] = 0;
948
949 /* Emit relocation to surface contents. */
950 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
951 *out_offset + 4,
952 bo, offset_bytes,
953 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
954 }
955
956 /* Creates a new WM constant buffer reflecting the current fragment program's
957 * constants, if needed by the fragment program.
958 *
959 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
960 * state atom.
961 */
962 static void
963 brw_upload_wm_pull_constants(struct brw_context *brw)
964 {
965 struct gl_context *ctx = &brw->intel.ctx;
966 struct intel_context *intel = &brw->intel;
967 /* BRW_NEW_FRAGMENT_PROGRAM */
968 struct brw_fragment_program *fp =
969 (struct brw_fragment_program *) brw->fragment_program;
970 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
971 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
972 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
973 float *constants;
974 unsigned int i;
975
976 _mesa_load_state_parameters(ctx, params);
977
978 /* CACHE_NEW_WM_PROG */
979 if (brw->wm.prog_data->nr_pull_params == 0) {
980 if (brw->wm.const_bo) {
981 drm_intel_bo_unreference(brw->wm.const_bo);
982 brw->wm.const_bo = NULL;
983 brw->wm.surf_offset[surf_index] = 0;
984 brw->state.dirty.brw |= BRW_NEW_SURFACES;
985 }
986 return;
987 }
988
989 drm_intel_bo_unreference(brw->wm.const_bo);
990 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
991 size, 64);
992
993 /* _NEW_PROGRAM_CONSTANTS */
994 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
995 constants = brw->wm.const_bo->virtual;
996 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
997 constants[i] = *brw->wm.prog_data->pull_param[i];
998 }
999 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1000
1001 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1002 params->NumParameters,
1003 &brw->wm.surf_offset[surf_index]);
1004
1005 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1006 }
1007
1008 const struct brw_tracked_state brw_wm_pull_constants = {
1009 .dirty = {
1010 .mesa = (_NEW_PROGRAM_CONSTANTS),
1011 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1012 .cache = CACHE_NEW_WM_PROG,
1013 },
1014 .emit = brw_upload_wm_pull_constants,
1015 };
1016
1017 static void
1018 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1019 {
1020 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1021 * Notes):
1022 *
1023 * A null surface will be used in instances where an actual surface is
1024 * not bound. When a write message is generated to a null surface, no
1025 * actual surface is written to. When a read message (including any
1026 * sampling engine message) is generated to a null surface, the result
1027 * is all zeros. Note that a null surface type is allowed to be used
1028 * with all messages, even if it is not specificially indicated as
1029 * supported. All of the remaining fields in surface state are ignored
1030 * for null surfaces, with the following exceptions:
1031 *
1032 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1033 * depth buffer’s corresponding state for all render target surfaces,
1034 * including null.
1035 *
1036 * - Surface Format must be R8G8B8A8_UNORM.
1037 */
1038 struct intel_context *intel = &brw->intel;
1039 struct gl_context *ctx = &intel->ctx;
1040 uint32_t *surf;
1041 unsigned surface_type = BRW_SURFACE_NULL;
1042 drm_intel_bo *bo = NULL;
1043 unsigned pitch_minus_1 = 0;
1044 uint32_t multisampling_state = 0;
1045
1046 /* _NEW_BUFFERS */
1047 const struct gl_framebuffer *fb = ctx->DrawBuffer;
1048
1049 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1050 6 * 4, 32, &brw->wm.surf_offset[unit]);
1051
1052 if (fb->Visual.samples > 1) {
1053 /* On Gen6, null render targets seem to cause GPU hangs when
1054 * multisampling. So work around this problem by rendering into dummy
1055 * color buffer.
1056 *
1057 * To decrease the amount of memory needed by the workaround buffer, we
1058 * set its pitch to 128 bytes (the width of a Y tile). This means that
1059 * the amount of memory needed for the workaround buffer is
1060 * (width_in_tiles + height_in_tiles - 1) tiles.
1061 *
1062 * Note that since the workaround buffer will be interpreted by the
1063 * hardware as an interleaved multisampled buffer, we need to compute
1064 * width_in_tiles and height_in_tiles by dividing the width and height
1065 * by 16 rather than the normal Y-tile size of 32.
1066 */
1067 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1068 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1069 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1070 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1071 size_needed);
1072 bo = brw->wm.multisampled_null_render_target_bo;
1073 surface_type = BRW_SURFACE_2D;
1074 pitch_minus_1 = 127;
1075 multisampling_state =
1076 brw_get_surface_num_multisamples(fb->Visual.samples);
1077 }
1078
1079 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1080 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1081 if (intel->gen < 6) {
1082 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1083 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1084 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1085 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1086 }
1087 surf[1] = bo ? bo->offset : 0;
1088 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1089 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1090
1091 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1092 * Notes):
1093 *
1094 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
1095 */
1096 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1097 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1098 surf[4] = multisampling_state;
1099 surf[5] = 0;
1100
1101 if (bo) {
1102 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1103 brw->wm.surf_offset[unit] + 4,
1104 bo, 0,
1105 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1106 }
1107 }
1108
1109 /**
1110 * Sets up a surface state structure to point at the given region.
1111 * While it is only used for the front/back buffer currently, it should be
1112 * usable for further buffers when doing ARB_draw_buffer support.
1113 */
1114 static void
1115 brw_update_renderbuffer_surface(struct brw_context *brw,
1116 struct gl_renderbuffer *rb,
1117 unsigned int unit)
1118 {
1119 struct intel_context *intel = &brw->intel;
1120 struct gl_context *ctx = &intel->ctx;
1121 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1122 struct intel_mipmap_tree *mt = irb->mt;
1123 struct intel_region *region;
1124 uint32_t *surf;
1125 uint32_t tile_x, tile_y;
1126 uint32_t format = 0;
1127 gl_format rb_format = intel_rb_format(irb);
1128
1129 if (irb->tex_image && !brw->has_surface_tile_offset) {
1130 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1131
1132 if (tile_x != 0 || tile_y != 0) {
1133 /* Original gen4 hardware couldn't draw to a non-tile-aligned
1134 * destination in a miptree unless you actually setup your renderbuffer
1135 * as a miptree and used the fragile lod/array_index/etc. controls to
1136 * select the image. So, instead, we just make a new single-level
1137 * miptree and render into that.
1138 */
1139 struct intel_context *intel = intel_context(ctx);
1140 struct intel_texture_image *intel_image =
1141 intel_texture_image(irb->tex_image);
1142 struct intel_mipmap_tree *new_mt;
1143 int width, height, depth;
1144
1145 intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth);
1146
1147 new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target,
1148 intel_image->base.Base.TexFormat,
1149 intel_image->base.Base.Level,
1150 intel_image->base.Base.Level,
1151 width, height, depth,
1152 true,
1153 0 /* num_samples */,
1154 INTEL_MSAA_LAYOUT_NONE);
1155
1156 intel_miptree_copy_teximage(intel, intel_image, new_mt);
1157 intel_miptree_reference(&irb->mt, intel_image->mt);
1158 intel_renderbuffer_set_draw_offset(irb);
1159 intel_miptree_release(&new_mt);
1160
1161 mt = irb->mt;
1162 }
1163 }
1164
1165 region = irb->mt->region;
1166
1167 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1168 6 * 4, 32, &brw->wm.surf_offset[unit]);
1169
1170 switch (rb_format) {
1171 case MESA_FORMAT_SARGB8:
1172 /* _NEW_BUFFERS
1173 *
1174 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1175 * blend/update as sRGB.
1176 */
1177 if (ctx->Color.sRGBEnabled)
1178 format = brw_format_for_mesa_format(rb_format);
1179 else
1180 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1181 break;
1182 default:
1183 format = brw->render_target_format[rb_format];
1184 if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1185 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1186 __FUNCTION__, _mesa_get_format_name(rb_format));
1187 }
1188 break;
1189 }
1190
1191 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1192 format << BRW_SURFACE_FORMAT_SHIFT);
1193
1194 /* reloc */
1195 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1196 region->bo->offset);
1197
1198 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1199 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1200
1201 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1202 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
1203
1204 surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1205
1206 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1207 /* Note that the low bits of these fields are missing, so
1208 * there's the possibility of getting in trouble.
1209 */
1210 assert(tile_x % 4 == 0);
1211 assert(tile_y % 2 == 0);
1212 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1213 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1214 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1215
1216 if (intel->gen < 6) {
1217 /* _NEW_COLOR */
1218 if (!ctx->Color.ColorLogicOpEnabled &&
1219 (ctx->Color.BlendEnabled & (1 << unit)))
1220 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1221
1222 if (!ctx->Color.ColorMask[unit][0])
1223 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1224 if (!ctx->Color.ColorMask[unit][1])
1225 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1226 if (!ctx->Color.ColorMask[unit][2])
1227 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1228
1229 /* As mentioned above, disable writes to the alpha component when the
1230 * renderbuffer is XRGB.
1231 */
1232 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1233 !ctx->Color.ColorMask[unit][3]) {
1234 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1235 }
1236 }
1237
1238 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1239 brw->wm.surf_offset[unit] + 4,
1240 region->bo,
1241 surf[1] - region->bo->offset,
1242 I915_GEM_DOMAIN_RENDER,
1243 I915_GEM_DOMAIN_RENDER);
1244 }
1245
1246 /**
1247 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1248 */
1249 static void
1250 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1251 {
1252 struct intel_context *intel = &brw->intel;
1253 struct gl_context *ctx = &brw->intel.ctx;
1254 GLuint i;
1255
1256 /* _NEW_BUFFERS | _NEW_COLOR */
1257 /* Update surfaces for drawing buffers */
1258 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1259 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1260 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1261 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1262 } else {
1263 intel->vtbl.update_null_renderbuffer_surface(brw, i);
1264 }
1265 }
1266 } else {
1267 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1268 }
1269 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1270 }
1271
1272 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1273 .dirty = {
1274 .mesa = (_NEW_COLOR |
1275 _NEW_BUFFERS),
1276 .brw = BRW_NEW_BATCH,
1277 .cache = 0
1278 },
1279 .emit = brw_update_renderbuffer_surfaces,
1280 };
1281
1282 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1283 .dirty = {
1284 .mesa = _NEW_BUFFERS,
1285 .brw = BRW_NEW_BATCH,
1286 .cache = 0
1287 },
1288 .emit = brw_update_renderbuffer_surfaces,
1289 };
1290
1291 /**
1292 * Construct SURFACE_STATE objects for enabled textures.
1293 */
1294 static void
1295 brw_update_texture_surfaces(struct brw_context *brw)
1296 {
1297 struct intel_context *intel = &brw->intel;
1298 struct gl_context *ctx = &intel->ctx;
1299
1300 /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1301 * Unfortunately, we're stuck using the gl_program structs until the
1302 * ARB_fragment_program front-end gets converted to GLSL IR. These
1303 * have the downside that SamplerUnits is split and only contains the
1304 * mappings for samplers active in that stage.
1305 */
1306 struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1307 struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1308
1309 unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1310
1311 for (unsigned s = 0; s < num_samplers; s++) {
1312 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1313 brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1314
1315 if (vs->SamplersUsed & (1 << s)) {
1316 const unsigned unit = vs->SamplerUnits[s];
1317
1318 /* _NEW_TEXTURE */
1319 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1320 intel->vtbl.update_texture_surface(ctx, unit,
1321 brw->vs.surf_offset,
1322 SURF_INDEX_VS_TEXTURE(s));
1323 }
1324 }
1325
1326 if (fs->SamplersUsed & (1 << s)) {
1327 const unsigned unit = fs->SamplerUnits[s];
1328
1329 /* _NEW_TEXTURE */
1330 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1331 intel->vtbl.update_texture_surface(ctx, unit,
1332 brw->wm.surf_offset,
1333 SURF_INDEX_TEXTURE(s));
1334 }
1335 }
1336 }
1337
1338 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1339 }
1340
1341 const struct brw_tracked_state brw_texture_surfaces = {
1342 .dirty = {
1343 .mesa = _NEW_TEXTURE,
1344 .brw = BRW_NEW_BATCH |
1345 BRW_NEW_VERTEX_PROGRAM |
1346 BRW_NEW_FRAGMENT_PROGRAM,
1347 .cache = 0
1348 },
1349 .emit = brw_update_texture_surfaces,
1350 };
1351
1352 void
1353 brw_upload_ubo_surfaces(struct brw_context *brw,
1354 struct gl_shader *shader,
1355 uint32_t *surf_offsets)
1356 {
1357 struct gl_context *ctx = &brw->intel.ctx;
1358 struct intel_context *intel = &brw->intel;
1359
1360 if (!shader)
1361 return;
1362
1363 for (int i = 0; i < shader->NumUniformBlocks; i++) {
1364 struct gl_uniform_buffer_binding *binding;
1365 struct intel_buffer_object *intel_bo;
1366
1367 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1368 intel_bo = intel_buffer_object(binding->BufferObject);
1369 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1370
1371 /* Because behavior for referencing outside of the binding's size in the
1372 * glBindBufferRange case is undefined, we can just bind the whole buffer
1373 * glBindBufferBase wants and be a correct implementation.
1374 */
1375 int size = bo->size - binding->Offset;
1376 size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1377
1378 intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1379 size,
1380 &surf_offsets[i]);
1381 }
1382
1383 if (shader->NumUniformBlocks)
1384 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1385 }
1386
1387 static void
1388 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1389 {
1390 struct gl_context *ctx = &brw->intel.ctx;
1391 /* _NEW_PROGRAM */
1392 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1393
1394 if (!prog)
1395 return;
1396
1397 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1398 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1399 }
1400
1401 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1402 .dirty = {
1403 .mesa = (_NEW_PROGRAM |
1404 _NEW_BUFFER_OBJECT),
1405 .brw = BRW_NEW_BATCH,
1406 .cache = 0,
1407 },
1408 .emit = brw_upload_wm_ubo_surfaces,
1409 };
1410
1411 /**
1412 * Constructs the binding table for the WM surface state, which maps unit
1413 * numbers to surface state objects.
1414 */
1415 static void
1416 brw_upload_wm_binding_table(struct brw_context *brw)
1417 {
1418 uint32_t *bind;
1419 int i;
1420
1421 /* Might want to calculate nr_surfaces first, to avoid taking up so much
1422 * space for the binding table.
1423 */
1424 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1425 sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1426 32, &brw->wm.bind_bo_offset);
1427
1428 /* BRW_NEW_SURFACES */
1429 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1430 bind[i] = brw->wm.surf_offset[i];
1431 }
1432
1433 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1434 }
1435
1436 const struct brw_tracked_state brw_wm_binding_table = {
1437 .dirty = {
1438 .mesa = 0,
1439 .brw = (BRW_NEW_BATCH |
1440 BRW_NEW_SURFACES),
1441 .cache = 0
1442 },
1443 .emit = brw_upload_wm_binding_table,
1444 };
1445
1446 void
1447 gen4_init_vtable_surface_functions(struct brw_context *brw)
1448 {
1449 struct intel_context *intel = &brw->intel;
1450
1451 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1452 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1453 intel->vtbl.update_null_renderbuffer_surface =
1454 brw_update_null_renderbuffer_surface;
1455 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1456 }