2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "main/texstore.h"
36 #include "program/prog_parameter.h"
38 #include "intel_mipmap_tree.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_fbo.h"
43 #include "brw_context.h"
44 #include "brw_state.h"
45 #include "brw_defines.h"
49 translate_tex_target(GLenum target
)
53 return BRW_SURFACE_1D
;
55 case GL_TEXTURE_RECTANGLE_NV
:
56 return BRW_SURFACE_2D
;
59 return BRW_SURFACE_2D
;
62 return BRW_SURFACE_3D
;
64 case GL_TEXTURE_CUBE_MAP
:
65 return BRW_SURFACE_CUBE
;
74 brw_format_for_mesa_format(gl_format mesa_format
)
76 static const uint32_t table
[MESA_FORMAT_COUNT
] =
78 [MESA_FORMAT_L8
] = BRW_SURFACEFORMAT_L8_UNORM
,
79 [MESA_FORMAT_I8
] = BRW_SURFACEFORMAT_I8_UNORM
,
80 [MESA_FORMAT_A8
] = BRW_SURFACEFORMAT_A8_UNORM
,
81 [MESA_FORMAT_AL88
] = BRW_SURFACEFORMAT_L8A8_UNORM
,
82 [MESA_FORMAT_AL1616
] = BRW_SURFACEFORMAT_L16A16_UNORM
,
83 [MESA_FORMAT_R8
] = BRW_SURFACEFORMAT_R8_UNORM
,
84 [MESA_FORMAT_R16
] = BRW_SURFACEFORMAT_R16_UNORM
,
85 [MESA_FORMAT_RG88
] = BRW_SURFACEFORMAT_R8G8_UNORM
,
86 [MESA_FORMAT_RG1616
] = BRW_SURFACEFORMAT_R16G16_UNORM
,
87 [MESA_FORMAT_ARGB8888
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM
,
88 [MESA_FORMAT_XRGB8888
] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM
,
89 [MESA_FORMAT_RGB565
] = BRW_SURFACEFORMAT_B5G6R5_UNORM
,
90 [MESA_FORMAT_ARGB1555
] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM
,
91 [MESA_FORMAT_ARGB4444
] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM
,
92 [MESA_FORMAT_YCBCR_REV
] = BRW_SURFACEFORMAT_YCRCB_NORMAL
,
93 [MESA_FORMAT_YCBCR
] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY
,
94 [MESA_FORMAT_RGB_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
95 [MESA_FORMAT_RGBA_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
96 [MESA_FORMAT_RGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB
,
97 [MESA_FORMAT_RGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM
,
98 [MESA_FORMAT_RGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM
,
99 [MESA_FORMAT_RGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM
,
100 [MESA_FORMAT_SRGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB
,
101 [MESA_FORMAT_SRGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB
,
102 [MESA_FORMAT_SRGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB
,
103 [MESA_FORMAT_SRGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB
,
104 [MESA_FORMAT_SARGB8
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
,
105 [MESA_FORMAT_SLA8
] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB
,
106 [MESA_FORMAT_SL8
] = BRW_SURFACEFORMAT_L8_UNORM_SRGB
,
107 [MESA_FORMAT_DUDV8
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
108 [MESA_FORMAT_SIGNED_R8
] = BRW_SURFACEFORMAT_R8_SNORM
,
109 [MESA_FORMAT_SIGNED_RG88_REV
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
110 [MESA_FORMAT_SIGNED_RGBA8888_REV
] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM
,
111 [MESA_FORMAT_SIGNED_R16
] = BRW_SURFACEFORMAT_R16_SNORM
,
112 [MESA_FORMAT_SIGNED_GR1616
] = BRW_SURFACEFORMAT_R16G16_SNORM
,
113 [MESA_FORMAT_RGBA_FLOAT32
] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
114 [MESA_FORMAT_RG_FLOAT32
] = BRW_SURFACEFORMAT_R32G32_FLOAT
,
115 [MESA_FORMAT_R_FLOAT32
] = BRW_SURFACEFORMAT_R32_FLOAT
,
116 [MESA_FORMAT_INTENSITY_FLOAT32
] = BRW_SURFACEFORMAT_I32_FLOAT
,
117 [MESA_FORMAT_LUMINANCE_FLOAT32
] = BRW_SURFACEFORMAT_L32_FLOAT
,
118 [MESA_FORMAT_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_A32_FLOAT
,
119 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_L32A32_FLOAT
,
120 [MESA_FORMAT_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_UNORM
,
121 [MESA_FORMAT_SIGNED_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_SNORM
,
122 [MESA_FORMAT_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_UNORM
,
123 [MESA_FORMAT_SIGNED_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_SNORM
,
125 assert(mesa_format
< MESA_FORMAT_COUNT
);
126 return table
[mesa_format
];
130 brw_render_target_supported(gl_format format
)
132 /* These are not color render targets like the table holds, but we
133 * ask the question for FBO completeness.
135 if (format
== MESA_FORMAT_S8_Z24
||
136 format
== MESA_FORMAT_X8_Z24
||
137 format
== MESA_FORMAT_S8
||
138 format
== MESA_FORMAT_Z16
) {
142 /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
144 if (format
== MESA_FORMAT_RGBA_FLOAT32
)
147 /* Not exactly true, as some of those formats are not renderable.
148 * But at least we know how to translate them.
150 return brw_format_for_mesa_format(format
) != 0;
154 translate_tex_format(gl_format mesa_format
,
155 GLenum internal_format
,
159 switch( mesa_format
) {
161 case MESA_FORMAT_Z16
:
162 if (depth_mode
== GL_INTENSITY
)
163 return BRW_SURFACEFORMAT_I16_UNORM
;
164 else if (depth_mode
== GL_ALPHA
)
165 return BRW_SURFACEFORMAT_A16_UNORM
;
166 else if (depth_mode
== GL_RED
)
167 return BRW_SURFACEFORMAT_R16_UNORM
;
169 return BRW_SURFACEFORMAT_L16_UNORM
;
171 case MESA_FORMAT_S8_Z24
:
172 case MESA_FORMAT_X8_Z24
:
173 /* XXX: these different surface formats don't seem to
174 * make any difference for shadow sampler/compares.
176 if (depth_mode
== GL_INTENSITY
)
177 return BRW_SURFACEFORMAT_I24X8_UNORM
;
178 else if (depth_mode
== GL_ALPHA
)
179 return BRW_SURFACEFORMAT_A24X8_UNORM
;
180 else if (depth_mode
== GL_RED
)
181 return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
;
183 return BRW_SURFACEFORMAT_L24X8_UNORM
;
185 case MESA_FORMAT_SARGB8
:
186 case MESA_FORMAT_SLA8
:
187 case MESA_FORMAT_SL8
:
188 if (srgb_decode
== GL_DECODE_EXT
)
189 return brw_format_for_mesa_format(mesa_format
);
190 else if (srgb_decode
== GL_SKIP_DECODE_EXT
)
191 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format
));
193 case MESA_FORMAT_RGBA_FLOAT32
:
194 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
197 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
200 assert(brw_format_for_mesa_format(mesa_format
) != 0);
201 return brw_format_for_mesa_format(mesa_format
);
206 brw_get_surface_tiling_bits(uint32_t tiling
)
210 return BRW_SURFACE_TILED
;
212 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
219 brw_update_texture_surface( struct gl_context
*ctx
, GLuint unit
)
221 struct brw_context
*brw
= brw_context(ctx
);
222 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
223 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
224 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
225 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
226 const GLuint surf_index
= SURF_INDEX_TEXTURE(unit
);
229 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
230 6 * 4, 32, &brw
->wm
.surf_offset
[surf_index
]);
232 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
233 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
234 BRW_SURFACE_CUBEFACE_ENABLES
|
235 (translate_tex_format(firstImage
->TexFormat
,
236 firstImage
->InternalFormat
,
238 sampler
->sRGBDecode
) <<
239 BRW_SURFACE_FORMAT_SHIFT
));
241 surf
[1] = intelObj
->mt
->region
->buffer
->offset
; /* reloc */
243 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
244 (firstImage
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
245 (firstImage
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
247 surf
[3] = (brw_get_surface_tiling_bits(intelObj
->mt
->region
->tiling
) |
248 (firstImage
->Depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
249 ((intelObj
->mt
->region
->pitch
* intelObj
->mt
->cpp
) - 1) <<
250 BRW_SURFACE_PITCH_SHIFT
);
255 /* Emit relocation to surface contents */
256 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
257 brw
->wm
.surf_offset
[surf_index
] + 4,
258 intelObj
->mt
->region
->buffer
, 0,
259 I915_GEM_DOMAIN_SAMPLER
, 0);
263 * Create the constant buffer surface. Vertex/fragment shader constants will be
264 * read from this buffer with Data Port Read instructions/messages.
267 brw_create_constant_surface(struct brw_context
*brw
,
270 uint32_t *out_offset
)
272 struct intel_context
*intel
= &brw
->intel
;
273 const GLint w
= width
- 1;
276 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
277 6 * 4, 32, out_offset
);
279 surf
[0] = (BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
280 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
281 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_SURFACE_FORMAT_SHIFT
);
284 surf
[0] |= BRW_SURFACE_RC_READ_WRITE
;
286 surf
[1] = bo
->offset
; /* reloc */
288 surf
[2] = (((w
& 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT
|
289 (((w
>> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT
);
291 surf
[3] = ((((w
>> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT
|
292 (width
* 16 - 1) << BRW_SURFACE_PITCH_SHIFT
);
297 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
298 * bspec ("Data Cache") says that the data cache does not exist as
299 * a separate cache and is just the sampler cache.
301 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
304 I915_GEM_DOMAIN_SAMPLER
, 0);
307 /* Creates a new WM constant buffer reflecting the current fragment program's
308 * constants, if needed by the fragment program.
310 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
314 prepare_wm_pull_constants(struct brw_context
*brw
)
316 struct gl_context
*ctx
= &brw
->intel
.ctx
;
317 struct intel_context
*intel
= &brw
->intel
;
318 struct brw_fragment_program
*fp
=
319 (struct brw_fragment_program
*) brw
->fragment_program
;
320 const int size
= brw
->wm
.prog_data
->nr_pull_params
* sizeof(float);
324 _mesa_load_state_parameters(ctx
, fp
->program
.Base
.Parameters
);
326 /* BRW_NEW_FRAGMENT_PROGRAM */
327 if (brw
->wm
.prog_data
->nr_pull_params
== 0) {
328 if (brw
->wm
.const_bo
) {
329 drm_intel_bo_unreference(brw
->wm
.const_bo
);
330 brw
->wm
.const_bo
= NULL
;
331 brw
->state
.dirty
.brw
|= BRW_NEW_WM_CONSTBUF
;
336 drm_intel_bo_unreference(brw
->wm
.const_bo
);
337 brw
->wm
.const_bo
= drm_intel_bo_alloc(intel
->bufmgr
, "WM const bo",
340 /* _NEW_PROGRAM_CONSTANTS */
341 drm_intel_gem_bo_map_gtt(brw
->wm
.const_bo
);
342 constants
= brw
->wm
.const_bo
->virtual;
343 for (i
= 0; i
< brw
->wm
.prog_data
->nr_pull_params
; i
++) {
344 constants
[i
] = convert_param(brw
->wm
.prog_data
->pull_param_convert
[i
],
345 brw
->wm
.prog_data
->pull_param
[i
]);
347 drm_intel_gem_bo_unmap_gtt(brw
->wm
.const_bo
);
349 brw
->state
.dirty
.brw
|= BRW_NEW_WM_CONSTBUF
;
352 const struct brw_tracked_state brw_wm_constants
= {
354 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
355 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
),
358 .prepare
= prepare_wm_pull_constants
,
362 * Updates surface / buffer for fragment shader constant buffer, if
365 * This consumes the state updates for the constant buffer, and produces
366 * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
367 * inclusion in the binding table.
369 static void upload_wm_constant_surface(struct brw_context
*brw
)
371 GLuint surf
= SURF_INDEX_FRAG_CONST_BUFFER
;
372 struct brw_fragment_program
*fp
=
373 (struct brw_fragment_program
*) brw
->fragment_program
;
374 const struct gl_program_parameter_list
*params
=
375 fp
->program
.Base
.Parameters
;
377 /* If there's no constant buffer, then no surface BO is needed to point at
380 if (brw
->wm
.const_bo
== 0) {
381 if (brw
->wm
.surf_offset
[surf
]) {
382 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
383 brw
->wm
.surf_offset
[surf
] = 0;
388 brw_create_constant_surface(brw
, brw
->wm
.const_bo
, params
->NumParameters
,
389 &brw
->wm
.surf_offset
[surf
]);
390 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
393 const struct brw_tracked_state brw_wm_constant_surface
= {
396 .brw
= (BRW_NEW_WM_CONSTBUF
|
400 .emit
= upload_wm_constant_surface
,
404 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
406 struct intel_context
*intel
= &brw
->intel
;
409 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
410 6 * 4, 32, &brw
->wm
.surf_offset
[unit
]);
412 surf
[0] = (BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
413 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
414 if (intel
->gen
< 6) {
415 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
416 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
417 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
418 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
428 * Sets up a surface state structure to point at the given region.
429 * While it is only used for the front/back buffer currently, it should be
430 * usable for further buffers when doing ARB_draw_buffer support.
433 brw_update_renderbuffer_surface(struct brw_context
*brw
,
434 struct gl_renderbuffer
*rb
,
437 struct intel_context
*intel
= &brw
->intel
;
438 struct gl_context
*ctx
= &intel
->ctx
;
439 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
440 struct intel_region
*region
= irb
->region
;
442 uint32_t tile_x
, tile_y
;
445 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
446 6 * 4, 32, &brw
->wm
.surf_offset
[unit
]);
448 switch (irb
->Base
.Format
) {
449 case MESA_FORMAT_XRGB8888
:
450 /* XRGB is handled as ARGB because the chips in this family
451 * cannot render to XRGB targets. This means that we have to
452 * mask writes to alpha (ala glColorMask) and reconfigure the
453 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
454 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
457 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
459 case MESA_FORMAT_INTENSITY_FLOAT32
:
460 case MESA_FORMAT_LUMINANCE_FLOAT32
:
461 /* For these formats, we just need to read/write the first
462 * channel into R, which is to say that we just treat them as
465 format
= BRW_SURFACEFORMAT_R32_FLOAT
;
467 case MESA_FORMAT_SARGB8
:
468 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
469 surfaces to the blend/update as sRGB */
470 if (ctx
->Color
.sRGBEnabled
)
471 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
473 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
476 assert(brw_render_target_supported(irb
->Base
.Format
));
477 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
480 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
481 format
<< BRW_SURFACE_FORMAT_SHIFT
);
484 surf
[1] = (intel_renderbuffer_tile_offsets(irb
, &tile_x
, &tile_y
) +
485 region
->buffer
->offset
);
487 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
488 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
490 surf
[3] = (brw_get_surface_tiling_bits(region
->tiling
) |
491 ((region
->pitch
* region
->cpp
) - 1) << BRW_SURFACE_PITCH_SHIFT
);
495 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
496 /* Note that the low bits of these fields are missing, so
497 * there's the possibility of getting in trouble.
499 assert(tile_x
% 4 == 0);
500 assert(tile_y
% 2 == 0);
501 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
502 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
);
504 if (intel
->gen
< 6) {
506 if (!ctx
->Color
._LogicOpEnabled
&&
507 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
508 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
510 if (!ctx
->Color
.ColorMask
[unit
][0])
511 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
512 if (!ctx
->Color
.ColorMask
[unit
][1])
513 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
514 if (!ctx
->Color
.ColorMask
[unit
][2])
515 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
517 /* As mentioned above, disable writes to the alpha component when the
518 * renderbuffer is XRGB.
520 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
521 !ctx
->Color
.ColorMask
[unit
][3]) {
522 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
526 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
527 brw
->wm
.surf_offset
[unit
] + 4,
529 surf
[1] - region
->buffer
->offset
,
530 I915_GEM_DOMAIN_RENDER
,
531 I915_GEM_DOMAIN_RENDER
);
535 prepare_wm_surfaces(struct brw_context
*brw
)
537 struct gl_context
*ctx
= &brw
->intel
.ctx
;
541 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
542 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
543 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
544 struct intel_region
*region
= irb
? irb
->region
: NULL
;
547 brw_add_validated_bo(brw
, region
->buffer
);
548 nr_surfaces
= SURF_INDEX_DRAW(i
) + 1;
551 if (brw
->wm
.const_bo
) {
552 brw_add_validated_bo(brw
, brw
->wm
.const_bo
);
553 nr_surfaces
= SURF_INDEX_FRAG_CONST_BUFFER
+ 1;
556 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
557 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
559 if (texUnit
->_ReallyEnabled
) {
560 struct gl_texture_object
*tObj
= texUnit
->_Current
;
561 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
563 brw_add_validated_bo(brw
, intelObj
->mt
->region
->buffer
);
564 nr_surfaces
= SURF_INDEX_TEXTURE(i
) + 1;
568 /* Have to update this in our prepare, since the unit's prepare
571 if (brw
->wm
.nr_surfaces
!= nr_surfaces
) {
572 brw
->wm
.nr_surfaces
= nr_surfaces
;
573 brw
->state
.dirty
.brw
|= BRW_NEW_NR_WM_SURFACES
;
578 * Constructs the set of surface state objects pointed to by the
582 upload_wm_surfaces(struct brw_context
*brw
)
584 struct gl_context
*ctx
= &brw
->intel
.ctx
;
587 /* _NEW_BUFFERS | _NEW_COLOR */
588 /* Update surfaces for drawing buffers */
589 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
590 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
591 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
592 brw_update_renderbuffer_surface(brw
,
593 ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
596 brw_update_null_renderbuffer_surface(brw
, i
);
600 brw_update_null_renderbuffer_surface(brw
, 0);
603 /* Update surfaces for textures */
604 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
605 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
606 const GLuint surf
= SURF_INDEX_TEXTURE(i
);
609 if (texUnit
->_ReallyEnabled
) {
610 brw_update_texture_surface(ctx
, i
);
612 brw
->wm
.surf_offset
[surf
] = 0;
616 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
619 const struct brw_tracked_state brw_wm_surfaces
= {
621 .mesa
= (_NEW_COLOR
|
624 .brw
= (BRW_NEW_BATCH
),
627 .prepare
= prepare_wm_surfaces
,
628 .emit
= upload_wm_surfaces
,
632 * Constructs the binding table for the WM surface state, which maps unit
633 * numbers to surface state objects.
636 brw_wm_upload_binding_table(struct brw_context
*brw
)
641 /* Might want to calculate nr_surfaces first, to avoid taking up so much
642 * space for the binding table.
644 bind
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
645 sizeof(uint32_t) * BRW_WM_MAX_SURF
,
646 32, &brw
->wm
.bind_bo_offset
);
648 for (i
= 0; i
< BRW_WM_MAX_SURF
; i
++) {
649 /* BRW_NEW_WM_SURFACES */
650 bind
[i
] = brw
->wm
.surf_offset
[i
];
653 brw
->state
.dirty
.brw
|= BRW_NEW_PS_BINDING_TABLE
;
656 const struct brw_tracked_state brw_wm_binding_table
= {
659 .brw
= (BRW_NEW_BATCH
|
660 BRW_NEW_WM_SURFACES
),
663 .emit
= brw_wm_upload_binding_table
,