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mesa: skip _MaxElement computation unless driver needs strict bounds checking
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "program/prog_parameter.h"
38
39 #include "intel_mipmap_tree.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_fbo.h"
43 #include "intel_buffer_objects.h"
44
45 #include "brw_context.h"
46 #include "brw_state.h"
47 #include "brw_defines.h"
48 #include "brw_wm.h"
49
50 GLuint
51 translate_tex_target(GLenum target)
52 {
53 switch (target) {
54 case GL_TEXTURE_1D:
55 case GL_TEXTURE_1D_ARRAY_EXT:
56 return BRW_SURFACE_1D;
57
58 case GL_TEXTURE_RECTANGLE_NV:
59 return BRW_SURFACE_2D;
60
61 case GL_TEXTURE_2D:
62 case GL_TEXTURE_2D_ARRAY_EXT:
63 case GL_TEXTURE_EXTERNAL_OES:
64 case GL_TEXTURE_2D_MULTISAMPLE:
65 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
66 return BRW_SURFACE_2D;
67
68 case GL_TEXTURE_3D:
69 return BRW_SURFACE_3D;
70
71 case GL_TEXTURE_CUBE_MAP:
72 case GL_TEXTURE_CUBE_MAP_ARRAY:
73 return BRW_SURFACE_CUBE;
74
75 default:
76 assert(0);
77 return 0;
78 }
79 }
80
81 struct surface_format_info {
82 bool exists;
83 int sampling;
84 int filtering;
85 int shadow_compare;
86 int chroma_key;
87 int render_target;
88 int alpha_blend;
89 int input_vb;
90 int streamed_output_vb;
91 int color_processing;
92 };
93
94 /* This macro allows us to write the table almost as it appears in the PRM,
95 * while restructuring it to turn it into the C code we want.
96 */
97 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
98 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
99
100 #define Y 0
101 #define x 999
102 /**
103 * This is the table of support for surface (texture, renderbuffer, and vertex
104 * buffer, but not depthbuffer) formats across the various hardware generations.
105 *
106 * The table is formatted to match the documentation, except that the docs have
107 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
108 * it in our table, here's the mapping:
109 *
110 * Y*: 45
111 * Y+: 45 (g45/gm45)
112 * Y~: 50 (gen5)
113 * Y^: 60 (gen6)
114 * Y#: 70 (gen7)
115 *
116 * The abbreviations in the header below are:
117 * smpl - Sampling Engine
118 * filt - Sampling Engine Filtering
119 * shad - Sampling Engine Shadow Map
120 * CK - Sampling Engine Chroma Key
121 * RT - Render Target
122 * AB - Alpha Blend Render Target
123 * VB - Input Vertex Buffer
124 * SO - Steamed Output Vertex Buffers (transform feedback)
125 * color - Color Processing
126 *
127 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
128 *
129 * As of Ivybridge, the columns are no longer in that table and the
130 * information can be found spread across:
131 *
132 * - VOL2_Part1 section 2.5.11 Format Conversion (vertex fetch).
133 * - VOL4_Part1 section 2.12.2.1.2 Sampler Output Channel Mapping.
134 * - VOL4_Part1 section 3.9.11 Render Target Write.
135 */
136 const struct surface_format_info surface_formats[] = {
137 /* smpl filt shad CK RT AB VB SO color */
138 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
139 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
140 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
141 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
144 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
145 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
146 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
147 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SFIXED)
148 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64_PASSTHRU)
149 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
150 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
151 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
152 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
153 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
154 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
155 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
156 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32_SFIXED)
157 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
158 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
159 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
160 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
161 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
162 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
163 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
164 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
165 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
166 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
167 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
168 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
169 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
170 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
171 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
172 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
173 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
174 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
175 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
176 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
177 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
178 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
179 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
180 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32_SFIXED)
181 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64_PASSTHRU)
182 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
183 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
184 /* smpl filt shad CK RT AB VB SO color */
185 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
186 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
187 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
188 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
189 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
190 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
191 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
192 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
193 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
194 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
195 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
196 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
197 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
198 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
199 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
200 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
201 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
202 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
203 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
204 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
205 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
206 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
207 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
208 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
209 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
210 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
211 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
212 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
213 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
214 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
215 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
216 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
217 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
218 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
219 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
220 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
221 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
222 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
223 /* smpl filt shad CK RT AB VB SO color */
224 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
225 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
226 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
227 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
228 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
229 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
231 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
232 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
233 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
234 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
235 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
236 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
237 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
238 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
239 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
240 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
241 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
242 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
243 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
244 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
245 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
246 SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0)
247 SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1)
248 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
249 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
250 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
251 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
252 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
253 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
254 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
255 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
256 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
257 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
258 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
259 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
260 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
261 /* smpl filt shad CK RT AB VB SO color */
262 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
263 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
264 SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0)
265 SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1)
266 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A1B5G5R5_UNORM)
267 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4B4G4R4_UNORM)
268 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UINT)
269 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_SINT)
270 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
271 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
272 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
273 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
274 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
275 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
276 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
277 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
278 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
279 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
280 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
281 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8_UNORM_PALETTE0)
282 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
283 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8_UNORM_PALETTE1)
284 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1)
285 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1)
286 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_Y8_SNORM)
287 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UINT)
288 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_SINT)
289 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UINT)
290 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_SINT)
291 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
292 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
293 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
294 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
295 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P2_UNORM_PALETTE0)
296 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P2_UNORM_PALETTE1)
297 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
298 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
299 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
300 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
301 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
302 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
303 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
304 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
305 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
306 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
307 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
308 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
309 /* smpl filt shad CK RT AB VB SO color */
310 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
311 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
312 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
313 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
314 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
315 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
316 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
317 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
318 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
319 SF(50, 50, x, x, x, x, 60, x, x, BRW_SURFACEFORMAT_R16G16B16_FLOAT)
320 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
321 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
322 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
323 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
324 SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC6H_SF16)
325 SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC7_UNORM)
326 SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC7_UNORM_SRGB)
327 SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC6H_UF16)
328 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_PLANAR_420_8)
329 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB)
330 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC1_RGB8)
331 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_RGB8)
332 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_R11)
333 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_RG11)
334 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_SIGNED_R11)
335 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_SIGNED_RG11)
336 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_SRGB8)
337 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16_UINT)
338 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16_SINT)
339 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_SFIXED)
340 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SNORM)
341 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_USCALED)
342 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SSCALED)
343 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SINT)
344 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SNORM)
345 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_USCALED)
346 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SSCALED)
347 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_UINT)
348 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SINT)
349 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU)
350 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64B64_PASSTHRU)
351 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_RGB8_PTA)
352 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_SRGB8_PTA)
353 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_EAC_RGBA8)
354 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8)
355 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_UINT)
356 SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_SINT)
357 };
358 #undef x
359 #undef Y
360
361 uint32_t
362 brw_format_for_mesa_format(gl_format mesa_format)
363 {
364 /* This table is ordered according to the enum ordering in formats.h. We do
365 * expect that enum to be extended without our explicit initialization
366 * staying in sync, so we initialize to 0 even though
367 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
368 */
369 static const uint32_t table[MESA_FORMAT_COUNT] =
370 {
371 [MESA_FORMAT_RGBA8888] = 0,
372 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
373 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
374 [MESA_FORMAT_ARGB8888_REV] = 0,
375 [MESA_FORMAT_RGBX8888] = 0,
376 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
377 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
378 [MESA_FORMAT_XRGB8888_REV] = 0,
379 [MESA_FORMAT_RGB888] = 0,
380 [MESA_FORMAT_BGR888] = 0,
381 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
382 [MESA_FORMAT_RGB565_REV] = 0,
383 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
384 [MESA_FORMAT_ARGB4444_REV] = 0,
385 [MESA_FORMAT_RGBA5551] = 0,
386 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
387 [MESA_FORMAT_ARGB1555_REV] = 0,
388 [MESA_FORMAT_AL44] = 0,
389 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
390 [MESA_FORMAT_AL88_REV] = 0,
391 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
392 [MESA_FORMAT_AL1616_REV] = 0,
393 [MESA_FORMAT_RGB332] = 0,
394 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
395 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
396 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
397 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
398 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
399 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
400 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
401 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
402 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
403 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
404 [MESA_FORMAT_RG88] = 0,
405 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
406 [MESA_FORMAT_GR1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
407 [MESA_FORMAT_RG1616] = 0,
408 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
409 [MESA_FORMAT_Z24_S8] = 0,
410 [MESA_FORMAT_S8_Z24] = 0,
411 [MESA_FORMAT_Z16] = 0,
412 [MESA_FORMAT_X8_Z24] = 0,
413 [MESA_FORMAT_Z24_X8] = 0,
414 [MESA_FORMAT_Z32] = 0,
415 [MESA_FORMAT_S8] = 0,
416
417 [MESA_FORMAT_SRGB8] = 0,
418 [MESA_FORMAT_SRGBA8] = 0,
419 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
420 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
421 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
422 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
423 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
424 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
425 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
426
427 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
428 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
429 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
430 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
431 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
432 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
433
434 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
435 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
436 [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
437 [MESA_FORMAT_RGB_FLOAT16] = 0,
438 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
439 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
440 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
441 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
442 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
443 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
444 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
445 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
446 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
447 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
448 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
449 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
450
451 [MESA_FORMAT_ALPHA_UINT8] = 0,
452 [MESA_FORMAT_ALPHA_UINT16] = 0,
453 [MESA_FORMAT_ALPHA_UINT32] = 0,
454 [MESA_FORMAT_ALPHA_INT8] = 0,
455 [MESA_FORMAT_ALPHA_INT16] = 0,
456 [MESA_FORMAT_ALPHA_INT32] = 0,
457
458 [MESA_FORMAT_INTENSITY_UINT8] = 0,
459 [MESA_FORMAT_INTENSITY_UINT16] = 0,
460 [MESA_FORMAT_INTENSITY_UINT32] = 0,
461 [MESA_FORMAT_INTENSITY_INT8] = 0,
462 [MESA_FORMAT_INTENSITY_INT16] = 0,
463 [MESA_FORMAT_INTENSITY_INT32] = 0,
464
465 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
466 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
467 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
468 [MESA_FORMAT_LUMINANCE_INT8] = 0,
469 [MESA_FORMAT_LUMINANCE_INT16] = 0,
470 [MESA_FORMAT_LUMINANCE_INT32] = 0,
471
472 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
473 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
474 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
475 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
476 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
477 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
478
479 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
480 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
481 [MESA_FORMAT_RGB_INT8] = 0,
482 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
483 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
484 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
485 [MESA_FORMAT_RGB_INT16] = 0,
486 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
487 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
488 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
489 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
490 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
491
492 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
493 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
494 [MESA_FORMAT_RGB_UINT8] = 0,
495 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
496 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
497 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
498 [MESA_FORMAT_RGB_UINT16] = 0,
499 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
500 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
501 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
502 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
503 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
504
505 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
506 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
507 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
508 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
509 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
510 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
511 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
512 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
513 [MESA_FORMAT_SIGNED_RGB_16] = 0,
514 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
515 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
516
517 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
518 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
519 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
520 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
521
522 [MESA_FORMAT_L_LATC1] = 0,
523 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
524 [MESA_FORMAT_LA_LATC2] = 0,
525 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
526
527 [MESA_FORMAT_ETC1_RGB8] = 0,
528 [MESA_FORMAT_ETC2_RGB8] = 0,
529 [MESA_FORMAT_ETC2_SRGB8] = 0,
530 [MESA_FORMAT_ETC2_RGBA8_EAC] = 0,
531 [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = 0,
532 [MESA_FORMAT_ETC2_R11_EAC] = 0,
533 [MESA_FORMAT_ETC2_RG11_EAC] = 0,
534 [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = 0,
535 [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = 0,
536 [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = 0,
537 [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = 0,
538
539 [MESA_FORMAT_SIGNED_A8] = 0,
540 [MESA_FORMAT_SIGNED_L8] = 0,
541 [MESA_FORMAT_SIGNED_AL88] = 0,
542 [MESA_FORMAT_SIGNED_I8] = 0,
543 [MESA_FORMAT_SIGNED_A16] = 0,
544 [MESA_FORMAT_SIGNED_L16] = 0,
545 [MESA_FORMAT_SIGNED_AL1616] = 0,
546 [MESA_FORMAT_SIGNED_I16] = 0,
547
548 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
549 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
550
551 [MESA_FORMAT_Z32_FLOAT] = 0,
552 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
553
554 [MESA_FORMAT_ARGB2101010_UINT] = 0,
555 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
556
557 [MESA_FORMAT_XRGB4444_UNORM] = 0,
558 [MESA_FORMAT_XRGB1555_UNORM] = 0,
559 [MESA_FORMAT_XBGR8888_SNORM] = 0,
560 [MESA_FORMAT_XBGR8888_SRGB] = 0,
561 [MESA_FORMAT_XBGR8888_UINT] = 0,
562 [MESA_FORMAT_XBGR8888_SINT] = 0,
563 [MESA_FORMAT_XRGB2101010_UNORM] = 0,
564 [MESA_FORMAT_XBGR16161616_UNORM] = 0,
565 [MESA_FORMAT_XBGR16161616_SNORM] = 0,
566 [MESA_FORMAT_XBGR16161616_FLOAT] = 0,
567 [MESA_FORMAT_XBGR16161616_UINT] = 0,
568 [MESA_FORMAT_XBGR16161616_SINT] = 0,
569 [MESA_FORMAT_XBGR32323232_FLOAT] = 0,
570 [MESA_FORMAT_XBGR32323232_UINT] = 0,
571 [MESA_FORMAT_XBGR32323232_SINT] = 0,
572 };
573 assert(mesa_format < MESA_FORMAT_COUNT);
574 return table[mesa_format];
575 }
576
577 void
578 brw_init_surface_formats(struct brw_context *brw)
579 {
580 struct intel_context *intel = &brw->intel;
581 struct gl_context *ctx = &intel->ctx;
582 int gen;
583 gl_format format;
584
585 gen = intel->gen * 10;
586 if (intel->is_g4x)
587 gen += 5;
588
589 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
590 uint32_t texture, render;
591 const struct surface_format_info *rinfo, *tinfo;
592 bool is_integer = _mesa_is_format_integer_color(format);
593
594 render = texture = brw_format_for_mesa_format(format);
595 tinfo = &surface_formats[texture];
596
597 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
598 * it.
599 */
600 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
601 continue;
602
603 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
604 ctx->TextureFormatSupported[format] = true;
605
606 /* Re-map some render target formats to make them supported when they
607 * wouldn't be using their format for texturing.
608 */
609 switch (render) {
610 /* For these formats, we just need to read/write the first
611 * channel into R, which is to say that we just treat them as
612 * GL_RED.
613 */
614 case BRW_SURFACEFORMAT_I32_FLOAT:
615 case BRW_SURFACEFORMAT_L32_FLOAT:
616 render = BRW_SURFACEFORMAT_R32_FLOAT;
617 break;
618 case BRW_SURFACEFORMAT_I16_FLOAT:
619 case BRW_SURFACEFORMAT_L16_FLOAT:
620 render = BRW_SURFACEFORMAT_R16_FLOAT;
621 break;
622 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
623 /* XRGB is handled as ARGB because the chips in this family
624 * cannot render to XRGB targets. This means that we have to
625 * mask writes to alpha (ala glColorMask) and reconfigure the
626 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
627 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
628 * used.
629 */
630 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
631 break;
632 }
633
634 rinfo = &surface_formats[render];
635
636 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
637 * integer, so we don't need hardware support for blending on it. Other
638 * than that, GL in general requires alpha blending for render targets,
639 * even though we don't support it for some formats.
640 */
641 if (gen >= rinfo->render_target &&
642 (gen >= rinfo->alpha_blend || is_integer)) {
643 brw->render_target_format[format] = render;
644 brw->format_supported_as_render_target[format] = true;
645 }
646 }
647
648 /* We will check this table for FBO completeness, but the surface format
649 * table above only covered color rendering.
650 */
651 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
652 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
653 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
654 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
655 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
656 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
657
658 /* We remap depth formats to a supported texturing format in
659 * translate_tex_format().
660 */
661 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
662 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
663 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
664 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
665
666 /* It appears that Z16 is slower than Z24 (on Intel Ivybridge and newer
667 * hardware at least), so there's no real reason to prefer it unless you're
668 * under memory (not memory bandwidth) pressure. Our speculation is that
669 * this is due to either increased fragment shader execution from
670 * GL_LEQUAL/GL_EQUAL depth tests at the reduced precision, or due to
671 * increased depth stalls from a cacheline-based heuristic for detecting
672 * depth stalls.
673 *
674 * However, desktop GL 3.0+ require that you get exactly 16 bits when
675 * asking for DEPTH_COMPONENT16, so we have to respect that.
676 */
677 if (_mesa_is_desktop_gl(ctx))
678 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
679
680 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
681 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
682 */
683 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
684
685 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
686 * MESA_FORMAT during glCompressedTexImage2D().
687 * See intel_mipmap_tree::wraps_etc2.
688 */
689 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
690 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
691 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
692 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
693 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
694 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
695 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
696 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
697 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
698 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
699 }
700
701 bool
702 brw_render_target_supported(struct intel_context *intel,
703 struct gl_renderbuffer *rb)
704 {
705 struct brw_context *brw = brw_context(&intel->ctx);
706 gl_format format = rb->Format;
707
708 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
709 * we would consider them renderable even though we don't have surface
710 * support for their alpha behavior and don't have the blending unit
711 * available to fake it like we do for XRGB8888. Force them to being
712 * unsupported.
713 */
714 if ((rb->_BaseFormat != GL_RGBA &&
715 rb->_BaseFormat != GL_RG &&
716 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
717 return false;
718
719 /* Under some conditions, MSAA is not supported for formats whose width is
720 * more than 64 bits.
721 */
722 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
723 /* Gen6: MSAA on >64 bit formats is unsupported. */
724 if (intel->gen <= 6)
725 return false;
726
727 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
728 if (rb->NumSamples >= 8)
729 return false;
730 }
731
732 return brw->format_supported_as_render_target[format];
733 }
734
735 GLuint
736 translate_tex_format(struct intel_context *intel,
737 gl_format mesa_format,
738 GLenum internal_format,
739 GLenum depth_mode,
740 GLenum srgb_decode)
741 {
742 struct gl_context *ctx = &intel->ctx;
743 if (srgb_decode == GL_SKIP_DECODE_EXT)
744 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
745
746 switch( mesa_format ) {
747
748 case MESA_FORMAT_Z16:
749 return BRW_SURFACEFORMAT_I16_UNORM;
750
751 case MESA_FORMAT_S8_Z24:
752 case MESA_FORMAT_X8_Z24:
753 return BRW_SURFACEFORMAT_I24X8_UNORM;
754
755 case MESA_FORMAT_Z32_FLOAT:
756 return BRW_SURFACEFORMAT_I32_FLOAT;
757
758 case MESA_FORMAT_Z32_FLOAT_X24S8:
759 return BRW_SURFACEFORMAT_R32G32_FLOAT;
760
761 case MESA_FORMAT_RGBA_FLOAT32:
762 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
763 * assertion below.
764 */
765 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
766
767 case MESA_FORMAT_SRGB_DXT1:
768 if (intel->gen == 4 && !intel->is_g4x) {
769 /* Work around missing SRGB DXT1 support on original gen4 by just
770 * skipping SRGB decode. It's not worth not supporting sRGB in
771 * general to prevent this.
772 */
773 WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
774 mesa_format = MESA_FORMAT_RGB_DXT1;
775 }
776 return brw_format_for_mesa_format(mesa_format);
777
778 default:
779 assert(brw_format_for_mesa_format(mesa_format) != 0);
780 return brw_format_for_mesa_format(mesa_format);
781 }
782 }
783
784 uint32_t
785 brw_get_surface_tiling_bits(uint32_t tiling)
786 {
787 switch (tiling) {
788 case I915_TILING_X:
789 return BRW_SURFACE_TILED;
790 case I915_TILING_Y:
791 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
792 default:
793 return 0;
794 }
795 }
796
797
798 uint32_t
799 brw_get_surface_num_multisamples(unsigned num_samples)
800 {
801 if (num_samples > 1)
802 return BRW_SURFACE_MULTISAMPLECOUNT_4;
803 else
804 return BRW_SURFACE_MULTISAMPLECOUNT_1;
805 }
806
807
808 /**
809 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
810 * swizzling.
811 */
812 int
813 brw_get_texture_swizzle(const struct gl_context *ctx,
814 const struct gl_texture_object *t)
815 {
816 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
817
818 int swizzles[SWIZZLE_NIL + 1] = {
819 SWIZZLE_X,
820 SWIZZLE_Y,
821 SWIZZLE_Z,
822 SWIZZLE_W,
823 SWIZZLE_ZERO,
824 SWIZZLE_ONE,
825 SWIZZLE_NIL
826 };
827
828 if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
829 img->_BaseFormat == GL_DEPTH_STENCIL) {
830 GLenum depth_mode = t->DepthMode;
831
832 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
833 * with depth component data specified with a sized internal format.
834 * Otherwise, it's left at the old default, GL_LUMINANCE.
835 */
836 if (_mesa_is_gles3(ctx) &&
837 img->InternalFormat != GL_DEPTH_COMPONENT &&
838 img->InternalFormat != GL_DEPTH_STENCIL) {
839 depth_mode = GL_RED;
840 }
841
842 switch (depth_mode) {
843 case GL_ALPHA:
844 swizzles[0] = SWIZZLE_ZERO;
845 swizzles[1] = SWIZZLE_ZERO;
846 swizzles[2] = SWIZZLE_ZERO;
847 swizzles[3] = SWIZZLE_X;
848 break;
849 case GL_LUMINANCE:
850 swizzles[0] = SWIZZLE_X;
851 swizzles[1] = SWIZZLE_X;
852 swizzles[2] = SWIZZLE_X;
853 swizzles[3] = SWIZZLE_ONE;
854 break;
855 case GL_INTENSITY:
856 swizzles[0] = SWIZZLE_X;
857 swizzles[1] = SWIZZLE_X;
858 swizzles[2] = SWIZZLE_X;
859 swizzles[3] = SWIZZLE_X;
860 break;
861 case GL_RED:
862 swizzles[0] = SWIZZLE_X;
863 swizzles[1] = SWIZZLE_ZERO;
864 swizzles[2] = SWIZZLE_ZERO;
865 swizzles[3] = SWIZZLE_ONE;
866 break;
867 }
868 }
869
870 /* If the texture's format is alpha-only, force R, G, and B to
871 * 0.0. Similarly, if the texture's format has no alpha channel,
872 * force the alpha value read to 1.0. This allows for the
873 * implementation to use an RGBA texture for any of these formats
874 * without leaking any unexpected values.
875 */
876 switch (img->_BaseFormat) {
877 case GL_ALPHA:
878 swizzles[0] = SWIZZLE_ZERO;
879 swizzles[1] = SWIZZLE_ZERO;
880 swizzles[2] = SWIZZLE_ZERO;
881 break;
882 case GL_RED:
883 case GL_RG:
884 case GL_RGB:
885 if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0)
886 swizzles[3] = SWIZZLE_ONE;
887 break;
888 }
889
890 return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
891 swizzles[GET_SWZ(t->_Swizzle, 1)],
892 swizzles[GET_SWZ(t->_Swizzle, 2)],
893 swizzles[GET_SWZ(t->_Swizzle, 3)]);
894 }
895
896
897 static void
898 brw_update_buffer_texture_surface(struct gl_context *ctx,
899 unsigned unit,
900 uint32_t *binding_table,
901 unsigned surf_index)
902 {
903 struct brw_context *brw = brw_context(ctx);
904 struct intel_context *intel = &brw->intel;
905 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
906 uint32_t *surf;
907 struct intel_buffer_object *intel_obj =
908 intel_buffer_object(tObj->BufferObject);
909 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
910 gl_format format = tObj->_BufferObjectFormat;
911 uint32_t brw_format = brw_format_for_mesa_format(format);
912 int texel_size = _mesa_get_format_bytes(format);
913
914 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
915 _mesa_problem(NULL, "bad format %s for texture buffer\n",
916 _mesa_get_format_name(format));
917 }
918
919 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
920 6 * 4, 32, &binding_table[surf_index]);
921
922 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
923 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
924
925 if (intel->gen >= 6)
926 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
927
928 if (bo) {
929 surf[1] = bo->offset; /* reloc */
930
931 /* Emit relocation to surface contents. */
932 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
933 binding_table[surf_index] + 4,
934 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
935
936 int w = intel_obj->Base.Size / texel_size;
937 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
938 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
939 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
940 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
941 } else {
942 surf[1] = 0;
943 surf[2] = 0;
944 surf[3] = 0;
945 }
946
947 surf[4] = 0;
948 surf[5] = 0;
949 }
950
951 static void
952 brw_update_texture_surface(struct gl_context *ctx,
953 unsigned unit,
954 uint32_t *binding_table,
955 unsigned surf_index)
956 {
957 struct intel_context *intel = intel_context(ctx);
958 struct brw_context *brw = brw_context(ctx);
959 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
960 struct intel_texture_object *intelObj = intel_texture_object(tObj);
961 struct intel_mipmap_tree *mt = intelObj->mt;
962 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
963 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
964 uint32_t *surf;
965 int width, height, depth;
966 uint32_t tile_x, tile_y;
967
968 if (tObj->Target == GL_TEXTURE_BUFFER) {
969 brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
970 return;
971 }
972
973 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
974
975 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
976 6 * 4, 32, &binding_table[surf_index]);
977
978 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
979 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
980 BRW_SURFACE_CUBEFACE_ENABLES |
981 (translate_tex_format(intel,
982 mt->format,
983 firstImage->InternalFormat,
984 tObj->DepthMode,
985 sampler->sRGBDecode) <<
986 BRW_SURFACE_FORMAT_SHIFT));
987
988 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
989
990 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
991 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
992 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
993
994 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
995 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
996 (intelObj->mt->region->pitch - 1) <<
997 BRW_SURFACE_PITCH_SHIFT);
998
999 surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
1000
1001 intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
1002 &tile_x, &tile_y);
1003 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1004 /* Note that the low bits of these fields are missing, so
1005 * there's the possibility of getting in trouble.
1006 */
1007 assert(tile_x % 4 == 0);
1008 assert(tile_y % 2 == 0);
1009 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1010 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1011 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1012
1013 /* Emit relocation to surface contents */
1014 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1015 binding_table[surf_index] + 4,
1016 intelObj->mt->region->bo,
1017 intelObj->mt->offset,
1018 I915_GEM_DOMAIN_SAMPLER, 0);
1019 }
1020
1021 /**
1022 * Create the constant buffer surface. Vertex/fragment shader constants will be
1023 * read from this buffer with Data Port Read instructions/messages.
1024 */
1025 static void
1026 brw_create_constant_surface(struct brw_context *brw,
1027 drm_intel_bo *bo,
1028 uint32_t offset,
1029 uint32_t size,
1030 uint32_t *out_offset,
1031 bool dword_pitch)
1032 {
1033 struct intel_context *intel = &brw->intel;
1034 uint32_t stride = dword_pitch ? 4 : 16;
1035 uint32_t elements = ALIGN(size, stride) / stride;
1036 const GLint w = elements - 1;
1037 uint32_t *surf;
1038
1039 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1040 6 * 4, 32, out_offset);
1041
1042 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1043 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1044 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
1045
1046 if (intel->gen >= 6)
1047 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
1048
1049 surf[1] = bo->offset + offset; /* reloc */
1050
1051 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
1052 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
1053
1054 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
1055 (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
1056
1057 surf[4] = 0;
1058 surf[5] = 0;
1059
1060 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
1061 * bspec ("Data Cache") says that the data cache does not exist as
1062 * a separate cache and is just the sampler cache.
1063 */
1064 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1065 *out_offset + 4,
1066 bo, offset,
1067 I915_GEM_DOMAIN_SAMPLER, 0);
1068 }
1069
1070 /**
1071 * Set up a binding table entry for use by stream output logic (transform
1072 * feedback).
1073 *
1074 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
1075 */
1076 void
1077 brw_update_sol_surface(struct brw_context *brw,
1078 struct gl_buffer_object *buffer_obj,
1079 uint32_t *out_offset, unsigned num_vector_components,
1080 unsigned stride_dwords, unsigned offset_dwords)
1081 {
1082 struct intel_context *intel = &brw->intel;
1083 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
1084 drm_intel_bo *bo =
1085 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
1086 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
1087 out_offset);
1088 uint32_t pitch_minus_1 = 4*stride_dwords - 1;
1089 uint32_t offset_bytes = 4 * offset_dwords;
1090 size_t size_dwords = buffer_obj->Size / 4;
1091 uint32_t buffer_size_minus_1, width, height, depth, surface_format;
1092
1093 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
1094 * too big to map using a single binding table entry?
1095 */
1096 assert((size_dwords - offset_dwords) / stride_dwords
1097 <= BRW_MAX_NUM_BUFFER_ENTRIES);
1098
1099 if (size_dwords > offset_dwords + num_vector_components) {
1100 /* There is room for at least 1 transform feedback output in the buffer.
1101 * Compute the number of additional transform feedback outputs the
1102 * buffer has room for.
1103 */
1104 buffer_size_minus_1 =
1105 (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
1106 } else {
1107 /* There isn't even room for a single transform feedback output in the
1108 * buffer. We can't configure the binding table entry to prevent output
1109 * entirely; we'll have to rely on the geometry shader to detect
1110 * overflow. But to minimize the damage in case of a bug, set up the
1111 * binding table entry to just allow a single output.
1112 */
1113 buffer_size_minus_1 = 0;
1114 }
1115 width = buffer_size_minus_1 & 0x7f;
1116 height = (buffer_size_minus_1 & 0xfff80) >> 7;
1117 depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
1118
1119 switch (num_vector_components) {
1120 case 1:
1121 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1122 break;
1123 case 2:
1124 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1125 break;
1126 case 3:
1127 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1128 break;
1129 case 4:
1130 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
1131 break;
1132 default:
1133 assert(!"Invalid vector size for transform feedback output");
1134 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1135 break;
1136 }
1137
1138 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1139 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1140 surface_format << BRW_SURFACE_FORMAT_SHIFT |
1141 BRW_SURFACE_RC_READ_WRITE;
1142 surf[1] = bo->offset + offset_bytes; /* reloc */
1143 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
1144 height << BRW_SURFACE_HEIGHT_SHIFT);
1145 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1146 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1147 surf[4] = 0;
1148 surf[5] = 0;
1149
1150 /* Emit relocation to surface contents. */
1151 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1152 *out_offset + 4,
1153 bo, offset_bytes,
1154 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1155 }
1156
1157 /* Creates a new WM constant buffer reflecting the current fragment program's
1158 * constants, if needed by the fragment program.
1159 *
1160 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
1161 * state atom.
1162 */
1163 static void
1164 brw_upload_wm_pull_constants(struct brw_context *brw)
1165 {
1166 struct gl_context *ctx = &brw->intel.ctx;
1167 struct intel_context *intel = &brw->intel;
1168 /* BRW_NEW_FRAGMENT_PROGRAM */
1169 struct brw_fragment_program *fp =
1170 (struct brw_fragment_program *) brw->fragment_program;
1171 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1172 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1173 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1174 float *constants;
1175 unsigned int i;
1176
1177 _mesa_load_state_parameters(ctx, params);
1178
1179 /* CACHE_NEW_WM_PROG */
1180 if (brw->wm.prog_data->nr_pull_params == 0) {
1181 if (brw->wm.const_bo) {
1182 drm_intel_bo_unreference(brw->wm.const_bo);
1183 brw->wm.const_bo = NULL;
1184 brw->wm.surf_offset[surf_index] = 0;
1185 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1186 }
1187 return;
1188 }
1189
1190 drm_intel_bo_unreference(brw->wm.const_bo);
1191 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1192 size, 64);
1193
1194 /* _NEW_PROGRAM_CONSTANTS */
1195 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1196 constants = brw->wm.const_bo->virtual;
1197 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1198 constants[i] = *brw->wm.prog_data->pull_param[i];
1199 }
1200 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1201
1202 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
1203 &brw->wm.surf_offset[surf_index],
1204 true);
1205
1206 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1207 }
1208
1209 const struct brw_tracked_state brw_wm_pull_constants = {
1210 .dirty = {
1211 .mesa = (_NEW_PROGRAM_CONSTANTS),
1212 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1213 .cache = CACHE_NEW_WM_PROG,
1214 },
1215 .emit = brw_upload_wm_pull_constants,
1216 };
1217
1218 static void
1219 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1220 {
1221 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1222 * Notes):
1223 *
1224 * A null surface will be used in instances where an actual surface is
1225 * not bound. When a write message is generated to a null surface, no
1226 * actual surface is written to. When a read message (including any
1227 * sampling engine message) is generated to a null surface, the result
1228 * is all zeros. Note that a null surface type is allowed to be used
1229 * with all messages, even if it is not specificially indicated as
1230 * supported. All of the remaining fields in surface state are ignored
1231 * for null surfaces, with the following exceptions:
1232 *
1233 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1234 * depth buffer’s corresponding state for all render target surfaces,
1235 * including null.
1236 *
1237 * - Surface Format must be R8G8B8A8_UNORM.
1238 */
1239 struct intel_context *intel = &brw->intel;
1240 struct gl_context *ctx = &intel->ctx;
1241 uint32_t *surf;
1242 unsigned surface_type = BRW_SURFACE_NULL;
1243 drm_intel_bo *bo = NULL;
1244 unsigned pitch_minus_1 = 0;
1245 uint32_t multisampling_state = 0;
1246
1247 /* _NEW_BUFFERS */
1248 const struct gl_framebuffer *fb = ctx->DrawBuffer;
1249
1250 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1251 6 * 4, 32, &brw->wm.surf_offset[unit]);
1252
1253 if (fb->Visual.samples > 1) {
1254 /* On Gen6, null render targets seem to cause GPU hangs when
1255 * multisampling. So work around this problem by rendering into dummy
1256 * color buffer.
1257 *
1258 * To decrease the amount of memory needed by the workaround buffer, we
1259 * set its pitch to 128 bytes (the width of a Y tile). This means that
1260 * the amount of memory needed for the workaround buffer is
1261 * (width_in_tiles + height_in_tiles - 1) tiles.
1262 *
1263 * Note that since the workaround buffer will be interpreted by the
1264 * hardware as an interleaved multisampled buffer, we need to compute
1265 * width_in_tiles and height_in_tiles by dividing the width and height
1266 * by 16 rather than the normal Y-tile size of 32.
1267 */
1268 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1269 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1270 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1271 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1272 size_needed);
1273 bo = brw->wm.multisampled_null_render_target_bo;
1274 surface_type = BRW_SURFACE_2D;
1275 pitch_minus_1 = 127;
1276 multisampling_state =
1277 brw_get_surface_num_multisamples(fb->Visual.samples);
1278 }
1279
1280 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1281 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1282 if (intel->gen < 6) {
1283 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1284 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1285 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1286 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1287 }
1288 surf[1] = bo ? bo->offset : 0;
1289 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1290 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1291
1292 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1293 * Notes):
1294 *
1295 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
1296 */
1297 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1298 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1299 surf[4] = multisampling_state;
1300 surf[5] = 0;
1301
1302 if (bo) {
1303 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1304 brw->wm.surf_offset[unit] + 4,
1305 bo, 0,
1306 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1307 }
1308 }
1309
1310 /**
1311 * Sets up a surface state structure to point at the given region.
1312 * While it is only used for the front/back buffer currently, it should be
1313 * usable for further buffers when doing ARB_draw_buffer support.
1314 */
1315 static void
1316 brw_update_renderbuffer_surface(struct brw_context *brw,
1317 struct gl_renderbuffer *rb,
1318 unsigned int unit)
1319 {
1320 struct intel_context *intel = &brw->intel;
1321 struct gl_context *ctx = &intel->ctx;
1322 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1323 struct intel_mipmap_tree *mt = irb->mt;
1324 struct intel_region *region;
1325 uint32_t *surf;
1326 uint32_t tile_x, tile_y;
1327 uint32_t format = 0;
1328 /* _NEW_BUFFERS */
1329 gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
1330
1331 if (irb->tex_image && !brw->has_surface_tile_offset) {
1332 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1333
1334 if (tile_x != 0 || tile_y != 0) {
1335 /* Original gen4 hardware couldn't draw to a non-tile-aligned
1336 * destination in a miptree unless you actually setup your renderbuffer
1337 * as a miptree and used the fragile lod/array_index/etc. controls to
1338 * select the image. So, instead, we just make a new single-level
1339 * miptree and render into that.
1340 */
1341 intel_renderbuffer_move_to_temp(intel, irb, false);
1342 mt = irb->mt;
1343 }
1344 }
1345
1346 region = irb->mt->region;
1347
1348 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1349 6 * 4, 32, &brw->wm.surf_offset[unit]);
1350
1351 format = brw->render_target_format[rb_format];
1352 if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1353 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1354 __FUNCTION__, _mesa_get_format_name(rb_format));
1355 }
1356
1357 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1358 format << BRW_SURFACE_FORMAT_SHIFT);
1359
1360 /* reloc */
1361 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1362 region->bo->offset);
1363
1364 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1365 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1366
1367 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1368 (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1369
1370 surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1371
1372 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1373 /* Note that the low bits of these fields are missing, so
1374 * there's the possibility of getting in trouble.
1375 */
1376 assert(tile_x % 4 == 0);
1377 assert(tile_y % 2 == 0);
1378 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1379 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1380 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1381
1382 if (intel->gen < 6) {
1383 /* _NEW_COLOR */
1384 if (!ctx->Color.ColorLogicOpEnabled &&
1385 (ctx->Color.BlendEnabled & (1 << unit)))
1386 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1387
1388 if (!ctx->Color.ColorMask[unit][0])
1389 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1390 if (!ctx->Color.ColorMask[unit][1])
1391 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1392 if (!ctx->Color.ColorMask[unit][2])
1393 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1394
1395 /* As mentioned above, disable writes to the alpha component when the
1396 * renderbuffer is XRGB.
1397 */
1398 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1399 !ctx->Color.ColorMask[unit][3]) {
1400 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1401 }
1402 }
1403
1404 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1405 brw->wm.surf_offset[unit] + 4,
1406 region->bo,
1407 surf[1] - region->bo->offset,
1408 I915_GEM_DOMAIN_RENDER,
1409 I915_GEM_DOMAIN_RENDER);
1410 }
1411
1412 /**
1413 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1414 */
1415 static void
1416 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1417 {
1418 struct intel_context *intel = &brw->intel;
1419 struct gl_context *ctx = &brw->intel.ctx;
1420 GLuint i;
1421
1422 /* _NEW_BUFFERS | _NEW_COLOR */
1423 /* Update surfaces for drawing buffers */
1424 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1425 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1426 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1427 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1428 } else {
1429 intel->vtbl.update_null_renderbuffer_surface(brw, i);
1430 }
1431 }
1432 } else {
1433 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1434 }
1435 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1436 }
1437
1438 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1439 .dirty = {
1440 .mesa = (_NEW_COLOR |
1441 _NEW_BUFFERS),
1442 .brw = BRW_NEW_BATCH,
1443 .cache = 0
1444 },
1445 .emit = brw_update_renderbuffer_surfaces,
1446 };
1447
1448 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1449 .dirty = {
1450 .mesa = _NEW_BUFFERS,
1451 .brw = BRW_NEW_BATCH,
1452 .cache = 0
1453 },
1454 .emit = brw_update_renderbuffer_surfaces,
1455 };
1456
1457 /**
1458 * Construct SURFACE_STATE objects for enabled textures.
1459 */
1460 static void
1461 brw_update_texture_surfaces(struct brw_context *brw)
1462 {
1463 struct intel_context *intel = &brw->intel;
1464 struct gl_context *ctx = &intel->ctx;
1465
1466 /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1467 * Unfortunately, we're stuck using the gl_program structs until the
1468 * ARB_fragment_program front-end gets converted to GLSL IR. These
1469 * have the downside that SamplerUnits is split and only contains the
1470 * mappings for samplers active in that stage.
1471 */
1472 struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1473 struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1474
1475 unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1476
1477 for (unsigned s = 0; s < num_samplers; s++) {
1478 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1479 brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1480
1481 if (vs->SamplersUsed & (1 << s)) {
1482 const unsigned unit = vs->SamplerUnits[s];
1483
1484 /* _NEW_TEXTURE */
1485 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1486 intel->vtbl.update_texture_surface(ctx, unit,
1487 brw->vs.surf_offset,
1488 SURF_INDEX_VS_TEXTURE(s));
1489 }
1490 }
1491
1492 if (fs->SamplersUsed & (1 << s)) {
1493 const unsigned unit = fs->SamplerUnits[s];
1494
1495 /* _NEW_TEXTURE */
1496 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1497 intel->vtbl.update_texture_surface(ctx, unit,
1498 brw->wm.surf_offset,
1499 SURF_INDEX_TEXTURE(s));
1500 }
1501 }
1502 }
1503
1504 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1505 }
1506
1507 const struct brw_tracked_state brw_texture_surfaces = {
1508 .dirty = {
1509 .mesa = _NEW_TEXTURE,
1510 .brw = BRW_NEW_BATCH |
1511 BRW_NEW_VERTEX_PROGRAM |
1512 BRW_NEW_FRAGMENT_PROGRAM,
1513 .cache = 0
1514 },
1515 .emit = brw_update_texture_surfaces,
1516 };
1517
1518 void
1519 brw_upload_ubo_surfaces(struct brw_context *brw,
1520 struct gl_shader *shader,
1521 uint32_t *surf_offsets)
1522 {
1523 struct gl_context *ctx = &brw->intel.ctx;
1524 struct intel_context *intel = &brw->intel;
1525
1526 if (!shader)
1527 return;
1528
1529 for (int i = 0; i < shader->NumUniformBlocks; i++) {
1530 struct gl_uniform_buffer_binding *binding;
1531 struct intel_buffer_object *intel_bo;
1532
1533 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1534 intel_bo = intel_buffer_object(binding->BufferObject);
1535 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1536
1537 /* Because behavior for referencing outside of the binding's size in the
1538 * glBindBufferRange case is undefined, we can just bind the whole buffer
1539 * glBindBufferBase wants and be a correct implementation.
1540 */
1541 intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1542 bo->size - binding->Offset,
1543 &surf_offsets[i],
1544 shader->Type == GL_FRAGMENT_SHADER);
1545 }
1546
1547 if (shader->NumUniformBlocks)
1548 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1549 }
1550
1551 static void
1552 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1553 {
1554 struct gl_context *ctx = &brw->intel.ctx;
1555 /* _NEW_PROGRAM */
1556 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1557
1558 if (!prog)
1559 return;
1560
1561 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1562 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1563 }
1564
1565 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1566 .dirty = {
1567 .mesa = (_NEW_PROGRAM |
1568 _NEW_BUFFER_OBJECT),
1569 .brw = BRW_NEW_BATCH,
1570 .cache = 0,
1571 },
1572 .emit = brw_upload_wm_ubo_surfaces,
1573 };
1574
1575 /**
1576 * Constructs the binding table for the WM surface state, which maps unit
1577 * numbers to surface state objects.
1578 */
1579 static void
1580 brw_upload_wm_binding_table(struct brw_context *brw)
1581 {
1582 uint32_t *bind;
1583 int i;
1584
1585 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1586 gen7_create_shader_time_surface(brw, &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1587 }
1588
1589 /* Might want to calculate nr_surfaces first, to avoid taking up so much
1590 * space for the binding table.
1591 */
1592 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1593 sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1594 32, &brw->wm.bind_bo_offset);
1595
1596 /* BRW_NEW_SURFACES */
1597 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1598 bind[i] = brw->wm.surf_offset[i];
1599 }
1600
1601 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1602 }
1603
1604 const struct brw_tracked_state brw_wm_binding_table = {
1605 .dirty = {
1606 .mesa = 0,
1607 .brw = (BRW_NEW_BATCH |
1608 BRW_NEW_SURFACES),
1609 .cache = 0
1610 },
1611 .emit = brw_upload_wm_binding_table,
1612 };
1613
1614 void
1615 gen4_init_vtable_surface_functions(struct brw_context *brw)
1616 {
1617 struct intel_context *intel = &brw->intel;
1618
1619 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1620 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1621 intel->vtbl.update_null_renderbuffer_surface =
1622 brw_update_null_renderbuffer_surface;
1623 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1624 }