2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/texstore.h"
35 #include "shader/prog_parameter.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
47 static GLuint
translate_tex_target( GLenum target
)
51 return BRW_SURFACE_1D
;
53 case GL_TEXTURE_RECTANGLE_NV
:
54 return BRW_SURFACE_2D
;
57 return BRW_SURFACE_2D
;
60 return BRW_SURFACE_3D
;
62 case GL_TEXTURE_CUBE_MAP
:
63 return BRW_SURFACE_CUBE
;
72 static GLuint
translate_tex_format( gl_format mesa_format
,
73 GLenum internal_format
,
76 switch( mesa_format
) {
78 return BRW_SURFACEFORMAT_L8_UNORM
;
81 return BRW_SURFACEFORMAT_I8_UNORM
;
84 return BRW_SURFACEFORMAT_A8_UNORM
;
86 case MESA_FORMAT_AL88
:
87 return BRW_SURFACEFORMAT_L8A8_UNORM
;
89 case MESA_FORMAT_AL1616
:
90 return BRW_SURFACEFORMAT_L16A16_UNORM
;
92 case MESA_FORMAT_RGB888
:
93 assert(0); /* not supported for sampling */
94 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
96 case MESA_FORMAT_ARGB8888
:
97 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
99 case MESA_FORMAT_XRGB8888
:
100 return BRW_SURFACEFORMAT_B8G8R8X8_UNORM
;
102 case MESA_FORMAT_RGBA8888_REV
:
103 _mesa_problem(NULL
, "unexpected format in i965:translate_tex_format()");
104 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
106 case MESA_FORMAT_RGB565
:
107 return BRW_SURFACEFORMAT_B5G6R5_UNORM
;
109 case MESA_FORMAT_ARGB1555
:
110 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
112 case MESA_FORMAT_ARGB4444
:
113 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
115 case MESA_FORMAT_YCBCR_REV
:
116 return BRW_SURFACEFORMAT_YCRCB_NORMAL
;
118 case MESA_FORMAT_YCBCR
:
119 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY
;
121 case MESA_FORMAT_RGB_FXT1
:
122 case MESA_FORMAT_RGBA_FXT1
:
123 return BRW_SURFACEFORMAT_FXT1
;
125 case MESA_FORMAT_Z16
:
126 if (depth_mode
== GL_INTENSITY
)
127 return BRW_SURFACEFORMAT_I16_UNORM
;
128 else if (depth_mode
== GL_ALPHA
)
129 return BRW_SURFACEFORMAT_A16_UNORM
;
131 return BRW_SURFACEFORMAT_L16_UNORM
;
133 case MESA_FORMAT_RGB_DXT1
:
134 return BRW_SURFACEFORMAT_DXT1_RGB
;
136 case MESA_FORMAT_RGBA_DXT1
:
137 return BRW_SURFACEFORMAT_BC1_UNORM
;
139 case MESA_FORMAT_RGBA_DXT3
:
140 return BRW_SURFACEFORMAT_BC2_UNORM
;
142 case MESA_FORMAT_RGBA_DXT5
:
143 return BRW_SURFACEFORMAT_BC3_UNORM
;
145 case MESA_FORMAT_SARGB8
:
146 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
;
148 case MESA_FORMAT_SLA8
:
149 return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB
;
151 case MESA_FORMAT_SL8
:
152 return BRW_SURFACEFORMAT_L8_UNORM_SRGB
;
154 case MESA_FORMAT_SRGB_DXT1
:
155 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB
;
157 case MESA_FORMAT_S8_Z24
:
158 /* XXX: these different surface formats don't seem to
159 * make any difference for shadow sampler/compares.
161 if (depth_mode
== GL_INTENSITY
)
162 return BRW_SURFACEFORMAT_I24X8_UNORM
;
163 else if (depth_mode
== GL_ALPHA
)
164 return BRW_SURFACEFORMAT_A24X8_UNORM
;
166 return BRW_SURFACEFORMAT_L24X8_UNORM
;
168 case MESA_FORMAT_DUDV8
:
169 return BRW_SURFACEFORMAT_R8G8_SNORM
;
171 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
172 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM
;
181 brw_set_surface_tiling(struct brw_surface_state
*surf
, uint32_t tiling
)
184 case I915_TILING_NONE
:
185 surf
->ss3
.tiled_surface
= 0;
186 surf
->ss3
.tile_walk
= 0;
189 surf
->ss3
.tiled_surface
= 1;
190 surf
->ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
193 surf
->ss3
.tiled_surface
= 1;
194 surf
->ss3
.tile_walk
= BRW_TILEWALK_YMAJOR
;
200 brw_create_texture_surface( struct brw_context
*brw
,
201 struct brw_surface_key
*key
)
203 struct brw_surface_state surf
;
206 memset(&surf
, 0, sizeof(surf
));
208 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
209 surf
.ss0
.surface_type
= translate_tex_target(key
->target
);
210 surf
.ss0
.surface_format
= translate_tex_format(key
->format
,
211 key
->internal_format
,
214 /* This is ok for all textures with channel width 8bit or less:
216 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
217 surf
.ss1
.base_addr
= key
->bo
->offset
; /* reloc */
219 surf
.ss2
.mip_count
= key
->last_level
- key
->first_level
;
220 surf
.ss2
.width
= key
->width
- 1;
221 surf
.ss2
.height
= key
->height
- 1;
222 brw_set_surface_tiling(&surf
, key
->tiling
);
223 surf
.ss3
.pitch
= (key
->pitch
* key
->cpp
) - 1;
224 surf
.ss3
.depth
= key
->depth
- 1;
226 surf
.ss4
.min_lod
= 0;
228 if (key
->target
== GL_TEXTURE_CUBE_MAP
) {
229 surf
.ss0
.cube_pos_x
= 1;
230 surf
.ss0
.cube_pos_y
= 1;
231 surf
.ss0
.cube_pos_z
= 1;
232 surf
.ss0
.cube_neg_x
= 1;
233 surf
.ss0
.cube_neg_y
= 1;
234 surf
.ss0
.cube_neg_z
= 1;
237 bo
= brw_upload_cache(&brw
->surface_cache
, BRW_SS_SURFACE
,
240 &surf
, sizeof(surf
));
242 /* Emit relocation to surface contents */
243 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_surface_state
, ss1
),
245 I915_GEM_DOMAIN_SAMPLER
, 0);
251 brw_update_texture_surface( GLcontext
*ctx
, GLuint unit
)
253 struct brw_context
*brw
= brw_context(ctx
);
254 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
255 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
256 struct gl_texture_image
*firstImage
= tObj
->Image
[0][intelObj
->firstLevel
];
257 struct brw_surface_key key
;
258 const GLuint surf
= SURF_INDEX_TEXTURE(unit
);
260 memset(&key
, 0, sizeof(key
));
262 key
.format
= firstImage
->TexFormat
;
263 key
.internal_format
= firstImage
->InternalFormat
;
264 key
.pitch
= intelObj
->mt
->region
->pitch
;
265 key
.depth
= firstImage
->Depth
;
266 key
.bo
= intelObj
->mt
->region
->buffer
;
269 key
.target
= tObj
->Target
;
270 key
.depthmode
= tObj
->DepthMode
;
271 key
.first_level
= intelObj
->firstLevel
;
272 key
.last_level
= intelObj
->lastLevel
;
273 key
.width
= firstImage
->Width
;
274 key
.height
= firstImage
->Height
;
275 key
.cpp
= intelObj
->mt
->cpp
;
276 key
.tiling
= intelObj
->mt
->region
->tiling
;
278 dri_bo_unreference(brw
->wm
.surf_bo
[surf
]);
279 brw
->wm
.surf_bo
[surf
] = brw_search_cache(&brw
->surface_cache
,
284 if (brw
->wm
.surf_bo
[surf
] == NULL
) {
285 brw
->wm
.surf_bo
[surf
] = brw_create_texture_surface(brw
, &key
);
292 * Create the constant buffer surface. Vertex/fragment shader constants will be
293 * read from this buffer with Data Port Read instructions/messages.
296 brw_create_constant_surface( struct brw_context
*brw
,
297 struct brw_surface_key
*key
)
299 const GLint w
= key
->width
- 1;
300 struct brw_surface_state surf
;
303 memset(&surf
, 0, sizeof(surf
));
305 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
306 surf
.ss0
.surface_type
= BRW_SURFACE_BUFFER
;
307 surf
.ss0
.surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
310 surf
.ss1
.base_addr
= key
->bo
->offset
; /* reloc */
312 surf
.ss2
.width
= w
& 0x7f; /* bits 6:0 of size or width */
313 surf
.ss2
.height
= (w
>> 7) & 0x1fff; /* bits 19:7 of size or width */
314 surf
.ss3
.depth
= (w
>> 20) & 0x7f; /* bits 26:20 of size or width */
315 surf
.ss3
.pitch
= (key
->pitch
* key
->cpp
) - 1; /* ignored?? */
316 brw_set_surface_tiling(&surf
, key
->tiling
); /* tiling now allowed */
318 bo
= brw_upload_cache(&brw
->surface_cache
, BRW_SS_SURFACE
,
321 &surf
, sizeof(surf
));
323 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
324 * bspec ("Data Cache") says that the data cache does not exist as
325 * a separate cache and is just the sampler cache.
327 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_surface_state
, ss1
),
329 I915_GEM_DOMAIN_SAMPLER
, 0);
334 /* Creates a new WM constant buffer reflecting the current fragment program's
335 * constants, if needed by the fragment program.
337 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
340 static drm_intel_bo
*
341 brw_wm_update_constant_buffer(struct brw_context
*brw
)
343 struct intel_context
*intel
= &brw
->intel
;
344 struct brw_fragment_program
*fp
=
345 (struct brw_fragment_program
*) brw
->fragment_program
;
346 const struct gl_program_parameter_list
*params
= fp
->program
.Base
.Parameters
;
347 const int size
= params
->NumParameters
* 4 * sizeof(GLfloat
);
348 drm_intel_bo
*const_buffer
;
350 /* BRW_NEW_FRAGMENT_PROGRAM */
351 if (!fp
->use_const_buffer
)
354 const_buffer
= drm_intel_bo_alloc(intel
->bufmgr
, "fp_const_buffer",
357 /* _NEW_PROGRAM_CONSTANTS */
358 dri_bo_subdata(const_buffer
, 0, size
, params
->ParameterValues
);
364 * Update the surface state for a WM constant buffer.
365 * The constant buffer will be (re)allocated here if needed.
368 brw_update_wm_constant_surface( GLcontext
*ctx
,
371 struct brw_context
*brw
= brw_context(ctx
);
372 struct brw_surface_key key
;
373 struct brw_fragment_program
*fp
=
374 (struct brw_fragment_program
*) brw
->fragment_program
;
375 const struct gl_program_parameter_list
*params
=
376 fp
->program
.Base
.Parameters
;
378 /* If we're in this state update atom, we need to update WM constants, so
379 * free the old buffer and create a new one for the new contents.
381 dri_bo_unreference(fp
->const_buffer
);
382 fp
->const_buffer
= brw_wm_update_constant_buffer(brw
);
384 /* If there's no constant buffer, then no surface BO is needed to point at
387 if (fp
->const_buffer
== NULL
) {
388 drm_intel_bo_unreference(brw
->wm
.surf_bo
[surf
]);
389 brw
->wm
.surf_bo
[surf
] = NULL
;
393 memset(&key
, 0, sizeof(key
));
395 key
.format
= MESA_FORMAT_RGBA_FLOAT32
;
396 key
.internal_format
= GL_RGBA
;
397 key
.bo
= fp
->const_buffer
;
398 key
.depthmode
= GL_NONE
;
399 key
.pitch
= params
->NumParameters
;
400 key
.width
= params
->NumParameters
;
406 printf("%s:\n", __FUNCTION__);
407 printf(" width %d height %d depth %d cpp %d pitch %d\n",
408 key.width, key.height, key.depth, key.cpp, key.pitch);
411 dri_bo_unreference(brw
->wm
.surf_bo
[surf
]);
412 brw
->wm
.surf_bo
[surf
] = brw_search_cache(&brw
->surface_cache
,
417 if (brw
->wm
.surf_bo
[surf
] == NULL
) {
418 brw
->wm
.surf_bo
[surf
] = brw_create_constant_surface(brw
, &key
);
420 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
424 * Updates surface / buffer for fragment shader constant buffer, if
427 * This consumes the state updates for the constant buffer, and produces
428 * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
429 * inclusion in the binding table.
431 static void prepare_wm_constant_surface(struct brw_context
*brw
)
433 GLcontext
*ctx
= &brw
->intel
.ctx
;
434 struct brw_fragment_program
*fp
=
435 (struct brw_fragment_program
*) brw
->fragment_program
;
436 GLuint surf
= SURF_INDEX_FRAG_CONST_BUFFER
;
438 drm_intel_bo_unreference(fp
->const_buffer
);
439 fp
->const_buffer
= brw_wm_update_constant_buffer(brw
);
441 /* If there's no constant buffer, then no surface BO is needed to point at
444 if (fp
->const_buffer
== 0) {
445 if (brw
->wm
.surf_bo
[surf
] != NULL
) {
446 drm_intel_bo_unreference(brw
->wm
.surf_bo
[surf
]);
447 brw
->wm
.surf_bo
[surf
] = NULL
;
448 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
453 brw_update_wm_constant_surface(ctx
, surf
);
456 const struct brw_tracked_state brw_wm_constant_surface
= {
458 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
459 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
),
462 .prepare
= prepare_wm_constant_surface
,
467 * Sets up a surface state structure to point at the given region.
468 * While it is only used for the front/back buffer currently, it should be
469 * usable for further buffers when doing ARB_draw_buffer support.
472 brw_update_renderbuffer_surface(struct brw_context
*brw
,
473 struct gl_renderbuffer
*rb
,
476 struct intel_context
*intel
= &brw
->intel
;
477 GLcontext
*ctx
= &intel
->ctx
;
478 dri_bo
*region_bo
= NULL
;
479 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
480 struct intel_region
*region
= irb
? irb
->region
: NULL
;
482 unsigned int surface_type
;
483 unsigned int surface_format
;
484 unsigned int width
, height
, pitch
, cpp
;
485 GLubyte color_mask
[4];
486 GLboolean color_blend
;
492 memset(&key
, 0, sizeof(key
));
494 if (region
!= NULL
) {
495 region_bo
= region
->buffer
;
497 key
.surface_type
= BRW_SURFACE_2D
;
498 switch (irb
->Base
.Format
) {
499 /* XRGB and ARGB are treated the same here because the chips in this
500 * family cannot render to XRGB targets. This means that we have to
501 * mask writes to alpha (ala glColorMask) and reconfigure the alpha
502 * blending hardware to use GL_ONE (or GL_ZERO) for cases where
503 * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
505 case MESA_FORMAT_ARGB8888
:
506 case MESA_FORMAT_XRGB8888
:
507 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
509 case MESA_FORMAT_RGB565
:
510 key
.surface_format
= BRW_SURFACEFORMAT_B5G6R5_UNORM
;
512 case MESA_FORMAT_ARGB1555
:
513 key
.surface_format
= BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
515 case MESA_FORMAT_ARGB4444
:
516 key
.surface_format
= BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
519 _mesa_problem(ctx
, "Bad renderbuffer format: %d\n", irb
->Base
.Format
);
521 key
.tiling
= region
->tiling
;
522 if (brw
->intel
.intelScreen
->driScrnPriv
->dri2
.enabled
) {
523 key
.width
= rb
->Width
;
524 key
.height
= rb
->Height
;
526 key
.width
= region
->width
;
527 key
.height
= region
->height
;
529 key
.pitch
= region
->pitch
;
530 key
.cpp
= region
->cpp
;
531 key
.draw_x
= region
->draw_x
;
532 key
.draw_y
= region
->draw_y
;
534 key
.surface_type
= BRW_SURFACE_NULL
;
535 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
536 key
.tiling
= I915_TILING_X
;
544 if (intel
->gen
< 6) {
546 memcpy(key
.color_mask
, ctx
->Color
.ColorMask
[unit
],
547 sizeof(key
.color_mask
));
549 /* As mentioned above, disable writes to the alpha component when the
550 * renderbuffer is XRGB.
552 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0)
553 key
.color_mask
[3] = GL_FALSE
;
555 key
.color_blend
= (!ctx
->Color
._LogicOpEnabled
&&
556 (ctx
->Color
.BlendEnabled
& (1 << unit
)));
559 dri_bo_unreference(brw
->wm
.surf_bo
[unit
]);
560 brw
->wm
.surf_bo
[unit
] = brw_search_cache(&brw
->surface_cache
,
566 if (brw
->wm
.surf_bo
[unit
] == NULL
) {
567 struct brw_surface_state surf
;
569 memset(&surf
, 0, sizeof(surf
));
571 surf
.ss0
.surface_format
= key
.surface_format
;
572 surf
.ss0
.surface_type
= key
.surface_type
;
573 if (key
.tiling
== I915_TILING_NONE
) {
574 surf
.ss1
.base_addr
= (key
.draw_x
+ key
.draw_y
* key
.pitch
) * key
.cpp
;
576 uint32_t tile_base
, tile_x
, tile_y
;
577 uint32_t pitch
= key
.pitch
* key
.cpp
;
579 if (key
.tiling
== I915_TILING_X
) {
580 tile_x
= key
.draw_x
% (512 / key
.cpp
);
581 tile_y
= key
.draw_y
% 8;
582 tile_base
= ((key
.draw_y
/ 8) * (8 * pitch
));
583 tile_base
+= (key
.draw_x
- tile_x
) / (512 / key
.cpp
) * 4096;
586 tile_x
= key
.draw_x
% (128 / key
.cpp
);
587 tile_y
= key
.draw_y
% 32;
588 tile_base
= ((key
.draw_y
/ 32) * (32 * pitch
));
589 tile_base
+= (key
.draw_x
- tile_x
) / (128 / key
.cpp
) * 4096;
591 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
592 assert(tile_x
% 4 == 0);
593 assert(tile_y
% 2 == 0);
594 /* Note that the low bits of these fields are missing, so
595 * there's the possibility of getting in trouble.
597 surf
.ss1
.base_addr
= tile_base
;
598 surf
.ss5
.x_offset
= tile_x
/ 4;
599 surf
.ss5
.y_offset
= tile_y
/ 2;
601 if (region_bo
!= NULL
)
602 surf
.ss1
.base_addr
+= region_bo
->offset
; /* reloc */
604 surf
.ss2
.width
= key
.width
- 1;
605 surf
.ss2
.height
= key
.height
- 1;
606 brw_set_surface_tiling(&surf
, key
.tiling
);
607 surf
.ss3
.pitch
= (key
.pitch
* key
.cpp
) - 1;
609 if (intel
->gen
< 6) {
611 surf
.ss0
.color_blend
= key
.color_blend
;
612 surf
.ss0
.writedisable_red
= !key
.color_mask
[0];
613 surf
.ss0
.writedisable_green
= !key
.color_mask
[1];
614 surf
.ss0
.writedisable_blue
= !key
.color_mask
[2];
615 surf
.ss0
.writedisable_alpha
= !key
.color_mask
[3];
618 /* Key size will never match key size for textures, so we're safe. */
619 brw
->wm
.surf_bo
[unit
] = brw_upload_cache(&brw
->surface_cache
,
623 &surf
, sizeof(surf
));
624 if (region_bo
!= NULL
) {
625 /* We might sample from it, and we might render to it, so flag
626 * them both. We might be able to figure out from other state
627 * a more restrictive relocation to emit.
629 drm_intel_bo_emit_reloc(brw
->wm
.surf_bo
[unit
],
630 offsetof(struct brw_surface_state
, ss1
),
632 surf
.ss1
.base_addr
- region_bo
->offset
,
633 I915_GEM_DOMAIN_RENDER
,
634 I915_GEM_DOMAIN_RENDER
);
641 * Constructs the binding table for the WM surface state, which maps unit
642 * numbers to surface state objects.
645 brw_wm_get_binding_table(struct brw_context
*brw
)
649 assert(brw
->wm
.nr_surfaces
<= BRW_WM_MAX_SURF
);
651 bind_bo
= brw_search_cache(&brw
->surface_cache
, BRW_SS_SURF_BIND
,
653 brw
->wm
.surf_bo
, brw
->wm
.nr_surfaces
,
656 if (bind_bo
== NULL
) {
657 GLuint data_size
= brw
->wm
.nr_surfaces
* sizeof(GLuint
);
658 uint32_t data
[BRW_WM_MAX_SURF
];
661 for (i
= 0; i
< brw
->wm
.nr_surfaces
; i
++)
662 if (brw
->wm
.surf_bo
[i
])
663 data
[i
] = brw
->wm
.surf_bo
[i
]->offset
;
667 bind_bo
= brw_upload_cache( &brw
->surface_cache
, BRW_SS_SURF_BIND
,
669 brw
->wm
.surf_bo
, brw
->wm
.nr_surfaces
,
672 /* Emit binding table relocations to surface state */
673 for (i
= 0; i
< BRW_WM_MAX_SURF
; i
++) {
674 if (brw
->wm
.surf_bo
[i
] != NULL
) {
675 dri_bo_emit_reloc(bind_bo
,
676 I915_GEM_DOMAIN_INSTRUCTION
, 0,
687 static void prepare_wm_surfaces(struct brw_context
*brw
)
689 GLcontext
*ctx
= &brw
->intel
.ctx
;
693 /* _NEW_BUFFERS | _NEW_COLOR */
694 /* Update surfaces for drawing buffers */
695 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
696 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
697 brw_update_renderbuffer_surface(brw
,
698 ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
702 brw_update_renderbuffer_surface(brw
, NULL
, 0);
705 old_nr_surfaces
= brw
->wm
.nr_surfaces
;
706 brw
->wm
.nr_surfaces
= BRW_MAX_DRAW_BUFFERS
;
708 if (brw
->wm
.surf_bo
[SURF_INDEX_FRAG_CONST_BUFFER
] != NULL
)
709 brw
->wm
.nr_surfaces
= SURF_INDEX_FRAG_CONST_BUFFER
+ 1;
711 /* Update surfaces for textures */
712 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
713 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
714 const GLuint surf
= SURF_INDEX_TEXTURE(i
);
716 /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
717 if (texUnit
->_ReallyEnabled
) {
718 brw_update_texture_surface(ctx
, i
);
719 brw
->wm
.nr_surfaces
= surf
+ 1;
721 dri_bo_unreference(brw
->wm
.surf_bo
[surf
]);
722 brw
->wm
.surf_bo
[surf
] = NULL
;
726 dri_bo_unreference(brw
->wm
.bind_bo
);
727 brw
->wm
.bind_bo
= brw_wm_get_binding_table(brw
);
729 if (brw
->wm
.nr_surfaces
!= old_nr_surfaces
)
730 brw
->state
.dirty
.brw
|= BRW_NEW_NR_WM_SURFACES
;
733 const struct brw_tracked_state brw_wm_surfaces
= {
735 .mesa
= (_NEW_COLOR
|
738 .brw
= (BRW_NEW_CONTEXT
|
739 BRW_NEW_WM_SURFACES
),
742 .prepare
= prepare_wm_surfaces
,