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i965: Avoid unnecessary copy when depthstencil workaround invoked by clear.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/context.h"
34 #include "main/mtypes.h"
35 #include "main/samplerobj.h"
36 #include "program/prog_parameter.h"
37
38 #include "intel_mipmap_tree.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_fbo.h"
42 #include "intel_buffer_objects.h"
43
44 #include "brw_context.h"
45 #include "brw_state.h"
46 #include "brw_defines.h"
47 #include "brw_wm.h"
48
49 GLuint
50 translate_tex_target(GLenum target)
51 {
52 switch (target) {
53 case GL_TEXTURE_1D:
54 case GL_TEXTURE_1D_ARRAY_EXT:
55 return BRW_SURFACE_1D;
56
57 case GL_TEXTURE_RECTANGLE_NV:
58 return BRW_SURFACE_2D;
59
60 case GL_TEXTURE_2D:
61 case GL_TEXTURE_2D_ARRAY_EXT:
62 case GL_TEXTURE_EXTERNAL_OES:
63 case GL_TEXTURE_2D_MULTISAMPLE:
64 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
65 return BRW_SURFACE_2D;
66
67 case GL_TEXTURE_3D:
68 return BRW_SURFACE_3D;
69
70 case GL_TEXTURE_CUBE_MAP:
71 case GL_TEXTURE_CUBE_MAP_ARRAY:
72 return BRW_SURFACE_CUBE;
73
74 default:
75 assert(0);
76 return 0;
77 }
78 }
79
80 struct surface_format_info {
81 bool exists;
82 int sampling;
83 int filtering;
84 int shadow_compare;
85 int chroma_key;
86 int render_target;
87 int alpha_blend;
88 int input_vb;
89 int streamed_output_vb;
90 int color_processing;
91 };
92
93 /* This macro allows us to write the table almost as it appears in the PRM,
94 * while restructuring it to turn it into the C code we want.
95 */
96 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
97 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
98
99 #define Y 0
100 #define x 999
101 /**
102 * This is the table of support for surface (texture, renderbuffer, and vertex
103 * buffer, but not depthbuffer) formats across the various hardware generations.
104 *
105 * The table is formatted to match the documentation, except that the docs have
106 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
107 * it in our table, here's the mapping:
108 *
109 * Y*: 45
110 * Y+: 45 (g45/gm45)
111 * Y~: 50 (gen5)
112 * Y^: 60 (gen6)
113 * Y#: 70 (gen7)
114 *
115 * The abbreviations in the header below are:
116 * smpl - Sampling Engine
117 * filt - Sampling Engine Filtering
118 * shad - Sampling Engine Shadow Map
119 * CK - Sampling Engine Chroma Key
120 * RT - Render Target
121 * AB - Alpha Blend Render Target
122 * VB - Input Vertex Buffer
123 * SO - Steamed Output Vertex Buffers (transform feedback)
124 * color - Color Processing
125 *
126 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
127 */
128 const struct surface_format_info surface_formats[] = {
129 /* smpl filt shad CK RT AB VB SO color */
130 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
131 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
132 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
133 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
134 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
135 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
136 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
137 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
138 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
139 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
140 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
141 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
144 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
145 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
146 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
147 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
148 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
149 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
150 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
151 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
152 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
153 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
154 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
155 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
156 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
157 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
158 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
159 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
160 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
161 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
162 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
163 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
164 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
165 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
166 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
167 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
168 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
169 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
170 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
171 /* smpl filt shad CK RT AB VB SO color */
172 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
173 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
174 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
175 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
176 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
177 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
178 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
179 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
180 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
181 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
182 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
183 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
184 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
185 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
186 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
187 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
188 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
189 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
190 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
191 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
192 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
193 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
194 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
195 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
196 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
197 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
198 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
199 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
200 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
201 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
202 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
203 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
204 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
205 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
206 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
207 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
208 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
209 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
210 /* smpl filt shad CK RT AB VB SO color */
211 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
212 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
213 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
214 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
215 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
216 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
217 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
218 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
219 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
220 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
221 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
222 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
223 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
224 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
225 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
226 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
227 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
228 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
229 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
230 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
231 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
232 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
233 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
234 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
235 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
236 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
237 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
238 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
239 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
240 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
241 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
242 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
243 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
244 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
245 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
246 /* smpl filt shad CK RT AB VB SO color */
247 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
248 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
249 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
250 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
251 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
252 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
253 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
255 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
256 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
257 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
258 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
259 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
260 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
261 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
262 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
263 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
264 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
265 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
266 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
267 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
268 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
269 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
271 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
272 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
273 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
274 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
275 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
276 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
277 /* smpl filt shad CK RT AB VB SO color */
278 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
279 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
280 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
281 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
282 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
283 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
284 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
285 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
286 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
287 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
288 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
289 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
290 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
291 };
292 #undef x
293 #undef Y
294
295 uint32_t
296 brw_format_for_mesa_format(gl_format mesa_format)
297 {
298 /* This table is ordered according to the enum ordering in formats.h. We do
299 * expect that enum to be extended without our explicit initialization
300 * staying in sync, so we initialize to 0 even though
301 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
302 */
303 static const uint32_t table[MESA_FORMAT_COUNT] =
304 {
305 [MESA_FORMAT_RGBA8888] = 0,
306 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
307 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
308 [MESA_FORMAT_ARGB8888_REV] = 0,
309 [MESA_FORMAT_RGBX8888] = 0,
310 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
311 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
312 [MESA_FORMAT_XRGB8888_REV] = 0,
313 [MESA_FORMAT_RGB888] = 0,
314 [MESA_FORMAT_BGR888] = 0,
315 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
316 [MESA_FORMAT_RGB565_REV] = 0,
317 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
318 [MESA_FORMAT_ARGB4444_REV] = 0,
319 [MESA_FORMAT_RGBA5551] = 0,
320 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
321 [MESA_FORMAT_ARGB1555_REV] = 0,
322 [MESA_FORMAT_AL44] = 0,
323 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
324 [MESA_FORMAT_AL88_REV] = 0,
325 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
326 [MESA_FORMAT_AL1616_REV] = 0,
327 [MESA_FORMAT_RGB332] = 0,
328 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
329 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
330 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
331 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
332 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
333 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
334 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
335 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
336 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
337 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
338 [MESA_FORMAT_RG88] = 0,
339 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
340 [MESA_FORMAT_GR1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
341 [MESA_FORMAT_RG1616] = 0,
342 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
343 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
344 [MESA_FORMAT_Z24_S8] = 0,
345 [MESA_FORMAT_S8_Z24] = 0,
346 [MESA_FORMAT_Z16] = 0,
347 [MESA_FORMAT_X8_Z24] = 0,
348 [MESA_FORMAT_Z24_X8] = 0,
349 [MESA_FORMAT_Z32] = 0,
350 [MESA_FORMAT_S8] = 0,
351
352 [MESA_FORMAT_SRGB8] = 0,
353 [MESA_FORMAT_SRGBA8] = 0,
354 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
355 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
356 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
357 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
358 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
359 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
360 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
361
362 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
363 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
364 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
365 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
366 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
367 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
368
369 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
370 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
371 [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
372 [MESA_FORMAT_RGB_FLOAT16] = 0,
373 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
374 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
375 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
376 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
377 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
378 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
379 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
380 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
381 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
382 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
383 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
384 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
385
386 [MESA_FORMAT_ALPHA_UINT8] = 0,
387 [MESA_FORMAT_ALPHA_UINT16] = 0,
388 [MESA_FORMAT_ALPHA_UINT32] = 0,
389 [MESA_FORMAT_ALPHA_INT8] = 0,
390 [MESA_FORMAT_ALPHA_INT16] = 0,
391 [MESA_FORMAT_ALPHA_INT32] = 0,
392
393 [MESA_FORMAT_INTENSITY_UINT8] = 0,
394 [MESA_FORMAT_INTENSITY_UINT16] = 0,
395 [MESA_FORMAT_INTENSITY_UINT32] = 0,
396 [MESA_FORMAT_INTENSITY_INT8] = 0,
397 [MESA_FORMAT_INTENSITY_INT16] = 0,
398 [MESA_FORMAT_INTENSITY_INT32] = 0,
399
400 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
401 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
402 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
403 [MESA_FORMAT_LUMINANCE_INT8] = 0,
404 [MESA_FORMAT_LUMINANCE_INT16] = 0,
405 [MESA_FORMAT_LUMINANCE_INT32] = 0,
406
407 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
408 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
409 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
410 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
411 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
412 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
413
414 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
415 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
416 [MESA_FORMAT_RGB_INT8] = 0,
417 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
418 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
419 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
420 [MESA_FORMAT_RGB_INT16] = 0,
421 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
422 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
423 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
424 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
425 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
426
427 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
428 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
429 [MESA_FORMAT_RGB_UINT8] = 0,
430 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
431 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
432 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
433 [MESA_FORMAT_RGB_UINT16] = 0,
434 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
435 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
436 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
437 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
438 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
439
440 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
441 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
442 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
443 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
444 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
445 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
446 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
447 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
448 [MESA_FORMAT_SIGNED_RGB_16] = 0,
449 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
450 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
451
452 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
453 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
454 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
455 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
456
457 [MESA_FORMAT_L_LATC1] = 0,
458 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
459 [MESA_FORMAT_LA_LATC2] = 0,
460 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
461
462 [MESA_FORMAT_SIGNED_A8] = 0,
463 [MESA_FORMAT_SIGNED_L8] = 0,
464 [MESA_FORMAT_SIGNED_AL88] = 0,
465 [MESA_FORMAT_SIGNED_I8] = 0,
466 [MESA_FORMAT_SIGNED_A16] = 0,
467 [MESA_FORMAT_SIGNED_L16] = 0,
468 [MESA_FORMAT_SIGNED_AL1616] = 0,
469 [MESA_FORMAT_SIGNED_I16] = 0,
470
471 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
472 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
473
474 [MESA_FORMAT_Z32_FLOAT] = 0,
475 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
476 };
477 assert(mesa_format < MESA_FORMAT_COUNT);
478 return table[mesa_format];
479 }
480
481 void
482 brw_init_surface_formats(struct brw_context *brw)
483 {
484 struct intel_context *intel = &brw->intel;
485 struct gl_context *ctx = &intel->ctx;
486 int gen;
487 gl_format format;
488
489 gen = intel->gen * 10;
490 if (intel->is_g4x)
491 gen += 5;
492
493 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
494 uint32_t texture, render;
495 const struct surface_format_info *rinfo, *tinfo;
496 bool is_integer = _mesa_is_format_integer_color(format);
497
498 render = texture = brw_format_for_mesa_format(format);
499 tinfo = &surface_formats[texture];
500
501 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
502 * it.
503 */
504 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
505 continue;
506
507 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
508 ctx->TextureFormatSupported[format] = true;
509
510 /* Re-map some render target formats to make them supported when they
511 * wouldn't be using their format for texturing.
512 */
513 switch (render) {
514 /* For these formats, we just need to read/write the first
515 * channel into R, which is to say that we just treat them as
516 * GL_RED.
517 */
518 case BRW_SURFACEFORMAT_I32_FLOAT:
519 case BRW_SURFACEFORMAT_L32_FLOAT:
520 render = BRW_SURFACEFORMAT_R32_FLOAT;
521 break;
522 case BRW_SURFACEFORMAT_I16_FLOAT:
523 case BRW_SURFACEFORMAT_L16_FLOAT:
524 render = BRW_SURFACEFORMAT_R16_FLOAT;
525 break;
526 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
527 /* XRGB is handled as ARGB because the chips in this family
528 * cannot render to XRGB targets. This means that we have to
529 * mask writes to alpha (ala glColorMask) and reconfigure the
530 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
531 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
532 * used.
533 */
534 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
535 break;
536 }
537
538 rinfo = &surface_formats[render];
539
540 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
541 * integer, so we don't need hardware support for blending on it. Other
542 * than that, GL in general requires alpha blending for render targets,
543 * even though we don't support it for some formats.
544 */
545 if (gen >= rinfo->render_target &&
546 (gen >= rinfo->alpha_blend || is_integer)) {
547 brw->render_target_format[format] = render;
548 brw->format_supported_as_render_target[format] = true;
549 }
550 }
551
552 /* We will check this table for FBO completeness, but the surface format
553 * table above only covered color rendering.
554 */
555 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
556 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
557 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
558 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
559 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
560 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
561
562 /* We remap depth formats to a supported texturing format in
563 * translate_tex_format().
564 */
565 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
566 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
567 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
568 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
569 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
570
571 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
572 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
573 */
574 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
575
576 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
577 * MESA_FORMAT during glCompressedTexImage2D().
578 * See intel_mipmap_tree::wraps_etc2.
579 */
580 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
581 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
582 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
583 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
584 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
585 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
586 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
587 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
588 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
589 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
590 }
591
592 bool
593 brw_render_target_supported(struct intel_context *intel,
594 struct gl_renderbuffer *rb)
595 {
596 struct brw_context *brw = brw_context(&intel->ctx);
597 gl_format format = rb->Format;
598
599 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
600 * we would consider them renderable even though we don't have surface
601 * support for their alpha behavior and don't have the blending unit
602 * available to fake it like we do for XRGB8888. Force them to being
603 * unsupported.
604 */
605 if ((rb->_BaseFormat != GL_RGBA &&
606 rb->_BaseFormat != GL_RG &&
607 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
608 return false;
609
610 /* Under some conditions, MSAA is not supported for formats whose width is
611 * more than 64 bits.
612 */
613 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
614 /* Gen6: MSAA on >64 bit formats is unsupported. */
615 if (intel->gen <= 6)
616 return false;
617
618 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
619 if (rb->NumSamples >= 8)
620 return false;
621 }
622
623 return brw->format_supported_as_render_target[format];
624 }
625
626 GLuint
627 translate_tex_format(struct intel_context *intel,
628 gl_format mesa_format,
629 GLenum internal_format,
630 GLenum depth_mode,
631 GLenum srgb_decode)
632 {
633 struct gl_context *ctx = &intel->ctx;
634 if (srgb_decode == GL_SKIP_DECODE_EXT)
635 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
636
637 switch( mesa_format ) {
638
639 case MESA_FORMAT_Z16:
640 return BRW_SURFACEFORMAT_I16_UNORM;
641
642 case MESA_FORMAT_S8_Z24:
643 case MESA_FORMAT_X8_Z24:
644 return BRW_SURFACEFORMAT_I24X8_UNORM;
645
646 case MESA_FORMAT_Z32_FLOAT:
647 return BRW_SURFACEFORMAT_I32_FLOAT;
648
649 case MESA_FORMAT_Z32_FLOAT_X24S8:
650 return BRW_SURFACEFORMAT_R32G32_FLOAT;
651
652 case MESA_FORMAT_RGBA_FLOAT32:
653 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
654 * assertion below.
655 */
656 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
657
658 case MESA_FORMAT_SRGB_DXT1:
659 if (intel->gen == 4 && !intel->is_g4x) {
660 /* Work around missing SRGB DXT1 support on original gen4 by just
661 * skipping SRGB decode. It's not worth not supporting sRGB in
662 * general to prevent this.
663 */
664 WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
665 mesa_format = MESA_FORMAT_RGB_DXT1;
666 }
667 return brw_format_for_mesa_format(mesa_format);
668
669 default:
670 assert(brw_format_for_mesa_format(mesa_format) != 0);
671 return brw_format_for_mesa_format(mesa_format);
672 }
673 }
674
675 uint32_t
676 brw_get_surface_tiling_bits(uint32_t tiling)
677 {
678 switch (tiling) {
679 case I915_TILING_X:
680 return BRW_SURFACE_TILED;
681 case I915_TILING_Y:
682 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
683 default:
684 return 0;
685 }
686 }
687
688
689 uint32_t
690 brw_get_surface_num_multisamples(unsigned num_samples)
691 {
692 if (num_samples > 1)
693 return BRW_SURFACE_MULTISAMPLECOUNT_4;
694 else
695 return BRW_SURFACE_MULTISAMPLECOUNT_1;
696 }
697
698
699 /**
700 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
701 * swizzling.
702 */
703 int
704 brw_get_texture_swizzle(const struct gl_context *ctx,
705 const struct gl_texture_object *t)
706 {
707 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
708
709 int swizzles[SWIZZLE_NIL + 1] = {
710 SWIZZLE_X,
711 SWIZZLE_Y,
712 SWIZZLE_Z,
713 SWIZZLE_W,
714 SWIZZLE_ZERO,
715 SWIZZLE_ONE,
716 SWIZZLE_NIL
717 };
718
719 if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
720 img->_BaseFormat == GL_DEPTH_STENCIL) {
721 GLenum depth_mode = t->DepthMode;
722
723 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
724 * with depth component data specified with a sized internal format.
725 * Otherwise, it's left at the old default, GL_LUMINANCE.
726 */
727 if (_mesa_is_gles3(ctx) &&
728 img->InternalFormat != GL_DEPTH_COMPONENT &&
729 img->InternalFormat != GL_DEPTH_STENCIL) {
730 depth_mode = GL_RED;
731 }
732
733 switch (depth_mode) {
734 case GL_ALPHA:
735 swizzles[0] = SWIZZLE_ZERO;
736 swizzles[1] = SWIZZLE_ZERO;
737 swizzles[2] = SWIZZLE_ZERO;
738 swizzles[3] = SWIZZLE_X;
739 break;
740 case GL_LUMINANCE:
741 swizzles[0] = SWIZZLE_X;
742 swizzles[1] = SWIZZLE_X;
743 swizzles[2] = SWIZZLE_X;
744 swizzles[3] = SWIZZLE_ONE;
745 break;
746 case GL_INTENSITY:
747 swizzles[0] = SWIZZLE_X;
748 swizzles[1] = SWIZZLE_X;
749 swizzles[2] = SWIZZLE_X;
750 swizzles[3] = SWIZZLE_X;
751 break;
752 case GL_RED:
753 swizzles[0] = SWIZZLE_X;
754 swizzles[1] = SWIZZLE_ZERO;
755 swizzles[2] = SWIZZLE_ZERO;
756 swizzles[3] = SWIZZLE_ONE;
757 break;
758 }
759 }
760
761 /* If the texture's format is alpha-only, force R, G, and B to
762 * 0.0. Similarly, if the texture's format has no alpha channel,
763 * force the alpha value read to 1.0. This allows for the
764 * implementation to use an RGBA texture for any of these formats
765 * without leaking any unexpected values.
766 */
767 switch (img->_BaseFormat) {
768 case GL_ALPHA:
769 swizzles[0] = SWIZZLE_ZERO;
770 swizzles[1] = SWIZZLE_ZERO;
771 swizzles[2] = SWIZZLE_ZERO;
772 break;
773 case GL_RED:
774 case GL_RG:
775 case GL_RGB:
776 swizzles[3] = SWIZZLE_ONE;
777 break;
778 }
779
780 return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
781 swizzles[GET_SWZ(t->_Swizzle, 1)],
782 swizzles[GET_SWZ(t->_Swizzle, 2)],
783 swizzles[GET_SWZ(t->_Swizzle, 3)]);
784 }
785
786
787 static void
788 brw_update_buffer_texture_surface(struct gl_context *ctx,
789 unsigned unit,
790 uint32_t *binding_table,
791 unsigned surf_index)
792 {
793 struct brw_context *brw = brw_context(ctx);
794 struct intel_context *intel = &brw->intel;
795 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
796 uint32_t *surf;
797 struct intel_buffer_object *intel_obj =
798 intel_buffer_object(tObj->BufferObject);
799 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
800 gl_format format = tObj->_BufferObjectFormat;
801 uint32_t brw_format = brw_format_for_mesa_format(format);
802 int texel_size = _mesa_get_format_bytes(format);
803
804 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
805 _mesa_problem(NULL, "bad format %s for texture buffer\n",
806 _mesa_get_format_name(format));
807 }
808
809 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
810 6 * 4, 32, &binding_table[surf_index]);
811
812 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
813 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
814
815 if (intel->gen >= 6)
816 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
817
818 if (bo) {
819 surf[1] = bo->offset; /* reloc */
820
821 /* Emit relocation to surface contents. */
822 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
823 binding_table[surf_index] + 4,
824 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
825
826 int w = intel_obj->Base.Size / texel_size;
827 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
828 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
829 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
830 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
831 } else {
832 surf[1] = 0;
833 surf[2] = 0;
834 surf[3] = 0;
835 }
836
837 surf[4] = 0;
838 surf[5] = 0;
839 }
840
841 static void
842 brw_update_texture_surface(struct gl_context *ctx,
843 unsigned unit,
844 uint32_t *binding_table,
845 unsigned surf_index)
846 {
847 struct intel_context *intel = intel_context(ctx);
848 struct brw_context *brw = brw_context(ctx);
849 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
850 struct intel_texture_object *intelObj = intel_texture_object(tObj);
851 struct intel_mipmap_tree *mt = intelObj->mt;
852 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
853 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
854 uint32_t *surf;
855 int width, height, depth;
856 uint32_t tile_x, tile_y;
857
858 if (tObj->Target == GL_TEXTURE_BUFFER) {
859 brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
860 return;
861 }
862
863 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
864
865 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
866 6 * 4, 32, &binding_table[surf_index]);
867
868 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
869 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
870 BRW_SURFACE_CUBEFACE_ENABLES |
871 (translate_tex_format(intel,
872 mt->format,
873 firstImage->InternalFormat,
874 tObj->DepthMode,
875 sampler->sRGBDecode) <<
876 BRW_SURFACE_FORMAT_SHIFT));
877
878 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
879
880 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
881 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
882 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
883
884 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
885 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
886 (intelObj->mt->region->pitch - 1) <<
887 BRW_SURFACE_PITCH_SHIFT);
888
889 surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
890
891 intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
892 &tile_x, &tile_y);
893 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
894 /* Note that the low bits of these fields are missing, so
895 * there's the possibility of getting in trouble.
896 */
897 assert(tile_x % 4 == 0);
898 assert(tile_y % 2 == 0);
899 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
900 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
901 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
902
903 /* Emit relocation to surface contents */
904 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
905 binding_table[surf_index] + 4,
906 intelObj->mt->region->bo,
907 intelObj->mt->offset,
908 I915_GEM_DOMAIN_SAMPLER, 0);
909 }
910
911 /**
912 * Create the constant buffer surface. Vertex/fragment shader constants will be
913 * read from this buffer with Data Port Read instructions/messages.
914 */
915 void
916 brw_create_constant_surface(struct brw_context *brw,
917 drm_intel_bo *bo,
918 uint32_t offset,
919 int width,
920 uint32_t *out_offset)
921 {
922 struct intel_context *intel = &brw->intel;
923 const GLint w = width - 1;
924 uint32_t *surf;
925
926 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
927 6 * 4, 32, out_offset);
928
929 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
930 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
931 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
932
933 if (intel->gen >= 6)
934 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
935
936 surf[1] = bo->offset + offset; /* reloc */
937
938 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
939 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
940
941 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
942 (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
943
944 surf[4] = 0;
945 surf[5] = 0;
946
947 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
948 * bspec ("Data Cache") says that the data cache does not exist as
949 * a separate cache and is just the sampler cache.
950 */
951 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
952 *out_offset + 4,
953 bo, offset,
954 I915_GEM_DOMAIN_SAMPLER, 0);
955 }
956
957 /**
958 * Set up a binding table entry for use by stream output logic (transform
959 * feedback).
960 *
961 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
962 */
963 void
964 brw_update_sol_surface(struct brw_context *brw,
965 struct gl_buffer_object *buffer_obj,
966 uint32_t *out_offset, unsigned num_vector_components,
967 unsigned stride_dwords, unsigned offset_dwords)
968 {
969 struct intel_context *intel = &brw->intel;
970 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
971 drm_intel_bo *bo =
972 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
973 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
974 out_offset);
975 uint32_t pitch_minus_1 = 4*stride_dwords - 1;
976 uint32_t offset_bytes = 4 * offset_dwords;
977 size_t size_dwords = buffer_obj->Size / 4;
978 uint32_t buffer_size_minus_1, width, height, depth, surface_format;
979
980 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
981 * too big to map using a single binding table entry?
982 */
983 assert((size_dwords - offset_dwords) / stride_dwords
984 <= BRW_MAX_NUM_BUFFER_ENTRIES);
985
986 if (size_dwords > offset_dwords + num_vector_components) {
987 /* There is room for at least 1 transform feedback output in the buffer.
988 * Compute the number of additional transform feedback outputs the
989 * buffer has room for.
990 */
991 buffer_size_minus_1 =
992 (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
993 } else {
994 /* There isn't even room for a single transform feedback output in the
995 * buffer. We can't configure the binding table entry to prevent output
996 * entirely; we'll have to rely on the geometry shader to detect
997 * overflow. But to minimize the damage in case of a bug, set up the
998 * binding table entry to just allow a single output.
999 */
1000 buffer_size_minus_1 = 0;
1001 }
1002 width = buffer_size_minus_1 & 0x7f;
1003 height = (buffer_size_minus_1 & 0xfff80) >> 7;
1004 depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
1005
1006 switch (num_vector_components) {
1007 case 1:
1008 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1009 break;
1010 case 2:
1011 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1012 break;
1013 case 3:
1014 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1015 break;
1016 case 4:
1017 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
1018 break;
1019 default:
1020 assert(!"Invalid vector size for transform feedback output");
1021 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1022 break;
1023 }
1024
1025 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1026 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1027 surface_format << BRW_SURFACE_FORMAT_SHIFT |
1028 BRW_SURFACE_RC_READ_WRITE;
1029 surf[1] = bo->offset + offset_bytes; /* reloc */
1030 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
1031 height << BRW_SURFACE_HEIGHT_SHIFT);
1032 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1033 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1034 surf[4] = 0;
1035 surf[5] = 0;
1036
1037 /* Emit relocation to surface contents. */
1038 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1039 *out_offset + 4,
1040 bo, offset_bytes,
1041 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1042 }
1043
1044 /* Creates a new WM constant buffer reflecting the current fragment program's
1045 * constants, if needed by the fragment program.
1046 *
1047 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
1048 * state atom.
1049 */
1050 static void
1051 brw_upload_wm_pull_constants(struct brw_context *brw)
1052 {
1053 struct gl_context *ctx = &brw->intel.ctx;
1054 struct intel_context *intel = &brw->intel;
1055 /* BRW_NEW_FRAGMENT_PROGRAM */
1056 struct brw_fragment_program *fp =
1057 (struct brw_fragment_program *) brw->fragment_program;
1058 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1059 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1060 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1061 float *constants;
1062 unsigned int i;
1063
1064 _mesa_load_state_parameters(ctx, params);
1065
1066 /* CACHE_NEW_WM_PROG */
1067 if (brw->wm.prog_data->nr_pull_params == 0) {
1068 if (brw->wm.const_bo) {
1069 drm_intel_bo_unreference(brw->wm.const_bo);
1070 brw->wm.const_bo = NULL;
1071 brw->wm.surf_offset[surf_index] = 0;
1072 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1073 }
1074 return;
1075 }
1076
1077 drm_intel_bo_unreference(brw->wm.const_bo);
1078 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1079 size, 64);
1080
1081 /* _NEW_PROGRAM_CONSTANTS */
1082 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1083 constants = brw->wm.const_bo->virtual;
1084 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1085 constants[i] = *brw->wm.prog_data->pull_param[i];
1086 }
1087 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1088
1089 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1090 ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4,
1091 &brw->wm.surf_offset[surf_index]);
1092
1093 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1094 }
1095
1096 const struct brw_tracked_state brw_wm_pull_constants = {
1097 .dirty = {
1098 .mesa = (_NEW_PROGRAM_CONSTANTS),
1099 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1100 .cache = CACHE_NEW_WM_PROG,
1101 },
1102 .emit = brw_upload_wm_pull_constants,
1103 };
1104
1105 static void
1106 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1107 {
1108 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1109 * Notes):
1110 *
1111 * A null surface will be used in instances where an actual surface is
1112 * not bound. When a write message is generated to a null surface, no
1113 * actual surface is written to. When a read message (including any
1114 * sampling engine message) is generated to a null surface, the result
1115 * is all zeros. Note that a null surface type is allowed to be used
1116 * with all messages, even if it is not specificially indicated as
1117 * supported. All of the remaining fields in surface state are ignored
1118 * for null surfaces, with the following exceptions:
1119 *
1120 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1121 * depth buffer’s corresponding state for all render target surfaces,
1122 * including null.
1123 *
1124 * - Surface Format must be R8G8B8A8_UNORM.
1125 */
1126 struct intel_context *intel = &brw->intel;
1127 struct gl_context *ctx = &intel->ctx;
1128 uint32_t *surf;
1129 unsigned surface_type = BRW_SURFACE_NULL;
1130 drm_intel_bo *bo = NULL;
1131 unsigned pitch_minus_1 = 0;
1132 uint32_t multisampling_state = 0;
1133
1134 /* _NEW_BUFFERS */
1135 const struct gl_framebuffer *fb = ctx->DrawBuffer;
1136
1137 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1138 6 * 4, 32, &brw->wm.surf_offset[unit]);
1139
1140 if (fb->Visual.samples > 1) {
1141 /* On Gen6, null render targets seem to cause GPU hangs when
1142 * multisampling. So work around this problem by rendering into dummy
1143 * color buffer.
1144 *
1145 * To decrease the amount of memory needed by the workaround buffer, we
1146 * set its pitch to 128 bytes (the width of a Y tile). This means that
1147 * the amount of memory needed for the workaround buffer is
1148 * (width_in_tiles + height_in_tiles - 1) tiles.
1149 *
1150 * Note that since the workaround buffer will be interpreted by the
1151 * hardware as an interleaved multisampled buffer, we need to compute
1152 * width_in_tiles and height_in_tiles by dividing the width and height
1153 * by 16 rather than the normal Y-tile size of 32.
1154 */
1155 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1156 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1157 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1158 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1159 size_needed);
1160 bo = brw->wm.multisampled_null_render_target_bo;
1161 surface_type = BRW_SURFACE_2D;
1162 pitch_minus_1 = 127;
1163 multisampling_state =
1164 brw_get_surface_num_multisamples(fb->Visual.samples);
1165 }
1166
1167 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1168 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1169 if (intel->gen < 6) {
1170 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1171 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1172 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1173 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1174 }
1175 surf[1] = bo ? bo->offset : 0;
1176 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1177 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1178
1179 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1180 * Notes):
1181 *
1182 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
1183 */
1184 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1185 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1186 surf[4] = multisampling_state;
1187 surf[5] = 0;
1188
1189 if (bo) {
1190 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1191 brw->wm.surf_offset[unit] + 4,
1192 bo, 0,
1193 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1194 }
1195 }
1196
1197 /**
1198 * Sets up a surface state structure to point at the given region.
1199 * While it is only used for the front/back buffer currently, it should be
1200 * usable for further buffers when doing ARB_draw_buffer support.
1201 */
1202 static void
1203 brw_update_renderbuffer_surface(struct brw_context *brw,
1204 struct gl_renderbuffer *rb,
1205 unsigned int unit)
1206 {
1207 struct intel_context *intel = &brw->intel;
1208 struct gl_context *ctx = &intel->ctx;
1209 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1210 struct intel_mipmap_tree *mt = irb->mt;
1211 struct intel_region *region;
1212 uint32_t *surf;
1213 uint32_t tile_x, tile_y;
1214 uint32_t format = 0;
1215 gl_format rb_format = intel_rb_format(irb);
1216
1217 if (irb->tex_image && !brw->has_surface_tile_offset) {
1218 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1219
1220 if (tile_x != 0 || tile_y != 0) {
1221 /* Original gen4 hardware couldn't draw to a non-tile-aligned
1222 * destination in a miptree unless you actually setup your renderbuffer
1223 * as a miptree and used the fragile lod/array_index/etc. controls to
1224 * select the image. So, instead, we just make a new single-level
1225 * miptree and render into that.
1226 */
1227 intel_renderbuffer_move_to_temp(intel, irb, false);
1228 mt = irb->mt;
1229 }
1230 }
1231
1232 region = irb->mt->region;
1233
1234 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1235 6 * 4, 32, &brw->wm.surf_offset[unit]);
1236
1237 switch (rb_format) {
1238 case MESA_FORMAT_SARGB8:
1239 /* _NEW_BUFFERS
1240 *
1241 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1242 * blend/update as sRGB.
1243 */
1244 if (ctx->Color.sRGBEnabled)
1245 format = brw_format_for_mesa_format(rb_format);
1246 else
1247 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1248 break;
1249 default:
1250 format = brw->render_target_format[rb_format];
1251 if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1252 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1253 __FUNCTION__, _mesa_get_format_name(rb_format));
1254 }
1255 break;
1256 }
1257
1258 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1259 format << BRW_SURFACE_FORMAT_SHIFT);
1260
1261 /* reloc */
1262 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1263 region->bo->offset);
1264
1265 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1266 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1267
1268 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1269 (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1270
1271 surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1272
1273 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1274 /* Note that the low bits of these fields are missing, so
1275 * there's the possibility of getting in trouble.
1276 */
1277 assert(tile_x % 4 == 0);
1278 assert(tile_y % 2 == 0);
1279 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1280 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1281 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1282
1283 if (intel->gen < 6) {
1284 /* _NEW_COLOR */
1285 if (!ctx->Color.ColorLogicOpEnabled &&
1286 (ctx->Color.BlendEnabled & (1 << unit)))
1287 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1288
1289 if (!ctx->Color.ColorMask[unit][0])
1290 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1291 if (!ctx->Color.ColorMask[unit][1])
1292 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1293 if (!ctx->Color.ColorMask[unit][2])
1294 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1295
1296 /* As mentioned above, disable writes to the alpha component when the
1297 * renderbuffer is XRGB.
1298 */
1299 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1300 !ctx->Color.ColorMask[unit][3]) {
1301 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1302 }
1303 }
1304
1305 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1306 brw->wm.surf_offset[unit] + 4,
1307 region->bo,
1308 surf[1] - region->bo->offset,
1309 I915_GEM_DOMAIN_RENDER,
1310 I915_GEM_DOMAIN_RENDER);
1311 }
1312
1313 /**
1314 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1315 */
1316 static void
1317 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1318 {
1319 struct intel_context *intel = &brw->intel;
1320 struct gl_context *ctx = &brw->intel.ctx;
1321 GLuint i;
1322
1323 /* _NEW_BUFFERS | _NEW_COLOR */
1324 /* Update surfaces for drawing buffers */
1325 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1326 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1327 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1328 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1329 } else {
1330 intel->vtbl.update_null_renderbuffer_surface(brw, i);
1331 }
1332 }
1333 } else {
1334 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1335 }
1336 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1337 }
1338
1339 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1340 .dirty = {
1341 .mesa = (_NEW_COLOR |
1342 _NEW_BUFFERS),
1343 .brw = BRW_NEW_BATCH,
1344 .cache = 0
1345 },
1346 .emit = brw_update_renderbuffer_surfaces,
1347 };
1348
1349 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1350 .dirty = {
1351 .mesa = _NEW_BUFFERS,
1352 .brw = BRW_NEW_BATCH,
1353 .cache = 0
1354 },
1355 .emit = brw_update_renderbuffer_surfaces,
1356 };
1357
1358 /**
1359 * Construct SURFACE_STATE objects for enabled textures.
1360 */
1361 static void
1362 brw_update_texture_surfaces(struct brw_context *brw)
1363 {
1364 struct intel_context *intel = &brw->intel;
1365 struct gl_context *ctx = &intel->ctx;
1366
1367 /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1368 * Unfortunately, we're stuck using the gl_program structs until the
1369 * ARB_fragment_program front-end gets converted to GLSL IR. These
1370 * have the downside that SamplerUnits is split and only contains the
1371 * mappings for samplers active in that stage.
1372 */
1373 struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1374 struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1375
1376 unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1377
1378 for (unsigned s = 0; s < num_samplers; s++) {
1379 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1380 brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1381
1382 if (vs->SamplersUsed & (1 << s)) {
1383 const unsigned unit = vs->SamplerUnits[s];
1384
1385 /* _NEW_TEXTURE */
1386 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1387 intel->vtbl.update_texture_surface(ctx, unit,
1388 brw->vs.surf_offset,
1389 SURF_INDEX_VS_TEXTURE(s));
1390 }
1391 }
1392
1393 if (fs->SamplersUsed & (1 << s)) {
1394 const unsigned unit = fs->SamplerUnits[s];
1395
1396 /* _NEW_TEXTURE */
1397 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1398 intel->vtbl.update_texture_surface(ctx, unit,
1399 brw->wm.surf_offset,
1400 SURF_INDEX_TEXTURE(s));
1401 }
1402 }
1403 }
1404
1405 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1406 }
1407
1408 const struct brw_tracked_state brw_texture_surfaces = {
1409 .dirty = {
1410 .mesa = _NEW_TEXTURE,
1411 .brw = BRW_NEW_BATCH |
1412 BRW_NEW_VERTEX_PROGRAM |
1413 BRW_NEW_FRAGMENT_PROGRAM,
1414 .cache = 0
1415 },
1416 .emit = brw_update_texture_surfaces,
1417 };
1418
1419 void
1420 brw_upload_ubo_surfaces(struct brw_context *brw,
1421 struct gl_shader *shader,
1422 uint32_t *surf_offsets)
1423 {
1424 struct gl_context *ctx = &brw->intel.ctx;
1425 struct intel_context *intel = &brw->intel;
1426
1427 if (!shader)
1428 return;
1429
1430 for (int i = 0; i < shader->NumUniformBlocks; i++) {
1431 struct gl_uniform_buffer_binding *binding;
1432 struct intel_buffer_object *intel_bo;
1433
1434 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1435 intel_bo = intel_buffer_object(binding->BufferObject);
1436 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1437
1438 /* Because behavior for referencing outside of the binding's size in the
1439 * glBindBufferRange case is undefined, we can just bind the whole buffer
1440 * glBindBufferBase wants and be a correct implementation.
1441 */
1442 int size = bo->size - binding->Offset;
1443 size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1444
1445 intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1446 size,
1447 &surf_offsets[i]);
1448 }
1449
1450 if (shader->NumUniformBlocks)
1451 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1452 }
1453
1454 static void
1455 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1456 {
1457 struct gl_context *ctx = &brw->intel.ctx;
1458 /* _NEW_PROGRAM */
1459 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1460
1461 if (!prog)
1462 return;
1463
1464 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1465 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1466 }
1467
1468 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1469 .dirty = {
1470 .mesa = (_NEW_PROGRAM |
1471 _NEW_BUFFER_OBJECT),
1472 .brw = BRW_NEW_BATCH,
1473 .cache = 0,
1474 },
1475 .emit = brw_upload_wm_ubo_surfaces,
1476 };
1477
1478 /**
1479 * Constructs the binding table for the WM surface state, which maps unit
1480 * numbers to surface state objects.
1481 */
1482 static void
1483 brw_upload_wm_binding_table(struct brw_context *brw)
1484 {
1485 uint32_t *bind;
1486 int i;
1487
1488 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1489 gen7_create_shader_time_surface(brw, &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1490 }
1491
1492 /* Might want to calculate nr_surfaces first, to avoid taking up so much
1493 * space for the binding table.
1494 */
1495 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1496 sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1497 32, &brw->wm.bind_bo_offset);
1498
1499 /* BRW_NEW_SURFACES */
1500 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1501 bind[i] = brw->wm.surf_offset[i];
1502 }
1503
1504 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1505 }
1506
1507 const struct brw_tracked_state brw_wm_binding_table = {
1508 .dirty = {
1509 .mesa = 0,
1510 .brw = (BRW_NEW_BATCH |
1511 BRW_NEW_SURFACES),
1512 .cache = 0
1513 },
1514 .emit = brw_upload_wm_binding_table,
1515 };
1516
1517 void
1518 gen4_init_vtable_surface_functions(struct brw_context *brw)
1519 {
1520 struct intel_context *intel = &brw->intel;
1521
1522 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1523 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1524 intel->vtbl.update_null_renderbuffer_surface =
1525 brw_update_null_renderbuffer_surface;
1526 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1527 }