src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "shader/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( gl_format mesa_format,
  73                                     GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_AL1616:
  90       return BRW_SURFACEFORMAT_L16A16_UNORM;
  91
  92    case MESA_FORMAT_RGB888:
  93       assert(0);                /* not supported for sampling */
  94       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  95
  96    case MESA_FORMAT_ARGB8888:
  97       if (internal_format == GL_RGB)
  98          return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
  99       else
 100          return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 101
 102    case MESA_FORMAT_XRGB8888:
 103       return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 104
 105    case MESA_FORMAT_RGBA8888_REV:
 106       _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
 107       if (internal_format == GL_RGB)
 108          return BRW_SURFACEFORMAT_R8G8B8X8_UNORM;
 109       else
 110          return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 111
 112    case MESA_FORMAT_RGB565:
 113       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 114
 115    case MESA_FORMAT_ARGB1555:
 116       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 117
 118    case MESA_FORMAT_ARGB4444:
 119       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 120
 121    case MESA_FORMAT_YCBCR_REV:
 122       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 123
 124    case MESA_FORMAT_YCBCR:
 125       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 126
 127    case MESA_FORMAT_RGB_FXT1:
 128    case MESA_FORMAT_RGBA_FXT1:
 129       return BRW_SURFACEFORMAT_FXT1;
 130
 131    case MESA_FORMAT_Z16:
 132       if (depth_mode == GL_INTENSITY)
 133           return BRW_SURFACEFORMAT_I16_UNORM;
 134       else if (depth_mode == GL_ALPHA)
 135           return BRW_SURFACEFORMAT_A16_UNORM;
 136       else
 137           return BRW_SURFACEFORMAT_L16_UNORM;
 138
 139    case MESA_FORMAT_RGB_DXT1:
 140        return BRW_SURFACEFORMAT_DXT1_RGB;
 141
 142    case MESA_FORMAT_RGBA_DXT1:
 143        return BRW_SURFACEFORMAT_BC1_UNORM;
 144
 145    case MESA_FORMAT_RGBA_DXT3:
 146        return BRW_SURFACEFORMAT_BC2_UNORM;
 147
 148    case MESA_FORMAT_RGBA_DXT5:
 149        return BRW_SURFACEFORMAT_BC3_UNORM;
 150
 151    case MESA_FORMAT_SARGB8:
 152       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 153
 154    case MESA_FORMAT_SLA8:
 155       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 156
 157    case MESA_FORMAT_SL8:
 158       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 159
 160    case MESA_FORMAT_SRGB_DXT1:
 161       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 162
 163    case MESA_FORMAT_S8_Z24:
 164       /* XXX: these different surface formats don't seem to
 165        * make any difference for shadow sampler/compares.
 166        */
 167       if (depth_mode == GL_INTENSITY)
 168          return BRW_SURFACEFORMAT_I24X8_UNORM;
 169       else if (depth_mode == GL_ALPHA)
 170          return BRW_SURFACEFORMAT_A24X8_UNORM;
 171       else
 172          return BRW_SURFACEFORMAT_L24X8_UNORM;
 173
 174    case MESA_FORMAT_DUDV8:
 175       return BRW_SURFACEFORMAT_R8G8_SNORM;
 176
 177    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 178       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 179
 180    default:
 181       assert(0);
 182       return 0;
 183    }
 184 }
 185
 186 static void
 187 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 188 {
 189    switch (tiling) {
 190    case I915_TILING_NONE:
 191       surf->ss3.tiled_surface = 0;
 192       surf->ss3.tile_walk = 0;
 193       break;
 194    case I915_TILING_X:
 195       surf->ss3.tiled_surface = 1;
 196       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 197       break;
 198    case I915_TILING_Y:
 199       surf->ss3.tiled_surface = 1;
 200       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 201       break;
 202    }
 203 }
 204
 205 static dri_bo *
 206 brw_create_texture_surface( struct brw_context *brw,
 207                             struct brw_surface_key *key )
 208 {
 209    struct brw_surface_state surf;
 210    dri_bo *bo;
 211
 212    memset(&surf, 0, sizeof(surf));
 213
 214    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 215    surf.ss0.surface_type = translate_tex_target(key->target);
 216    if (key->bo) {
 217       surf.ss0.surface_format = translate_tex_format(key->format,
 218                                                      key->internal_format,
 219                                                      key->depthmode);
 220    }
 221    else {
 222       switch (key->depth) {
 223       case 32:
 224          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 225          break;
 226       default:
 227       case 24:
 228          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 229          break;
 230       case 16:
 231          surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 232          break;
 233       }
 234    }
 235
 236    /* This is ok for all textures with channel width 8bit or less:
 237     */
 238 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 239    if (key->bo)
 240       surf.ss1.base_addr = key->bo->offset; /* reloc */
 241    else
 242       surf.ss1.base_addr = key->offset;
 243
 244    surf.ss2.mip_count = key->last_level - key->first_level;
 245    surf.ss2.width = key->width - 1;
 246    surf.ss2.height = key->height - 1;
 247    brw_set_surface_tiling(&surf, key->tiling);
 248    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 249    surf.ss3.depth = key->depth - 1;
 250
 251    surf.ss4.min_lod = 0;
 252
 253    if (key->target == GL_TEXTURE_CUBE_MAP) {
 254       surf.ss0.cube_pos_x = 1;
 255       surf.ss0.cube_pos_y = 1;
 256       surf.ss0.cube_pos_z = 1;
 257       surf.ss0.cube_neg_x = 1;
 258       surf.ss0.cube_neg_y = 1;
 259       surf.ss0.cube_neg_z = 1;
 260    }
 261
 262    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 263                          key, sizeof(*key),
 264                          &key->bo, key->bo ? 1 : 0,
 265                          &surf, sizeof(surf),
 266                          NULL, NULL);
 267
 268    if (key->bo) {
 269       /* Emit relocation to surface contents */
 270       dri_bo_emit_reloc(bo,
 271                         I915_GEM_DOMAIN_SAMPLER, 0,
 272                         0,
 273                         offsetof(struct brw_surface_state, ss1),
 274                         key->bo);
 275    }
 276    return bo;
 277 }
 278
 279 static void
 280 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 281 {
 282    struct brw_context *brw = brw_context(ctx);
 283    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 284    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 285    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 286    struct brw_surface_key key;
 287    const GLuint surf = SURF_INDEX_TEXTURE(unit);
 288
 289    memset(&key, 0, sizeof(key));
 290
 291    if (intelObj->imageOverride) {
 292       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 293       key.depth = intelObj->depthOverride;
 294       key.bo = NULL;
 295       key.offset = intelObj->textureOffset;
 296    } else {
 297       key.format = firstImage->TexFormat;
 298       key.internal_format = firstImage->InternalFormat;
 299       key.pitch = intelObj->mt->pitch;
 300       key.depth = firstImage->Depth;
 301       key.bo = intelObj->mt->region->buffer;
 302       key.offset = 0;
 303    }
 304
 305    key.target = tObj->Target;
 306    key.depthmode = tObj->DepthMode;
 307    key.first_level = intelObj->firstLevel;
 308    key.last_level = intelObj->lastLevel;
 309    key.width = firstImage->Width;
 310    key.height = firstImage->Height;
 311    key.cpp = intelObj->mt->cpp;
 312    key.tiling = intelObj->mt->region->tiling;
 313
 314    dri_bo_unreference(brw->wm.surf_bo[surf]);
 315    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 316                                             BRW_SS_SURFACE,
 317                                             &key, sizeof(key),
 318                                             &key.bo, key.bo ? 1 : 0,
 319                                             NULL);
 320    if (brw->wm.surf_bo[surf] == NULL) {
 321       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
 322    }
 323 }
 324
 325
 326
 327 /**
 328  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 329  * read from this buffer with Data Port Read instructions/messages.
 330  */
 331 dri_bo *
 332 brw_create_constant_surface( struct brw_context *brw,
 333                              struct brw_surface_key *key )
 334 {
 335    const GLint w = key->width - 1;
 336    struct brw_surface_state surf;
 337    dri_bo *bo;
 338
 339    memset(&surf, 0, sizeof(surf));
 340
 341    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 342    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 343    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 344
 345    assert(key->bo);
 346    if (key->bo)
 347       surf.ss1.base_addr = key->bo->offset; /* reloc */
 348    else
 349       surf.ss1.base_addr = key->offset;
 350
 351    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 352    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 353    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 354    surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
 355    brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
 356
 357    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 358                          key, sizeof(*key),
 359                          &key->bo, key->bo ? 1 : 0,
 360                          &surf, sizeof(surf),
 361                          NULL, NULL);
 362
 363    if (key->bo) {
 364       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 365        * bspec ("Data Cache") says that the data cache does not exist as
 366        * a separate cache and is just the sampler cache.
 367        */
 368       dri_bo_emit_reloc(bo,
 369                         I915_GEM_DOMAIN_SAMPLER, 0,
 370                         0,
 371                         offsetof(struct brw_surface_state, ss1),
 372                         key->bo);
 373    }
 374
 375    return bo;
 376 }
 377
 378 /* Creates a new WM constant buffer reflecting the current fragment program's
 379  * constants, if needed by the fragment program.
 380  *
 381  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 382  * state atom.
 383  */
 384 static drm_intel_bo *
 385 brw_wm_update_constant_buffer(struct brw_context *brw)
 386 {
 387    struct intel_context *intel = &brw->intel;
 388    struct brw_fragment_program *fp =
 389       (struct brw_fragment_program *) brw->fragment_program;
 390    const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 391    const int size = params->NumParameters * 4 * sizeof(GLfloat);
 392    drm_intel_bo *const_buffer;
 393
 394    /* BRW_NEW_FRAGMENT_PROGRAM */
 395    if (!fp->use_const_buffer)
 396       return NULL;
 397
 398    const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
 399                                      size, 64);
 400
 401    /* _NEW_PROGRAM_CONSTANTS */
 402    dri_bo_subdata(const_buffer, 0, size, params->ParameterValues);
 403
 404    return const_buffer;
 405 }
 406
 407 /**
 408  * Update the surface state for a WM constant buffer.
 409  * The constant buffer will be (re)allocated here if needed.
 410  */
 411 static void
 412 brw_update_wm_constant_surface( GLcontext *ctx,
 413                                 GLuint surf)
 414 {
 415    struct brw_context *brw = brw_context(ctx);
 416    struct brw_surface_key key;
 417    struct brw_fragment_program *fp =
 418       (struct brw_fragment_program *) brw->fragment_program;
 419    const struct gl_program_parameter_list *params =
 420       fp->program.Base.Parameters;
 421
 422    /* If we're in this state update atom, we need to update WM constants, so
 423     * free the old buffer and create a new one for the new contents.
 424     */
 425    dri_bo_unreference(fp->const_buffer);
 426    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 427
 428    /* If there's no constant buffer, then no surface BO is needed to point at
 429     * it.
 430     */
 431    if (fp->const_buffer == 0) {
 432       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 433       brw->wm.surf_bo[surf] = NULL;
 434       return;
 435    }
 436
 437    memset(&key, 0, sizeof(key));
 438
 439    key.format = MESA_FORMAT_RGBA_FLOAT32;
 440    key.internal_format = GL_RGBA;
 441    key.bo = fp->const_buffer;
 442    key.depthmode = GL_NONE;
 443    key.pitch = params->NumParameters;
 444    key.width = params->NumParameters;
 445    key.height = 1;
 446    key.depth = 1;
 447    key.cpp = 16;
 448
 449    /*
 450    printf("%s:\n", __FUNCTION__);
 451    printf("  width %d  height %d  depth %d  cpp %d  pitch %d\n",
 452           key.width, key.height, key.depth, key.cpp, key.pitch);
 453    */
 454
 455    dri_bo_unreference(brw->wm.surf_bo[surf]);
 456    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 457                                             BRW_SS_SURFACE,
 458                                             &key, sizeof(key),
 459                                             &key.bo, key.bo ? 1 : 0,
 460                                             NULL);
 461    if (brw->wm.surf_bo[surf] == NULL) {
 462       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
 463    }
 464    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 465 }
 466
 467 /**
 468  * Updates surface / buffer for fragment shader constant buffer, if
 469  * one is required.
 470  *
 471  * This consumes the state updates for the constant buffer, and produces
 472  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 473  * inclusion in the binding table.
 474  */
 475 static void prepare_wm_constant_surface(struct brw_context *brw )
 476 {
 477    GLcontext *ctx = &brw->intel.ctx;
 478    struct brw_fragment_program *fp =
 479       (struct brw_fragment_program *) brw->fragment_program;
 480    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 481
 482    drm_intel_bo_unreference(fp->const_buffer);
 483    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 484
 485    /* If there's no constant buffer, then no surface BO is needed to point at
 486     * it.
 487     */
 488    if (fp->const_buffer == 0) {
 489       if (brw->wm.surf_bo[surf] != NULL) {
 490          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 491          brw->wm.surf_bo[surf] = NULL;
 492          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 493       }
 494       return;
 495    }
 496
 497    brw_update_wm_constant_surface(ctx, surf);
 498 }
 499
 500 const struct brw_tracked_state brw_wm_constant_surface = {
 501    .dirty = {
 502       .mesa = (_NEW_PROGRAM_CONSTANTS),
 503       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 504       .cache = 0
 505    },
 506    .prepare = prepare_wm_constant_surface,
 507 };
 508
 509
 510 /**
 511  * Sets up a surface state structure to point at the given region.
 512  * While it is only used for the front/back buffer currently, it should be
 513  * usable for further buffers when doing ARB_draw_buffer support.
 514  */
 515 static void
 516 brw_update_renderbuffer_surface(struct brw_context *brw,
 517                                 struct gl_renderbuffer *rb,
 518                                 unsigned int unit)
 519 {
 520    GLcontext *ctx = &brw->intel.ctx;
 521    dri_bo *region_bo = NULL;
 522    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 523    struct intel_region *region = irb ? irb->region : NULL;
 524    struct {
 525       unsigned int surface_type;
 526       unsigned int surface_format;
 527       unsigned int width, height, pitch, cpp;
 528       GLubyte color_mask[4];
 529       GLboolean color_blend;
 530       uint32_t tiling;
 531       uint32_t draw_offset;
 532    } key;
 533
 534    memset(&key, 0, sizeof(key));
 535
 536    if (region != NULL) {
 537       region_bo = region->buffer;
 538
 539       key.surface_type = BRW_SURFACE_2D;
 540       switch (irb->texformat) {
 541       case MESA_FORMAT_ARGB8888:
 542          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 543          break;
 544       case MESA_FORMAT_XRGB8888:
 545          key.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 546          break;
 547       case MESA_FORMAT_RGB565:
 548          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 549          break;
 550       case MESA_FORMAT_ARGB1555:
 551          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 552          break;
 553       case MESA_FORMAT_ARGB4444:
 554          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 555          break;
 556       default:
 557          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat);
 558       }
 559       key.tiling = region->tiling;
 560       if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
 561          key.width = rb->Width;
 562          key.height = rb->Height;
 563       } else {
 564          key.width = region->width;
 565          key.height = region->height;
 566       }
 567       key.pitch = region->pitch;
 568       key.cpp = region->cpp;
 569       key.draw_offset = region->draw_offset; /* cur 3d or cube face offset */
 570    } else {
 571       key.surface_type = BRW_SURFACE_NULL;
 572       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 573       key.tiling = I915_TILING_X;
 574       key.width = 1;
 575       key.height = 1;
 576       key.cpp = 4;
 577       key.draw_offset = 0;
 578    }
 579    /* _NEW_COLOR */
 580    memcpy(key.color_mask, ctx->Color.ColorMask,
 581           sizeof(key.color_mask));
 582    key.color_blend = (!ctx->Color._LogicOpEnabled &&
 583                       ctx->Color.BlendEnabled);
 584
 585    dri_bo_unreference(brw->wm.surf_bo[unit]);
 586    brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
 587                                             BRW_SS_SURFACE,
 588                                             &key, sizeof(key),
 589                                             &region_bo, 1,
 590                                             NULL);
 591
 592    if (brw->wm.surf_bo[unit] == NULL) {
 593       struct brw_surface_state surf;
 594
 595       memset(&surf, 0, sizeof(surf));
 596
 597       surf.ss0.surface_format = key.surface_format;
 598       surf.ss0.surface_type = key.surface_type;
 599       if (key.tiling == I915_TILING_NONE) {
 600          surf.ss1.base_addr = key.draw_offset;
 601       } else {
 602          uint32_t tile_offset = key.draw_offset % 4096;
 603
 604          surf.ss1.base_addr = key.draw_offset - tile_offset;
 605
 606          assert(BRW_IS_G4X(brw) || tile_offset == 0);
 607          if (BRW_IS_G4X(brw)) {
 608             if (key.tiling == I915_TILING_X) {
 609                /* Note that the low bits of these fields are missing, so
 610                 * there's the possibility of getting in trouble.
 611                 */
 612                surf.ss5.x_offset = (tile_offset % 512) / key.cpp / 4;
 613                surf.ss5.y_offset = tile_offset / 512 / 2;
 614             } else {
 615                surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4;
 616                surf.ss5.y_offset = tile_offset / 128 / 2;
 617             }
 618          }
 619       }
 620       if (region_bo != NULL)
 621          surf.ss1.base_addr += region_bo->offset; /* reloc */
 622
 623       surf.ss2.width = key.width - 1;
 624       surf.ss2.height = key.height - 1;
 625       brw_set_surface_tiling(&surf, key.tiling);
 626       surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 627
 628       /* _NEW_COLOR */
 629       surf.ss0.color_blend = key.color_blend;
 630       surf.ss0.writedisable_red =   !key.color_mask[0];
 631       surf.ss0.writedisable_green = !key.color_mask[1];
 632       surf.ss0.writedisable_blue =  !key.color_mask[2];
 633       surf.ss0.writedisable_alpha = !key.color_mask[3];
 634
 635       /* Key size will never match key size for textures, so we're safe. */
 636       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
 637                                                BRW_SS_SURFACE,
 638                                                &key, sizeof(key),
 639                                                &region_bo, 1,
 640                                                &surf, sizeof(surf),
 641                                                NULL, NULL);
 642       if (region_bo != NULL) {
 643          /* We might sample from it, and we might render to it, so flag
 644           * them both.  We might be able to figure out from other state
 645           * a more restrictive relocation to emit.
 646           */
 647          drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 648                                  offsetof(struct brw_surface_state, ss1),
 649                                  region_bo,
 650                                  surf.ss1.base_addr - region_bo->offset,
 651                                  I915_GEM_DOMAIN_RENDER,
 652                                  I915_GEM_DOMAIN_RENDER);
 653       }
 654    }
 655 }
 656
 657
 658 /**
 659  * Constructs the binding table for the WM surface state, which maps unit
 660  * numbers to surface state objects.
 661  */
 662 static dri_bo *
 663 brw_wm_get_binding_table(struct brw_context *brw)
 664 {
 665    dri_bo *bind_bo;
 666
 667    assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF);
 668
 669    bind_bo = brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND,
 670                               NULL, 0,
 671                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 672                               NULL);
 673
 674    if (bind_bo == NULL) {
 675       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 676       uint32_t data[BRW_WM_MAX_SURF];
 677       int i;
 678
 679       for (i = 0; i < brw->wm.nr_surfaces; i++)
 680          if (brw->wm.surf_bo[i])
 681             data[i] = brw->wm.surf_bo[i]->offset;
 682          else
 683             data[i] = 0;
 684
 685       bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
 686                                   NULL, 0,
 687                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 688                                   data, data_size,
 689                                   NULL, NULL);
 690
 691       /* Emit binding table relocations to surface state */
 692       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 693          if (brw->wm.surf_bo[i] != NULL) {
 694             dri_bo_emit_reloc(bind_bo,
 695                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 696                               0,
 697                               i * sizeof(GLuint),
 698                               brw->wm.surf_bo[i]);
 699          }
 700       }
 701    }
 702
 703    return bind_bo;
 704 }
 705
 706 static void prepare_wm_surfaces(struct brw_context *brw )
 707 {
 708    GLcontext *ctx = &brw->intel.ctx;
 709    GLuint i;
 710    int old_nr_surfaces;
 711
 712    /* _NEW_BUFFERS | _NEW_COLOR */
 713    /* Update surfaces for drawing buffers */
 714    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 715       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 716          brw_update_renderbuffer_surface(brw,
 717                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 718                                          i);
 719       }
 720    } else {
 721       brw_update_renderbuffer_surface(brw, NULL, 0);
 722    }
 723
 724    old_nr_surfaces = brw->wm.nr_surfaces;
 725    brw->wm.nr_surfaces = BRW_MAX_DRAW_BUFFERS;
 726
 727    if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
 728        brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 729
 730    /* Update surfaces for textures */
 731    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 732       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 733       const GLuint surf = SURF_INDEX_TEXTURE(i);
 734
 735       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 736       if (texUnit->_ReallyEnabled) {
 737          brw_update_texture_surface(ctx, i);
 738          brw->wm.nr_surfaces = surf + 1;
 739       } else {
 740          dri_bo_unreference(brw->wm.surf_bo[surf]);
 741          brw->wm.surf_bo[surf] = NULL;
 742       }
 743    }
 744
 745    dri_bo_unreference(brw->wm.bind_bo);
 746    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 747
 748    if (brw->wm.nr_surfaces != old_nr_surfaces)
 749       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 750 }
 751
 752 const struct brw_tracked_state brw_wm_surfaces = {
 753    .dirty = {
 754       .mesa = (_NEW_COLOR |
 755                _NEW_TEXTURE |
 756                _NEW_BUFFERS),
 757       .brw = (BRW_NEW_CONTEXT |
 758               BRW_NEW_WM_SURFACES),
 759       .cache = 0
 760    },
 761    .prepare = prepare_wm_surfaces,
 762 };
 763
 764
 765