2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "compiler/nir/nir.h"
34 #include "main/context.h"
35 #include "main/blend.h"
36 #include "main/mtypes.h"
37 #include "main/samplerobj.h"
38 #include "main/shaderimage.h"
39 #include "main/teximage.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_instruction.h"
42 #include "main/framebuffer.h"
43 #include "main/shaderapi.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_batchbuffer.h"
49 #include "intel_tex.h"
50 #include "intel_fbo.h"
51 #include "intel_buffer_objects.h"
53 #include "brw_context.h"
54 #include "brw_state.h"
55 #include "brw_defines.h"
59 INTEL_RENDERBUFFER_LAYERED
= 1 << 0,
60 INTEL_AUX_BUFFER_DISABLED
= 1 << 1,
63 uint32_t tex_mocs
[] = {
69 uint32_t rb_mocs
[] = {
76 brw_emit_surface_state(struct brw_context
*brw
,
77 struct intel_mipmap_tree
*mt
, uint32_t flags
,
78 GLenum target
, struct isl_view view
,
79 uint32_t mocs
, uint32_t *surf_offset
, int surf_index
,
80 unsigned read_domains
, unsigned write_domains
)
82 uint32_t tile_x
= mt
->level
[0].slice
[0].x_offset
;
83 uint32_t tile_y
= mt
->level
[0].slice
[0].y_offset
;
84 uint32_t offset
= mt
->offset
;
87 intel_miptree_get_isl_surf(brw
, mt
, &surf
);
89 surf
.dim
= get_isl_surf_dim(target
);
91 const enum isl_dim_layout dim_layout
=
92 get_isl_dim_layout(&brw
->screen
->devinfo
, mt
->tiling
, target
,
95 if (surf
.dim_layout
!= dim_layout
) {
96 /* The layout of the specified texture target is not compatible with the
97 * actual layout of the miptree structure in memory -- You're entering
98 * dangerous territory, this can only possibly work if you only intended
99 * to access a single level and slice of the texture, and the hardware
100 * supports the tile offset feature in order to allow non-tile-aligned
101 * base offsets, since we'll have to point the hardware to the first
102 * texel of the level instead of relying on the usual base level/layer
105 assert(brw
->has_surface_tile_offset
);
106 assert(view
.levels
== 1 && view
.array_len
== 1);
107 assert(tile_x
== 0 && tile_y
== 0);
109 offset
+= intel_miptree_get_tile_offsets(mt
, view
.base_level
,
110 view
.base_array_layer
,
113 /* Minify the logical dimensions of the texture. */
114 const unsigned l
= view
.base_level
- mt
->first_level
;
115 surf
.logical_level0_px
.width
= minify(surf
.logical_level0_px
.width
, l
);
116 surf
.logical_level0_px
.height
= surf
.dim
<= ISL_SURF_DIM_1D
? 1 :
117 minify(surf
.logical_level0_px
.height
, l
);
118 surf
.logical_level0_px
.depth
= surf
.dim
<= ISL_SURF_DIM_2D
? 1 :
119 minify(surf
.logical_level0_px
.depth
, l
);
121 /* Only the base level and layer can be addressed with the overridden
124 surf
.logical_level0_px
.array_len
= 1;
126 surf
.dim_layout
= dim_layout
;
128 /* The requested slice of the texture is now at the base level and
132 view
.base_array_layer
= 0;
135 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
137 struct brw_bo
*aux_bo
;
138 struct isl_surf
*aux_surf
= NULL
, aux_surf_s
;
139 uint64_t aux_offset
= 0;
140 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
141 if ((mt
->mcs_buf
|| intel_miptree_sample_with_hiz(brw
, mt
)) &&
142 !(flags
& INTEL_AUX_BUFFER_DISABLED
)) {
143 intel_miptree_get_aux_isl_surf(brw
, mt
, &aux_surf_s
, &aux_usage
);
144 aux_surf
= &aux_surf_s
;
147 aux_bo
= mt
->mcs_buf
->bo
;
148 aux_offset
= mt
->mcs_buf
->bo
->offset64
+ mt
->mcs_buf
->offset
;
150 aux_bo
= mt
->hiz_buf
->aux_base
.bo
;
151 aux_offset
= mt
->hiz_buf
->aux_base
.bo
->offset64
;
154 /* We only really need a clear color if we also have an auxiliary
155 * surface. Without one, it does nothing.
157 clear_color
= intel_miptree_get_isl_clear_color(brw
, mt
);
160 void *state
= brw_state_batch(brw
,
161 brw
->isl_dev
.ss
.size
,
162 brw
->isl_dev
.ss
.align
,
165 isl_surf_fill_state(&brw
->isl_dev
, state
, .surf
= &surf
, .view
= &view
,
166 .address
= mt
->bo
->offset64
+ offset
,
167 .aux_surf
= aux_surf
, .aux_usage
= aux_usage
,
168 .aux_address
= aux_offset
,
169 .mocs
= mocs
, .clear_color
= clear_color
,
170 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
172 brw_emit_reloc(&brw
->batch
, *surf_offset
+ brw
->isl_dev
.ss
.addr_offset
,
173 mt
->bo
, offset
, read_domains
, write_domains
);
176 /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
177 * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
178 * contain other control information. Since buffer addresses are always
179 * on 4k boundaries (and thus have their lower 12 bits zero), we can use
180 * an ordinary reloc to do the necessary address translation.
182 assert((aux_offset
& 0xfff) == 0);
183 uint32_t *aux_addr
= state
+ brw
->isl_dev
.ss
.aux_addr_offset
;
184 brw_emit_reloc(&brw
->batch
,
185 *surf_offset
+ brw
->isl_dev
.ss
.aux_addr_offset
,
186 aux_bo
, *aux_addr
- aux_bo
->offset64
,
187 read_domains
, write_domains
);
192 brw_update_renderbuffer_surface(struct brw_context
*brw
,
193 struct gl_renderbuffer
*rb
,
194 uint32_t flags
, unsigned unit
/* unused */,
197 struct gl_context
*ctx
= &brw
->ctx
;
198 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
199 struct intel_mipmap_tree
*mt
= irb
->mt
;
202 assert(!(flags
& INTEL_AUX_BUFFER_DISABLED
));
205 assert(brw_render_target_supported(brw
, rb
));
207 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
208 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
209 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
210 __func__
, _mesa_get_format_name(rb_format
));
213 const unsigned layer_multiplier
=
214 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
215 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
216 MAX2(irb
->mt
->num_samples
, 1) : 1;
218 struct isl_view view
= {
219 .format
= brw
->render_target_format
[rb_format
],
220 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
222 .base_array_layer
= irb
->mt_layer
/ layer_multiplier
,
223 .array_len
= MAX2(irb
->layer_count
, 1),
224 .swizzle
= ISL_SWIZZLE_IDENTITY
,
225 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
229 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
232 I915_GEM_DOMAIN_RENDER
,
233 I915_GEM_DOMAIN_RENDER
);
238 translate_tex_target(GLenum target
)
242 case GL_TEXTURE_1D_ARRAY_EXT
:
243 return BRW_SURFACE_1D
;
245 case GL_TEXTURE_RECTANGLE_NV
:
246 return BRW_SURFACE_2D
;
249 case GL_TEXTURE_2D_ARRAY_EXT
:
250 case GL_TEXTURE_EXTERNAL_OES
:
251 case GL_TEXTURE_2D_MULTISAMPLE
:
252 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
253 return BRW_SURFACE_2D
;
256 return BRW_SURFACE_3D
;
258 case GL_TEXTURE_CUBE_MAP
:
259 case GL_TEXTURE_CUBE_MAP_ARRAY
:
260 return BRW_SURFACE_CUBE
;
263 unreachable("not reached");
268 brw_get_surface_tiling_bits(uint32_t tiling
)
272 return BRW_SURFACE_TILED
;
274 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
282 brw_get_surface_num_multisamples(unsigned num_samples
)
285 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
287 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
291 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
295 brw_get_texture_swizzle(const struct gl_context
*ctx
,
296 const struct gl_texture_object
*t
)
298 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
300 int swizzles
[SWIZZLE_NIL
+ 1] = {
310 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
311 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
312 GLenum depth_mode
= t
->DepthMode
;
314 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
315 * with depth component data specified with a sized internal format.
316 * Otherwise, it's left at the old default, GL_LUMINANCE.
318 if (_mesa_is_gles3(ctx
) &&
319 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
320 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
324 switch (depth_mode
) {
326 swizzles
[0] = SWIZZLE_ZERO
;
327 swizzles
[1] = SWIZZLE_ZERO
;
328 swizzles
[2] = SWIZZLE_ZERO
;
329 swizzles
[3] = SWIZZLE_X
;
332 swizzles
[0] = SWIZZLE_X
;
333 swizzles
[1] = SWIZZLE_X
;
334 swizzles
[2] = SWIZZLE_X
;
335 swizzles
[3] = SWIZZLE_ONE
;
338 swizzles
[0] = SWIZZLE_X
;
339 swizzles
[1] = SWIZZLE_X
;
340 swizzles
[2] = SWIZZLE_X
;
341 swizzles
[3] = SWIZZLE_X
;
344 swizzles
[0] = SWIZZLE_X
;
345 swizzles
[1] = SWIZZLE_ZERO
;
346 swizzles
[2] = SWIZZLE_ZERO
;
347 swizzles
[3] = SWIZZLE_ONE
;
352 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
354 /* If the texture's format is alpha-only, force R, G, and B to
355 * 0.0. Similarly, if the texture's format has no alpha channel,
356 * force the alpha value read to 1.0. This allows for the
357 * implementation to use an RGBA texture for any of these formats
358 * without leaking any unexpected values.
360 switch (img
->_BaseFormat
) {
362 swizzles
[0] = SWIZZLE_ZERO
;
363 swizzles
[1] = SWIZZLE_ZERO
;
364 swizzles
[2] = SWIZZLE_ZERO
;
367 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
368 swizzles
[0] = SWIZZLE_X
;
369 swizzles
[1] = SWIZZLE_X
;
370 swizzles
[2] = SWIZZLE_X
;
371 swizzles
[3] = SWIZZLE_ONE
;
374 case GL_LUMINANCE_ALPHA
:
375 if (datatype
== GL_SIGNED_NORMALIZED
) {
376 swizzles
[0] = SWIZZLE_X
;
377 swizzles
[1] = SWIZZLE_X
;
378 swizzles
[2] = SWIZZLE_X
;
379 swizzles
[3] = SWIZZLE_W
;
383 if (datatype
== GL_SIGNED_NORMALIZED
) {
384 swizzles
[0] = SWIZZLE_X
;
385 swizzles
[1] = SWIZZLE_X
;
386 swizzles
[2] = SWIZZLE_X
;
387 swizzles
[3] = SWIZZLE_X
;
393 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0 ||
394 img
->TexFormat
== MESA_FORMAT_RGB_DXT1
||
395 img
->TexFormat
== MESA_FORMAT_SRGB_DXT1
)
396 swizzles
[3] = SWIZZLE_ONE
;
400 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
401 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
402 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
403 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
407 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
408 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
410 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
413 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
415 * which is simply adding 4 then modding by 8 (or anding with 7).
417 * We then may need to apply workarounds for textureGather hardware bugs.
420 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
422 unsigned scs
= (swizzle
+ 4) & 7;
424 return (need_green_to_blue
&& scs
== HSW_SCS_GREEN
) ? HSW_SCS_BLUE
: scs
;
428 brw_find_matching_rb(const struct gl_framebuffer
*fb
,
429 const struct intel_mipmap_tree
*mt
)
431 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
432 const struct intel_renderbuffer
*irb
=
433 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
435 if (irb
&& irb
->mt
== mt
)
439 return fb
->_NumColorDrawBuffers
;
443 brw_texture_view_sane(const struct brw_context
*brw
,
444 const struct intel_mipmap_tree
*mt
,
445 const struct isl_view
*view
)
447 /* There are special cases only for lossless compression. */
448 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
451 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, view
->format
))
454 /* Logic elsewhere needs to take care to resolve the color buffer prior
455 * to sampling it as non-compressed.
457 if (intel_miptree_has_color_unresolved(mt
, view
->base_level
, view
->levels
,
458 view
->base_array_layer
,
462 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
463 const unsigned rb_index
= brw_find_matching_rb(fb
, mt
);
465 if (rb_index
== fb
->_NumColorDrawBuffers
)
468 /* Underlying surface is compressed but it is sampled using a format that
469 * the sampling engine doesn't support as compressed. Compression must be
470 * disabled for both sampling engine and data port in case the same surface
471 * is used also as render target.
473 return brw
->draw_aux_buffer_disabled
[rb_index
];
477 brw_disable_aux_surface(const struct brw_context
*brw
,
478 const struct intel_mipmap_tree
*mt
,
479 const struct isl_view
*view
)
481 /* Nothing to disable. */
485 const bool is_unresolved
= intel_miptree_has_color_unresolved(
486 mt
, view
->base_level
, view
->levels
,
487 view
->base_array_layer
, view
->array_len
);
489 /* There are special cases only for lossless compression. */
490 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
491 return !is_unresolved
;
493 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
494 const unsigned rb_index
= brw_find_matching_rb(fb
, mt
);
496 /* If we are drawing into this with compression enabled, then we must also
497 * enable compression when texturing from it regardless of
498 * fast_clear_state. If we don't then, after the first draw call with
499 * this setup, there will be data in the CCS which won't get picked up by
500 * subsequent texturing operations as required by ARB_texture_barrier.
501 * Since we don't want to re-emit the binding table or do a resolve
502 * operation every draw call, the easiest thing to do is just enable
503 * compression on the texturing side. This is completely safe to do
504 * since, if compressed texturing weren't allowed, we would have disabled
505 * compression of render targets in whatever_that_function_is_called().
507 if (rb_index
< fb
->_NumColorDrawBuffers
) {
508 if (brw
->draw_aux_buffer_disabled
[rb_index
]) {
509 assert(!is_unresolved
);
512 return brw
->draw_aux_buffer_disabled
[rb_index
];
515 return !is_unresolved
;
519 brw_update_texture_surface(struct gl_context
*ctx
,
521 uint32_t *surf_offset
,
525 struct brw_context
*brw
= brw_context(ctx
);
526 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
528 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
529 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
532 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
533 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
536 if (mt
->plane
[plane
- 1] == NULL
)
538 mt
= mt
->plane
[plane
- 1];
541 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
542 /* If this is a view with restricted NumLayers, then our effective depth
543 * is not just the miptree depth.
545 const unsigned view_num_layers
=
546 (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
) ? obj
->NumLayers
:
549 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
550 * texturing functions that return a float, as our code generation always
551 * selects the .x channel (which would always be 0).
553 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
554 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
555 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
556 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
557 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
558 brw_get_texture_swizzle(&brw
->ctx
, obj
));
560 mesa_format mesa_fmt
= plane
== 0 ? intel_obj
->_Format
: mt
->format
;
561 enum isl_format format
= translate_tex_format(brw
, mesa_fmt
,
562 sampler
->sRGBDecode
);
564 /* Implement gen6 and gen7 gather work-around */
565 bool need_green_to_blue
= false;
567 if (brw
->gen
== 7 && (format
== ISL_FORMAT_R32G32_FLOAT
||
568 format
== ISL_FORMAT_R32G32_SINT
||
569 format
== ISL_FORMAT_R32G32_UINT
)) {
570 format
= ISL_FORMAT_R32G32_FLOAT_LD
;
571 need_green_to_blue
= brw
->is_haswell
;
572 } else if (brw
->gen
== 6) {
573 /* Sandybridge's gather4 message is broken for integer formats.
574 * To work around this, we pretend the surface is UNORM for
575 * 8 or 16-bit formats, and emit shader instructions to recover
576 * the real INT/UINT value. For 32-bit formats, we pretend
577 * the surface is FLOAT, and simply reinterpret the resulting
581 case ISL_FORMAT_R8_SINT
:
582 case ISL_FORMAT_R8_UINT
:
583 format
= ISL_FORMAT_R8_UNORM
;
586 case ISL_FORMAT_R16_SINT
:
587 case ISL_FORMAT_R16_UINT
:
588 format
= ISL_FORMAT_R16_UNORM
;
591 case ISL_FORMAT_R32_SINT
:
592 case ISL_FORMAT_R32_UINT
:
593 format
= ISL_FORMAT_R32_FLOAT
;
602 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
604 assert(mt
->r8stencil_mt
&& !mt
->stencil_mt
->r8stencil_needs_update
);
605 mt
= mt
->r8stencil_mt
;
609 format
= ISL_FORMAT_R8_UINT
;
610 } else if (brw
->gen
<= 7 && mt
->format
== MESA_FORMAT_S_UINT8
) {
611 assert(mt
->r8stencil_mt
&& !mt
->r8stencil_needs_update
);
612 mt
= mt
->r8stencil_mt
;
613 format
= ISL_FORMAT_R8_UINT
;
616 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
618 struct isl_view view
= {
620 .base_level
= obj
->MinLevel
+ obj
->BaseLevel
,
621 .levels
= intel_obj
->_MaxLevel
- obj
->BaseLevel
+ 1,
622 .base_array_layer
= obj
->MinLayer
,
623 .array_len
= view_num_layers
,
625 .r
= swizzle_to_scs(GET_SWZ(swizzle
, 0), need_green_to_blue
),
626 .g
= swizzle_to_scs(GET_SWZ(swizzle
, 1), need_green_to_blue
),
627 .b
= swizzle_to_scs(GET_SWZ(swizzle
, 2), need_green_to_blue
),
628 .a
= swizzle_to_scs(GET_SWZ(swizzle
, 3), need_green_to_blue
),
630 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
633 if (obj
->Target
== GL_TEXTURE_CUBE_MAP
||
634 obj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
635 view
.usage
|= ISL_SURF_USAGE_CUBE_BIT
;
637 assert(brw_texture_view_sane(brw
, mt
, &view
));
639 const int flags
= brw_disable_aux_surface(brw
, mt
, &view
) ?
640 INTEL_AUX_BUFFER_DISABLED
: 0;
641 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
643 surf_offset
, surf_index
,
644 I915_GEM_DOMAIN_SAMPLER
, 0);
649 brw_emit_buffer_surface_state(struct brw_context
*brw
,
650 uint32_t *out_offset
,
652 unsigned buffer_offset
,
653 unsigned surface_format
,
654 unsigned buffer_size
,
658 uint32_t *dw
= brw_state_batch(brw
,
659 brw
->isl_dev
.ss
.size
,
660 brw
->isl_dev
.ss
.align
,
663 isl_buffer_fill_state(&brw
->isl_dev
, dw
,
664 .address
= (bo
? bo
->offset64
: 0) + buffer_offset
,
666 .format
= surface_format
,
668 .mocs
= tex_mocs
[brw
->gen
]);
671 brw_emit_reloc(&brw
->batch
, *out_offset
+ brw
->isl_dev
.ss
.addr_offset
,
673 I915_GEM_DOMAIN_SAMPLER
,
674 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
679 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
681 uint32_t *surf_offset
)
683 struct brw_context
*brw
= brw_context(ctx
);
684 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
685 struct intel_buffer_object
*intel_obj
=
686 intel_buffer_object(tObj
->BufferObject
);
687 uint32_t size
= tObj
->BufferSize
;
688 struct brw_bo
*bo
= NULL
;
689 mesa_format format
= tObj
->_BufferObjectFormat
;
690 const enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
691 int texel_size
= _mesa_get_format_bytes(format
);
694 size
= MIN2(size
, intel_obj
->Base
.Size
);
695 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
698 /* The ARB_texture_buffer_specification says:
700 * "The number of texels in the buffer texture's texel array is given by
702 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
704 * where <buffer_size> is the size of the buffer object, in basic
705 * machine units and <components> and <base_type> are the element count
706 * and base data type for elements, as specified in Table X.1. The
707 * number of texels in the texel array is then clamped to the
708 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
710 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
711 * so that when ISL divides by stride to obtain the number of texels, that
712 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
714 size
= MIN2(size
, ctx
->Const
.MaxTextureBufferSize
* (unsigned) texel_size
);
716 if (isl_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
717 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
718 _mesa_get_format_name(format
));
721 brw_emit_buffer_surface_state(brw
, surf_offset
, bo
,
730 * Create the constant buffer surface. Vertex/fragment shader constants will be
731 * read from this buffer with Data Port Read instructions/messages.
734 brw_create_constant_surface(struct brw_context
*brw
,
738 uint32_t *out_offset
)
740 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
741 ISL_FORMAT_R32G32B32A32_FLOAT
,
746 * Create the buffer surface. Shader buffer variables will be
747 * read from / write to this buffer with Data Port Read/Write
748 * instructions/messages.
751 brw_create_buffer_surface(struct brw_context
*brw
,
755 uint32_t *out_offset
)
757 /* Use a raw surface so we can reuse existing untyped read/write/atomic
758 * messages. We need these specifically for the fragment shader since they
759 * include a pixel mask header that we need to ensure correct behavior
760 * with helper invocations, which cannot write to the buffer.
762 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
768 * Set up a binding table entry for use by stream output logic (transform
771 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
774 brw_update_sol_surface(struct brw_context
*brw
,
775 struct gl_buffer_object
*buffer_obj
,
776 uint32_t *out_offset
, unsigned num_vector_components
,
777 unsigned stride_dwords
, unsigned offset_dwords
)
779 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
780 uint32_t offset_bytes
= 4 * offset_dwords
;
781 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
783 buffer_obj
->Size
- offset_bytes
);
784 uint32_t *surf
= brw_state_batch(brw
, 6 * 4, 32, out_offset
);
785 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
786 size_t size_dwords
= buffer_obj
->Size
/ 4;
787 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
789 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
790 * too big to map using a single binding table entry?
792 assert((size_dwords
- offset_dwords
) / stride_dwords
793 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
795 if (size_dwords
> offset_dwords
+ num_vector_components
) {
796 /* There is room for at least 1 transform feedback output in the buffer.
797 * Compute the number of additional transform feedback outputs the
798 * buffer has room for.
800 buffer_size_minus_1
=
801 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
803 /* There isn't even room for a single transform feedback output in the
804 * buffer. We can't configure the binding table entry to prevent output
805 * entirely; we'll have to rely on the geometry shader to detect
806 * overflow. But to minimize the damage in case of a bug, set up the
807 * binding table entry to just allow a single output.
809 buffer_size_minus_1
= 0;
811 width
= buffer_size_minus_1
& 0x7f;
812 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
813 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
815 switch (num_vector_components
) {
817 surface_format
= ISL_FORMAT_R32_FLOAT
;
820 surface_format
= ISL_FORMAT_R32G32_FLOAT
;
823 surface_format
= ISL_FORMAT_R32G32B32_FLOAT
;
826 surface_format
= ISL_FORMAT_R32G32B32A32_FLOAT
;
829 unreachable("Invalid vector size for transform feedback output");
832 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
833 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
834 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
835 BRW_SURFACE_RC_READ_WRITE
;
836 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
837 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
838 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
839 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
840 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
844 /* Emit relocation to surface contents. */
845 brw_emit_reloc(&brw
->batch
, *out_offset
+ 4, bo
, offset_bytes
,
846 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
849 /* Creates a new WM constant buffer reflecting the current fragment program's
850 * constants, if needed by the fragment program.
852 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
856 brw_upload_wm_pull_constants(struct brw_context
*brw
)
858 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
859 /* BRW_NEW_FRAGMENT_PROGRAM */
860 struct brw_program
*fp
= (struct brw_program
*) brw
->fragment_program
;
861 /* BRW_NEW_FS_PROG_DATA */
862 struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
864 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
865 /* _NEW_PROGRAM_CONSTANTS */
866 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
,
867 stage_state
, prog_data
);
870 const struct brw_tracked_state brw_wm_pull_constants
= {
872 .mesa
= _NEW_PROGRAM_CONSTANTS
,
873 .brw
= BRW_NEW_BATCH
|
875 BRW_NEW_FRAGMENT_PROGRAM
|
876 BRW_NEW_FS_PROG_DATA
,
878 .emit
= brw_upload_wm_pull_constants
,
882 * Creates a null renderbuffer surface.
884 * This is used when the shader doesn't write to any color output. An FB
885 * write to target 0 will still be emitted, because that's how the thread is
886 * terminated (and computed depth is returned), so we need to have the
887 * hardware discard the target 0 color output..
890 brw_emit_null_surface_state(struct brw_context
*brw
,
894 uint32_t *out_offset
)
896 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
899 * A null surface will be used in instances where an actual surface is
900 * not bound. When a write message is generated to a null surface, no
901 * actual surface is written to. When a read message (including any
902 * sampling engine message) is generated to a null surface, the result
903 * is all zeros. Note that a null surface type is allowed to be used
904 * with all messages, even if it is not specificially indicated as
905 * supported. All of the remaining fields in surface state are ignored
906 * for null surfaces, with the following exceptions:
908 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
909 * depth buffer’s corresponding state for all render target surfaces,
912 * - Surface Format must be R8G8B8A8_UNORM.
914 unsigned surface_type
= BRW_SURFACE_NULL
;
915 struct brw_bo
*bo
= NULL
;
916 unsigned pitch_minus_1
= 0;
917 uint32_t multisampling_state
= 0;
918 uint32_t *surf
= brw_state_batch(brw
, 6 * 4, 32, out_offset
);
921 /* On Gen6, null render targets seem to cause GPU hangs when
922 * multisampling. So work around this problem by rendering into dummy
925 * To decrease the amount of memory needed by the workaround buffer, we
926 * set its pitch to 128 bytes (the width of a Y tile). This means that
927 * the amount of memory needed for the workaround buffer is
928 * (width_in_tiles + height_in_tiles - 1) tiles.
930 * Note that since the workaround buffer will be interpreted by the
931 * hardware as an interleaved multisampled buffer, we need to compute
932 * width_in_tiles and height_in_tiles by dividing the width and height
933 * by 16 rather than the normal Y-tile size of 32.
935 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
936 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
937 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
938 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
940 bo
= brw
->wm
.multisampled_null_render_target_bo
;
941 surface_type
= BRW_SURFACE_2D
;
943 multisampling_state
= brw_get_surface_num_multisamples(samples
);
946 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
947 ISL_FORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
949 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
950 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
951 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
952 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
954 surf
[1] = bo
? bo
->offset64
: 0;
955 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
956 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
958 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
961 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
963 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
964 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
965 surf
[4] = multisampling_state
;
969 brw_emit_reloc(&brw
->batch
, *out_offset
+ 4, bo
, 0,
970 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
975 * Sets up a surface state structure to point at the given region.
976 * While it is only used for the front/back buffer currently, it should be
977 * usable for further buffers when doing ARB_draw_buffer support.
980 gen4_update_renderbuffer_surface(struct brw_context
*brw
,
981 struct gl_renderbuffer
*rb
,
982 uint32_t flags
, unsigned unit
,
985 struct gl_context
*ctx
= &brw
->ctx
;
986 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
987 struct intel_mipmap_tree
*mt
= irb
->mt
;
989 uint32_t tile_x
, tile_y
;
990 enum isl_format format
;
993 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
994 /* BRW_NEW_FS_PROG_DATA */
996 assert(!(flags
& INTEL_RENDERBUFFER_LAYERED
));
997 assert(!(flags
& INTEL_AUX_BUFFER_DISABLED
));
999 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
1000 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
1002 if (tile_x
!= 0 || tile_y
!= 0) {
1003 /* Original gen4 hardware couldn't draw to a non-tile-aligned
1004 * destination in a miptree unless you actually setup your renderbuffer
1005 * as a miptree and used the fragile lod/array_index/etc. controls to
1006 * select the image. So, instead, we just make a new single-level
1007 * miptree and render into that.
1009 intel_renderbuffer_move_to_temp(brw
, irb
, false);
1014 surf
= brw_state_batch(brw
, 6 * 4, 32, &offset
);
1016 format
= brw
->render_target_format
[rb_format
];
1017 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
1018 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
1019 __func__
, _mesa_get_format_name(rb_format
));
1022 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
1023 format
<< BRW_SURFACE_FORMAT_SHIFT
);
1026 assert(mt
->offset
% mt
->cpp
== 0);
1027 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
1028 mt
->bo
->offset64
+ mt
->offset
);
1030 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
1031 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
1033 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
1034 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
1036 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
1038 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
1039 /* Note that the low bits of these fields are missing, so
1040 * there's the possibility of getting in trouble.
1042 assert(tile_x
% 4 == 0);
1043 assert(tile_y
% 2 == 0);
1044 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
1045 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
1046 (mt
->valign
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
1050 if (!ctx
->Color
.ColorLogicOpEnabled
&& !ctx
->Color
._AdvancedBlendMode
&&
1051 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
1052 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
1054 if (!ctx
->Color
.ColorMask
[unit
][0])
1055 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
1056 if (!ctx
->Color
.ColorMask
[unit
][1])
1057 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
1058 if (!ctx
->Color
.ColorMask
[unit
][2])
1059 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
1061 /* As mentioned above, disable writes to the alpha component when the
1062 * renderbuffer is XRGB.
1064 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
1065 !ctx
->Color
.ColorMask
[unit
][3]) {
1066 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
1070 brw_emit_reloc(&brw
->batch
, offset
+ 4, mt
->bo
, surf
[1] - mt
->bo
->offset64
,
1071 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
1077 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1080 brw_update_renderbuffer_surfaces(struct brw_context
*brw
,
1081 const struct gl_framebuffer
*fb
,
1082 uint32_t render_target_start
,
1083 uint32_t *surf_offset
)
1086 const unsigned int w
= _mesa_geometric_width(fb
);
1087 const unsigned int h
= _mesa_geometric_height(fb
);
1088 const unsigned int s
= _mesa_geometric_samples(fb
);
1090 /* Update surfaces for drawing buffers */
1091 if (fb
->_NumColorDrawBuffers
>= 1) {
1092 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1093 const uint32_t surf_index
= render_target_start
+ i
;
1094 const int flags
= (_mesa_geometric_layers(fb
) > 0 ?
1095 INTEL_RENDERBUFFER_LAYERED
: 0) |
1096 (brw
->draw_aux_buffer_disabled
[i
] ?
1097 INTEL_AUX_BUFFER_DISABLED
: 0);
1099 if (intel_renderbuffer(fb
->_ColorDrawBuffers
[i
])) {
1100 surf_offset
[surf_index
] =
1101 brw
->vtbl
.update_renderbuffer_surface(
1102 brw
, fb
->_ColorDrawBuffers
[i
], flags
, i
, surf_index
);
1104 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1105 &surf_offset
[surf_index
]);
1109 const uint32_t surf_index
= render_target_start
;
1110 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1111 &surf_offset
[surf_index
]);
1116 update_renderbuffer_surfaces(struct brw_context
*brw
)
1118 const struct gl_context
*ctx
= &brw
->ctx
;
1120 /* BRW_NEW_FS_PROG_DATA */
1121 const struct brw_wm_prog_data
*wm_prog_data
=
1122 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1124 /* _NEW_BUFFERS | _NEW_COLOR */
1125 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1126 brw_update_renderbuffer_surfaces(
1128 wm_prog_data
->binding_table
.render_target_start
,
1129 brw
->wm
.base
.surf_offset
);
1130 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1133 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
1135 .mesa
= _NEW_BUFFERS
|
1137 .brw
= BRW_NEW_BATCH
|
1139 BRW_NEW_FS_PROG_DATA
,
1141 .emit
= update_renderbuffer_surfaces
,
1144 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
1146 .mesa
= _NEW_BUFFERS
,
1147 .brw
= BRW_NEW_BATCH
|
1150 .emit
= update_renderbuffer_surfaces
,
1154 update_renderbuffer_read_surfaces(struct brw_context
*brw
)
1156 const struct gl_context
*ctx
= &brw
->ctx
;
1158 /* BRW_NEW_FS_PROG_DATA */
1159 const struct brw_wm_prog_data
*wm_prog_data
=
1160 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1162 /* BRW_NEW_FRAGMENT_PROGRAM */
1163 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
1164 brw
->fragment_program
&& brw
->fragment_program
->info
.outputs_read
) {
1166 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1168 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1169 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[i
];
1170 const struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1171 const unsigned surf_index
=
1172 wm_prog_data
->binding_table
.render_target_read_start
+ i
;
1173 uint32_t *surf_offset
= &brw
->wm
.base
.surf_offset
[surf_index
];
1176 const enum isl_format format
= brw
->render_target_format
[
1177 _mesa_get_render_format(ctx
, intel_rb_format(irb
))];
1178 assert(isl_format_supports_sampling(&brw
->screen
->devinfo
,
1181 /* Override the target of the texture if the render buffer is a
1182 * single slice of a 3D texture (since the minimum array element
1183 * field of the surface state structure is ignored by the sampler
1184 * unit for 3D textures on some hardware), or if the render buffer
1185 * is a 1D array (since shaders always provide the array index
1186 * coordinate at the Z component to avoid state-dependent
1187 * recompiles when changing the texture target of the
1190 const GLenum target
=
1191 (irb
->mt
->target
== GL_TEXTURE_3D
&&
1192 irb
->layer_count
== 1) ? GL_TEXTURE_2D
:
1193 irb
->mt
->target
== GL_TEXTURE_1D_ARRAY
? GL_TEXTURE_2D_ARRAY
:
1196 /* intel_renderbuffer::mt_layer is expressed in sample units for
1197 * the UMS and CMS multisample layouts, but
1198 * intel_renderbuffer::layer_count is expressed in units of whole
1199 * logical layers regardless of the multisample layout.
1201 const unsigned mt_layer_unit
=
1202 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
1203 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
1204 MAX2(irb
->mt
->num_samples
, 1) : 1;
1206 const struct isl_view view
= {
1208 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
1210 .base_array_layer
= irb
->mt_layer
/ mt_layer_unit
,
1211 .array_len
= irb
->layer_count
,
1212 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1213 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
1216 const int flags
= brw
->draw_aux_buffer_disabled
[i
] ?
1217 INTEL_AUX_BUFFER_DISABLED
: 0;
1218 brw_emit_surface_state(brw
, irb
->mt
, flags
, target
, view
,
1220 surf_offset
, surf_index
,
1221 I915_GEM_DOMAIN_SAMPLER
, 0);
1224 brw
->vtbl
.emit_null_surface_state(
1225 brw
, _mesa_geometric_width(fb
), _mesa_geometric_height(fb
),
1226 _mesa_geometric_samples(fb
), surf_offset
);
1230 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1234 const struct brw_tracked_state brw_renderbuffer_read_surfaces
= {
1236 .mesa
= _NEW_BUFFERS
,
1237 .brw
= BRW_NEW_BATCH
|
1238 BRW_NEW_FRAGMENT_PROGRAM
|
1239 BRW_NEW_FS_PROG_DATA
,
1241 .emit
= update_renderbuffer_read_surfaces
,
1245 update_stage_texture_surfaces(struct brw_context
*brw
,
1246 const struct gl_program
*prog
,
1247 struct brw_stage_state
*stage_state
,
1248 bool for_gather
, uint32_t plane
)
1253 struct gl_context
*ctx
= &brw
->ctx
;
1255 uint32_t *surf_offset
= stage_state
->surf_offset
;
1257 /* BRW_NEW_*_PROG_DATA */
1259 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
1261 surf_offset
+= stage_state
->prog_data
->binding_table
.plane_start
[plane
];
1263 unsigned num_samplers
= util_last_bit(prog
->SamplersUsed
);
1264 for (unsigned s
= 0; s
< num_samplers
; s
++) {
1267 if (prog
->SamplersUsed
& (1 << s
)) {
1268 const unsigned unit
= prog
->SamplerUnits
[s
];
1271 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1272 brw_update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
, plane
);
1280 * Construct SURFACE_STATE objects for enabled textures.
1283 brw_update_texture_surfaces(struct brw_context
*brw
)
1285 /* BRW_NEW_VERTEX_PROGRAM */
1286 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
1288 /* BRW_NEW_TESS_PROGRAMS */
1289 struct gl_program
*tcs
= (struct gl_program
*) brw
->tess_ctrl_program
;
1290 struct gl_program
*tes
= (struct gl_program
*) brw
->tess_eval_program
;
1292 /* BRW_NEW_GEOMETRY_PROGRAM */
1293 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
1295 /* BRW_NEW_FRAGMENT_PROGRAM */
1296 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
1299 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false, 0);
1300 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, false, 0);
1301 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, false, 0);
1302 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false, 0);
1303 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 0);
1305 /* emit alternate set of surface state for gather. this
1306 * allows the surface format to be overriden for only the
1307 * gather4 messages. */
1309 if (vs
&& vs
->nir
->info
.uses_texture_gather
)
1310 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true, 0);
1311 if (tcs
&& tcs
->nir
->info
.uses_texture_gather
)
1312 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, true, 0);
1313 if (tes
&& tes
->nir
->info
.uses_texture_gather
)
1314 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, true, 0);
1315 if (gs
&& gs
->nir
->info
.uses_texture_gather
)
1316 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true, 0);
1317 if (fs
&& fs
->nir
->info
.uses_texture_gather
)
1318 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true, 0);
1322 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 1);
1323 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 2);
1326 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1329 const struct brw_tracked_state brw_texture_surfaces
= {
1331 .mesa
= _NEW_TEXTURE
,
1332 .brw
= BRW_NEW_BATCH
|
1334 BRW_NEW_FRAGMENT_PROGRAM
|
1335 BRW_NEW_FS_PROG_DATA
|
1336 BRW_NEW_GEOMETRY_PROGRAM
|
1337 BRW_NEW_GS_PROG_DATA
|
1338 BRW_NEW_TESS_PROGRAMS
|
1339 BRW_NEW_TCS_PROG_DATA
|
1340 BRW_NEW_TES_PROG_DATA
|
1341 BRW_NEW_TEXTURE_BUFFER
|
1342 BRW_NEW_VERTEX_PROGRAM
|
1343 BRW_NEW_VS_PROG_DATA
,
1345 .emit
= brw_update_texture_surfaces
,
1349 brw_update_cs_texture_surfaces(struct brw_context
*brw
)
1351 /* BRW_NEW_COMPUTE_PROGRAM */
1352 struct gl_program
*cs
= (struct gl_program
*) brw
->compute_program
;
1355 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, false, 0);
1357 /* emit alternate set of surface state for gather. this
1358 * allows the surface format to be overriden for only the
1362 if (cs
&& cs
->nir
->info
.uses_texture_gather
)
1363 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, true, 0);
1366 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1369 const struct brw_tracked_state brw_cs_texture_surfaces
= {
1371 .mesa
= _NEW_TEXTURE
,
1372 .brw
= BRW_NEW_BATCH
|
1374 BRW_NEW_COMPUTE_PROGRAM
,
1376 .emit
= brw_update_cs_texture_surfaces
,
1381 brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1382 struct brw_stage_state
*stage_state
,
1383 struct brw_stage_prog_data
*prog_data
)
1385 struct gl_context
*ctx
= &brw
->ctx
;
1390 uint32_t *ubo_surf_offsets
=
1391 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
1393 for (int i
= 0; i
< prog
->info
.num_ubos
; i
++) {
1394 struct gl_uniform_buffer_binding
*binding
=
1395 &ctx
->UniformBufferBindings
[prog
->sh
.UniformBlocks
[i
]->Binding
];
1397 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1398 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ubo_surf_offsets
[i
]);
1400 struct intel_buffer_object
*intel_bo
=
1401 intel_buffer_object(binding
->BufferObject
);
1402 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1403 if (!binding
->AutomaticSize
)
1404 size
= MIN2(size
, binding
->Size
);
1406 intel_bufferobj_buffer(brw
, intel_bo
,
1409 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
1411 &ubo_surf_offsets
[i
]);
1415 uint32_t *ssbo_surf_offsets
=
1416 &stage_state
->surf_offset
[prog_data
->binding_table
.ssbo_start
];
1418 for (int i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
1419 struct gl_shader_storage_buffer_binding
*binding
=
1420 &ctx
->ShaderStorageBufferBindings
[prog
->sh
.ShaderStorageBlocks
[i
]->Binding
];
1422 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1423 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ssbo_surf_offsets
[i
]);
1425 struct intel_buffer_object
*intel_bo
=
1426 intel_buffer_object(binding
->BufferObject
);
1427 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1428 if (!binding
->AutomaticSize
)
1429 size
= MIN2(size
, binding
->Size
);
1431 intel_bufferobj_buffer(brw
, intel_bo
,
1434 brw_create_buffer_surface(brw
, bo
, binding
->Offset
,
1436 &ssbo_surf_offsets
[i
]);
1440 if (prog
->info
.num_ubos
|| prog
->info
.num_ssbos
)
1441 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1445 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
1447 struct gl_context
*ctx
= &brw
->ctx
;
1449 struct gl_program
*prog
= ctx
->FragmentProgram
._Current
;
1451 /* BRW_NEW_FS_PROG_DATA */
1452 brw_upload_ubo_surfaces(brw
, prog
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1455 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
1457 .mesa
= _NEW_PROGRAM
,
1458 .brw
= BRW_NEW_BATCH
|
1460 BRW_NEW_FS_PROG_DATA
|
1461 BRW_NEW_UNIFORM_BUFFER
,
1463 .emit
= brw_upload_wm_ubo_surfaces
,
1467 brw_upload_cs_ubo_surfaces(struct brw_context
*brw
)
1469 struct gl_context
*ctx
= &brw
->ctx
;
1471 struct gl_program
*prog
=
1472 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1474 /* BRW_NEW_CS_PROG_DATA */
1475 brw_upload_ubo_surfaces(brw
, prog
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1478 const struct brw_tracked_state brw_cs_ubo_surfaces
= {
1480 .mesa
= _NEW_PROGRAM
,
1481 .brw
= BRW_NEW_BATCH
|
1483 BRW_NEW_CS_PROG_DATA
|
1484 BRW_NEW_UNIFORM_BUFFER
,
1486 .emit
= brw_upload_cs_ubo_surfaces
,
1490 brw_upload_abo_surfaces(struct brw_context
*brw
,
1491 const struct gl_program
*prog
,
1492 struct brw_stage_state
*stage_state
,
1493 struct brw_stage_prog_data
*prog_data
)
1495 struct gl_context
*ctx
= &brw
->ctx
;
1496 uint32_t *surf_offsets
=
1497 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
1499 if (prog
->info
.num_abos
) {
1500 for (unsigned i
= 0; i
< prog
->info
.num_abos
; i
++) {
1501 struct gl_atomic_buffer_binding
*binding
=
1502 &ctx
->AtomicBufferBindings
[prog
->sh
.AtomicBuffers
[i
]->Binding
];
1503 struct intel_buffer_object
*intel_bo
=
1504 intel_buffer_object(binding
->BufferObject
);
1505 struct brw_bo
*bo
= intel_bufferobj_buffer(
1506 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
1508 brw_emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
1509 binding
->Offset
, ISL_FORMAT_RAW
,
1510 bo
->size
- binding
->Offset
, 1, true);
1513 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1518 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
1521 const struct gl_program
*wm
= brw
->fragment_program
;
1524 /* BRW_NEW_FS_PROG_DATA */
1525 brw_upload_abo_surfaces(brw
, wm
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1529 const struct brw_tracked_state brw_wm_abo_surfaces
= {
1531 .mesa
= _NEW_PROGRAM
,
1532 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1535 BRW_NEW_FS_PROG_DATA
,
1537 .emit
= brw_upload_wm_abo_surfaces
,
1541 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1544 const struct gl_program
*cp
= brw
->compute_program
;
1547 /* BRW_NEW_CS_PROG_DATA */
1548 brw_upload_abo_surfaces(brw
, cp
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1552 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1554 .mesa
= _NEW_PROGRAM
,
1555 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1558 BRW_NEW_CS_PROG_DATA
,
1560 .emit
= brw_upload_cs_abo_surfaces
,
1564 brw_upload_cs_image_surfaces(struct brw_context
*brw
)
1567 const struct gl_program
*cp
= brw
->compute_program
;
1570 /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1571 brw_upload_image_surfaces(brw
, cp
, &brw
->cs
.base
,
1572 brw
->cs
.base
.prog_data
);
1576 const struct brw_tracked_state brw_cs_image_surfaces
= {
1578 .mesa
= _NEW_TEXTURE
| _NEW_PROGRAM
,
1579 .brw
= BRW_NEW_BATCH
|
1581 BRW_NEW_CS_PROG_DATA
|
1584 .emit
= brw_upload_cs_image_surfaces
,
1588 get_image_format(struct brw_context
*brw
, mesa_format format
, GLenum access
)
1590 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1591 enum isl_format hw_format
= brw_isl_format_for_mesa_format(format
);
1592 if (access
== GL_WRITE_ONLY
) {
1594 } else if (isl_has_matching_typed_storage_image_format(devinfo
, hw_format
)) {
1595 /* Typed surface reads support a very limited subset of the shader
1596 * image formats. Translate it into the closest format the
1597 * hardware supports.
1599 return isl_lower_storage_image_format(devinfo
, hw_format
);
1601 /* The hardware doesn't actually support a typed format that we can use
1602 * so we have to fall back to untyped read/write messages.
1604 return ISL_FORMAT_RAW
;
1609 update_default_image_param(struct brw_context
*brw
,
1610 struct gl_image_unit
*u
,
1611 unsigned surface_idx
,
1612 struct brw_image_param
*param
)
1614 memset(param
, 0, sizeof(*param
));
1615 param
->surface_idx
= surface_idx
;
1616 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1617 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1618 * detailed explanation of these parameters.
1620 param
->swizzling
[0] = 0xff;
1621 param
->swizzling
[1] = 0xff;
1625 update_buffer_image_param(struct brw_context
*brw
,
1626 struct gl_image_unit
*u
,
1627 unsigned surface_idx
,
1628 struct brw_image_param
*param
)
1630 struct gl_buffer_object
*obj
= u
->TexObj
->BufferObject
;
1631 const uint32_t size
= MIN2((uint32_t)u
->TexObj
->BufferSize
, obj
->Size
);
1632 update_default_image_param(brw
, u
, surface_idx
, param
);
1634 param
->size
[0] = size
/ _mesa_get_format_bytes(u
->_ActualFormat
);
1635 param
->stride
[0] = _mesa_get_format_bytes(u
->_ActualFormat
);
1639 update_texture_image_param(struct brw_context
*brw
,
1640 struct gl_image_unit
*u
,
1641 unsigned surface_idx
,
1642 struct brw_image_param
*param
)
1644 struct intel_mipmap_tree
*mt
= intel_texture_object(u
->TexObj
)->mt
;
1646 update_default_image_param(brw
, u
, surface_idx
, param
);
1648 param
->size
[0] = minify(mt
->logical_width0
, u
->Level
);
1649 param
->size
[1] = minify(mt
->logical_height0
, u
->Level
);
1650 param
->size
[2] = (!u
->Layered
? 1 :
1651 u
->TexObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1652 u
->TexObj
->Target
== GL_TEXTURE_3D
?
1653 minify(mt
->logical_depth0
, u
->Level
) :
1654 mt
->logical_depth0
);
1656 intel_miptree_get_image_offset(mt
, u
->Level
, u
->_Layer
,
1660 param
->stride
[0] = mt
->cpp
;
1661 param
->stride
[1] = mt
->pitch
/ mt
->cpp
;
1663 brw_miptree_get_horizontal_slice_pitch(brw
, mt
, u
->Level
);
1665 brw_miptree_get_vertical_slice_pitch(brw
, mt
, u
->Level
);
1667 if (mt
->tiling
== I915_TILING_X
) {
1668 /* An X tile is a rectangular block of 512x8 bytes. */
1669 param
->tiling
[0] = _mesa_logbase2(512 / mt
->cpp
);
1670 param
->tiling
[1] = _mesa_logbase2(8);
1672 if (brw
->has_swizzling
) {
1673 /* Right shifts required to swizzle bits 9 and 10 of the memory
1674 * address with bit 6.
1676 param
->swizzling
[0] = 3;
1677 param
->swizzling
[1] = 4;
1679 } else if (mt
->tiling
== I915_TILING_Y
) {
1680 /* The layout of a Y-tiled surface in memory isn't really fundamentally
1681 * different to the layout of an X-tiled surface, we simply pretend that
1682 * the surface is broken up in a number of smaller 16Bx32 tiles, each
1683 * one arranged in X-major order just like is the case for X-tiling.
1685 param
->tiling
[0] = _mesa_logbase2(16 / mt
->cpp
);
1686 param
->tiling
[1] = _mesa_logbase2(32);
1688 if (brw
->has_swizzling
) {
1689 /* Right shift required to swizzle bit 9 of the memory address with
1692 param
->swizzling
[0] = 3;
1696 /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
1697 * address calculation algorithm (emit_address_calculation() in
1698 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
1699 * modulus equal to the LOD.
1701 param
->tiling
[2] = (u
->TexObj
->Target
== GL_TEXTURE_3D
? u
->Level
:
1706 update_image_surface(struct brw_context
*brw
,
1707 struct gl_image_unit
*u
,
1709 unsigned surface_idx
,
1710 uint32_t *surf_offset
,
1711 struct brw_image_param
*param
)
1713 if (_mesa_is_image_unit_valid(&brw
->ctx
, u
)) {
1714 struct gl_texture_object
*obj
= u
->TexObj
;
1715 const unsigned format
= get_image_format(brw
, u
->_ActualFormat
, access
);
1717 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
1718 struct intel_buffer_object
*intel_obj
=
1719 intel_buffer_object(obj
->BufferObject
);
1720 const unsigned texel_size
= (format
== ISL_FORMAT_RAW
? 1 :
1721 _mesa_get_format_bytes(u
->_ActualFormat
));
1723 brw_emit_buffer_surface_state(
1724 brw
, surf_offset
, intel_obj
->buffer
, obj
->BufferOffset
,
1725 format
, intel_obj
->Base
.Size
, texel_size
,
1726 access
!= GL_READ_ONLY
);
1728 update_buffer_image_param(brw
, u
, surface_idx
, param
);
1731 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
1732 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
1734 if (format
== ISL_FORMAT_RAW
) {
1735 brw_emit_buffer_surface_state(
1736 brw
, surf_offset
, mt
->bo
, mt
->offset
,
1737 format
, mt
->bo
->size
- mt
->offset
, 1 /* pitch */,
1738 access
!= GL_READ_ONLY
);
1741 const unsigned num_layers
= (!u
->Layered
? 1 :
1742 obj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1743 mt
->logical_depth0
);
1745 struct isl_view view
= {
1747 .base_level
= obj
->MinLevel
+ u
->Level
,
1749 .base_array_layer
= obj
->MinLayer
+ u
->_Layer
,
1750 .array_len
= num_layers
,
1751 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1752 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
1755 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
1756 const bool unresolved
= intel_miptree_has_color_unresolved(
1757 mt
, view
.base_level
, view
.levels
,
1758 view
.base_array_layer
, view
.array_len
);
1759 const int flags
= unresolved
? 0 : INTEL_AUX_BUFFER_DISABLED
;
1760 brw_emit_surface_state(brw
, mt
, flags
, mt
->target
, view
,
1762 surf_offset
, surf_index
,
1763 I915_GEM_DOMAIN_SAMPLER
,
1764 access
== GL_READ_ONLY
? 0 :
1765 I915_GEM_DOMAIN_SAMPLER
);
1768 update_texture_image_param(brw
, u
, surface_idx
, param
);
1772 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, surf_offset
);
1773 update_default_image_param(brw
, u
, surface_idx
, param
);
1778 brw_upload_image_surfaces(struct brw_context
*brw
,
1779 const struct gl_program
*prog
,
1780 struct brw_stage_state
*stage_state
,
1781 struct brw_stage_prog_data
*prog_data
)
1784 struct gl_context
*ctx
= &brw
->ctx
;
1786 if (prog
->info
.num_images
) {
1787 for (unsigned i
= 0; i
< prog
->info
.num_images
; i
++) {
1788 struct gl_image_unit
*u
= &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[i
]];
1789 const unsigned surf_idx
= prog_data
->binding_table
.image_start
+ i
;
1791 update_image_surface(brw
, u
, prog
->sh
.ImageAccess
[i
],
1793 &stage_state
->surf_offset
[surf_idx
],
1794 &prog_data
->image_param
[i
]);
1797 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1798 /* This may have changed the image metadata dependent on the context
1799 * image unit state and passed to the program as uniforms, make sure
1800 * that push and pull constants are reuploaded.
1802 brw
->NewGLState
|= _NEW_PROGRAM_CONSTANTS
;
1807 brw_upload_wm_image_surfaces(struct brw_context
*brw
)
1809 /* BRW_NEW_FRAGMENT_PROGRAM */
1810 const struct gl_program
*wm
= brw
->fragment_program
;
1813 /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1814 brw_upload_image_surfaces(brw
, wm
, &brw
->wm
.base
,
1815 brw
->wm
.base
.prog_data
);
1819 const struct brw_tracked_state brw_wm_image_surfaces
= {
1821 .mesa
= _NEW_TEXTURE
,
1822 .brw
= BRW_NEW_BATCH
|
1824 BRW_NEW_FRAGMENT_PROGRAM
|
1825 BRW_NEW_FS_PROG_DATA
|
1828 .emit
= brw_upload_wm_image_surfaces
,
1832 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
1834 brw
->vtbl
.update_renderbuffer_surface
= gen4_update_renderbuffer_surface
;
1835 brw
->vtbl
.emit_null_surface_state
= brw_emit_null_surface_state
;
1839 gen6_init_vtable_surface_functions(struct brw_context
*brw
)
1841 gen4_init_vtable_surface_functions(brw
);
1842 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
1846 brw_upload_cs_work_groups_surface(struct brw_context
*brw
)
1848 struct gl_context
*ctx
= &brw
->ctx
;
1850 struct gl_program
*prog
=
1851 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1852 /* BRW_NEW_CS_PROG_DATA */
1853 const struct brw_cs_prog_data
*cs_prog_data
=
1854 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
1856 if (prog
&& cs_prog_data
->uses_num_work_groups
) {
1857 const unsigned surf_idx
=
1858 cs_prog_data
->binding_table
.work_groups_start
;
1859 uint32_t *surf_offset
= &brw
->cs
.base
.surf_offset
[surf_idx
];
1863 if (brw
->compute
.num_work_groups_bo
== NULL
) {
1865 intel_upload_data(brw
,
1866 (void *)brw
->compute
.num_work_groups
,
1872 bo
= brw
->compute
.num_work_groups_bo
;
1873 bo_offset
= brw
->compute
.num_work_groups_offset
;
1876 brw_emit_buffer_surface_state(brw
, surf_offset
,
1879 3 * sizeof(GLuint
), 1, true);
1880 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1884 const struct brw_tracked_state brw_cs_work_groups_surface
= {
1886 .brw
= BRW_NEW_BLORP
|
1887 BRW_NEW_CS_PROG_DATA
|
1888 BRW_NEW_CS_WORK_GROUPS
1890 .emit
= brw_upload_cs_work_groups_surface
,