2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "compiler/nir/nir.h"
34 #include "main/context.h"
35 #include "main/blend.h"
36 #include "main/mtypes.h"
37 #include "main/samplerobj.h"
38 #include "main/shaderimage.h"
39 #include "main/teximage.h"
40 #include "program/prog_parameter.h"
41 #include "program/prog_instruction.h"
42 #include "main/framebuffer.h"
43 #include "main/shaderapi.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_batchbuffer.h"
49 #include "intel_tex.h"
50 #include "intel_fbo.h"
51 #include "intel_buffer_objects.h"
53 #include "brw_context.h"
54 #include "brw_state.h"
55 #include "brw_defines.h"
59 INTEL_RENDERBUFFER_LAYERED
= 1 << 0,
60 INTEL_AUX_BUFFER_DISABLED
= 1 << 1,
63 uint32_t tex_mocs
[] = {
70 uint32_t rb_mocs
[] = {
78 get_isl_surf(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
79 GLenum target
, struct isl_view
*view
,
80 uint32_t *tile_x
, uint32_t *tile_y
,
81 uint32_t *offset
, struct isl_surf
*surf
)
85 const enum isl_dim_layout dim_layout
=
86 get_isl_dim_layout(&brw
->screen
->devinfo
, mt
->surf
.tiling
, target
);
88 if (surf
->dim_layout
== dim_layout
)
91 /* The layout of the specified texture target is not compatible with the
92 * actual layout of the miptree structure in memory -- You're entering
93 * dangerous territory, this can only possibly work if you only intended
94 * to access a single level and slice of the texture, and the hardware
95 * supports the tile offset feature in order to allow non-tile-aligned
96 * base offsets, since we'll have to point the hardware to the first
97 * texel of the level instead of relying on the usual base level/layer
100 assert(brw
->has_surface_tile_offset
);
101 assert(view
->levels
== 1 && view
->array_len
== 1);
102 assert(*tile_x
== 0 && *tile_y
== 0);
104 *offset
+= intel_miptree_get_tile_offsets(mt
, view
->base_level
,
105 view
->base_array_layer
,
108 /* Minify the logical dimensions of the texture. */
109 const unsigned l
= view
->base_level
- mt
->first_level
;
110 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
111 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
112 minify(surf
->logical_level0_px
.height
, l
);
113 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
114 minify(surf
->logical_level0_px
.depth
, l
);
116 /* Only the base level and layer can be addressed with the overridden
119 surf
->logical_level0_px
.array_len
= 1;
121 surf
->dim_layout
= dim_layout
;
123 /* The requested slice of the texture is now at the base level and
126 view
->base_level
= 0;
127 view
->base_array_layer
= 0;
131 brw_emit_surface_state(struct brw_context
*brw
,
132 struct intel_mipmap_tree
*mt
,
133 GLenum target
, struct isl_view view
,
134 enum isl_aux_usage aux_usage
,
135 uint32_t mocs
, uint32_t *surf_offset
, int surf_index
,
136 unsigned read_domains
, unsigned write_domains
)
138 uint32_t tile_x
= mt
->level
[0].level_x
;
139 uint32_t tile_y
= mt
->level
[0].level_y
;
140 uint32_t offset
= mt
->offset
;
142 struct isl_surf surf
;
144 get_isl_surf(brw
, mt
, target
, &view
, &tile_x
, &tile_y
, &offset
, &surf
);
146 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
148 struct brw_bo
*aux_bo
;
149 struct isl_surf
*aux_surf
= NULL
;
150 uint64_t aux_offset
= 0;
152 case ISL_AUX_USAGE_MCS
:
153 case ISL_AUX_USAGE_CCS_D
:
154 case ISL_AUX_USAGE_CCS_E
:
155 aux_surf
= &mt
->mcs_buf
->surf
;
156 aux_bo
= mt
->mcs_buf
->bo
;
157 aux_offset
= mt
->mcs_buf
->offset
;
160 case ISL_AUX_USAGE_HIZ
:
161 aux_surf
= &mt
->hiz_buf
->surf
;
162 aux_bo
= mt
->hiz_buf
->bo
;
166 case ISL_AUX_USAGE_NONE
:
170 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
171 /* We only really need a clear color if we also have an auxiliary
172 * surface. Without one, it does nothing.
174 clear_color
= mt
->fast_clear_color
;
177 void *state
= brw_state_batch(brw
,
178 brw
->isl_dev
.ss
.size
,
179 brw
->isl_dev
.ss
.align
,
182 isl_surf_fill_state(&brw
->isl_dev
, state
, .surf
= &mt
->surf
, .view
= &view
,
183 .address
= brw_emit_reloc(&brw
->batch
,
184 *surf_offset
+ brw
->isl_dev
.ss
.addr_offset
,
185 mt
->bo
, offset
, read_domains
, write_domains
),
186 .aux_surf
= aux_surf
, .aux_usage
= aux_usage
,
187 .aux_address
= aux_offset
,
188 .mocs
= mocs
, .clear_color
= clear_color
,
189 .x_offset_sa
= tile_x
, .y_offset_sa
= tile_y
);
191 /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
192 * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
193 * contain other control information. Since buffer addresses are always
194 * on 4k boundaries (and thus have their lower 12 bits zero), we can use
195 * an ordinary reloc to do the necessary address translation.
197 * FIXME: move to the point of assignment.
199 assert((aux_offset
& 0xfff) == 0);
200 uint32_t *aux_addr
= state
+ brw
->isl_dev
.ss
.aux_addr_offset
;
201 *aux_addr
= brw_emit_reloc(&brw
->batch
,
203 brw
->isl_dev
.ss
.aux_addr_offset
,
205 read_domains
, write_domains
);
210 brw_update_renderbuffer_surface(struct brw_context
*brw
,
211 struct gl_renderbuffer
*rb
,
212 uint32_t flags
, unsigned unit
,
215 struct gl_context
*ctx
= &brw
->ctx
;
216 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
217 struct intel_mipmap_tree
*mt
= irb
->mt
;
219 enum isl_aux_usage aux_usage
=
220 intel_miptree_render_aux_usage(brw
, mt
, ctx
->Color
.sRGBEnabled
,
221 ctx
->Color
.BlendEnabled
& (1 << unit
));
223 if (flags
& INTEL_AUX_BUFFER_DISABLED
) {
224 assert(brw
->gen
>= 9);
225 aux_usage
= ISL_AUX_USAGE_NONE
;
228 assert(brw_render_target_supported(brw
, rb
));
230 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
231 if (unlikely(!brw
->mesa_format_supports_render
[rb_format
])) {
232 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
233 __func__
, _mesa_get_format_name(rb_format
));
236 struct isl_view view
= {
237 .format
= brw
->mesa_to_isl_render_format
[rb_format
],
238 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
240 .base_array_layer
= irb
->mt_layer
,
241 .array_len
= MAX2(irb
->layer_count
, 1),
242 .swizzle
= ISL_SWIZZLE_IDENTITY
,
243 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
247 brw_emit_surface_state(brw
, mt
, mt
->target
, view
, aux_usage
,
250 I915_GEM_DOMAIN_RENDER
,
251 I915_GEM_DOMAIN_RENDER
);
256 translate_tex_target(GLenum target
)
260 case GL_TEXTURE_1D_ARRAY_EXT
:
261 return BRW_SURFACE_1D
;
263 case GL_TEXTURE_RECTANGLE_NV
:
264 return BRW_SURFACE_2D
;
267 case GL_TEXTURE_2D_ARRAY_EXT
:
268 case GL_TEXTURE_EXTERNAL_OES
:
269 case GL_TEXTURE_2D_MULTISAMPLE
:
270 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
271 return BRW_SURFACE_2D
;
274 return BRW_SURFACE_3D
;
276 case GL_TEXTURE_CUBE_MAP
:
277 case GL_TEXTURE_CUBE_MAP_ARRAY
:
278 return BRW_SURFACE_CUBE
;
281 unreachable("not reached");
286 brw_get_surface_tiling_bits(enum isl_tiling tiling
)
290 return BRW_SURFACE_TILED
;
292 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
300 brw_get_surface_num_multisamples(unsigned num_samples
)
303 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
305 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
309 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
313 brw_get_texture_swizzle(const struct gl_context
*ctx
,
314 const struct gl_texture_object
*t
)
316 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
318 int swizzles
[SWIZZLE_NIL
+ 1] = {
328 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
329 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
330 GLenum depth_mode
= t
->DepthMode
;
332 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
333 * with depth component data specified with a sized internal format.
334 * Otherwise, it's left at the old default, GL_LUMINANCE.
336 if (_mesa_is_gles3(ctx
) &&
337 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
338 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
342 switch (depth_mode
) {
344 swizzles
[0] = SWIZZLE_ZERO
;
345 swizzles
[1] = SWIZZLE_ZERO
;
346 swizzles
[2] = SWIZZLE_ZERO
;
347 swizzles
[3] = SWIZZLE_X
;
350 swizzles
[0] = SWIZZLE_X
;
351 swizzles
[1] = SWIZZLE_X
;
352 swizzles
[2] = SWIZZLE_X
;
353 swizzles
[3] = SWIZZLE_ONE
;
356 swizzles
[0] = SWIZZLE_X
;
357 swizzles
[1] = SWIZZLE_X
;
358 swizzles
[2] = SWIZZLE_X
;
359 swizzles
[3] = SWIZZLE_X
;
362 swizzles
[0] = SWIZZLE_X
;
363 swizzles
[1] = SWIZZLE_ZERO
;
364 swizzles
[2] = SWIZZLE_ZERO
;
365 swizzles
[3] = SWIZZLE_ONE
;
370 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
372 /* If the texture's format is alpha-only, force R, G, and B to
373 * 0.0. Similarly, if the texture's format has no alpha channel,
374 * force the alpha value read to 1.0. This allows for the
375 * implementation to use an RGBA texture for any of these formats
376 * without leaking any unexpected values.
378 switch (img
->_BaseFormat
) {
380 swizzles
[0] = SWIZZLE_ZERO
;
381 swizzles
[1] = SWIZZLE_ZERO
;
382 swizzles
[2] = SWIZZLE_ZERO
;
385 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
386 swizzles
[0] = SWIZZLE_X
;
387 swizzles
[1] = SWIZZLE_X
;
388 swizzles
[2] = SWIZZLE_X
;
389 swizzles
[3] = SWIZZLE_ONE
;
392 case GL_LUMINANCE_ALPHA
:
393 if (datatype
== GL_SIGNED_NORMALIZED
) {
394 swizzles
[0] = SWIZZLE_X
;
395 swizzles
[1] = SWIZZLE_X
;
396 swizzles
[2] = SWIZZLE_X
;
397 swizzles
[3] = SWIZZLE_W
;
401 if (datatype
== GL_SIGNED_NORMALIZED
) {
402 swizzles
[0] = SWIZZLE_X
;
403 swizzles
[1] = SWIZZLE_X
;
404 swizzles
[2] = SWIZZLE_X
;
405 swizzles
[3] = SWIZZLE_X
;
411 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0 ||
412 img
->TexFormat
== MESA_FORMAT_RGB_DXT1
||
413 img
->TexFormat
== MESA_FORMAT_SRGB_DXT1
)
414 swizzles
[3] = SWIZZLE_ONE
;
418 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
419 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
420 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
421 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
425 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
426 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
428 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
431 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
433 * which is simply adding 4 then modding by 8 (or anding with 7).
435 * We then may need to apply workarounds for textureGather hardware bugs.
438 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
440 unsigned scs
= (swizzle
+ 4) & 7;
442 return (need_green_to_blue
&& scs
== HSW_SCS_GREEN
) ? HSW_SCS_BLUE
: scs
;
446 brw_aux_surface_disabled(const struct brw_context
*brw
,
447 const struct intel_mipmap_tree
*mt
)
449 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
451 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
452 const struct intel_renderbuffer
*irb
=
453 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
455 if (irb
&& irb
->mt
== mt
)
456 return brw
->draw_aux_buffer_disabled
[i
];
463 brw_update_texture_surface(struct gl_context
*ctx
,
465 uint32_t *surf_offset
,
469 struct brw_context
*brw
= brw_context(ctx
);
470 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
472 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
473 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
476 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
477 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
480 if (mt
->plane
[plane
- 1] == NULL
)
482 mt
= mt
->plane
[plane
- 1];
485 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
486 /* If this is a view with restricted NumLayers, then our effective depth
487 * is not just the miptree depth.
489 unsigned view_num_layers
;
490 if (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
) {
491 view_num_layers
= obj
->NumLayers
;
493 view_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
494 mt
->surf
.logical_level0_px
.depth
:
495 mt
->surf
.logical_level0_px
.array_len
;
498 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
499 * texturing functions that return a float, as our code generation always
500 * selects the .x channel (which would always be 0).
502 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
503 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
504 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
505 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
506 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
507 brw_get_texture_swizzle(&brw
->ctx
, obj
));
509 mesa_format mesa_fmt
= plane
== 0 ? intel_obj
->_Format
: mt
->format
;
510 enum isl_format format
= translate_tex_format(brw
, mesa_fmt
,
511 sampler
->sRGBDecode
);
513 /* Implement gen6 and gen7 gather work-around */
514 bool need_green_to_blue
= false;
516 if (brw
->gen
== 7 && (format
== ISL_FORMAT_R32G32_FLOAT
||
517 format
== ISL_FORMAT_R32G32_SINT
||
518 format
== ISL_FORMAT_R32G32_UINT
)) {
519 format
= ISL_FORMAT_R32G32_FLOAT_LD
;
520 need_green_to_blue
= brw
->is_haswell
;
521 } else if (brw
->gen
== 6) {
522 /* Sandybridge's gather4 message is broken for integer formats.
523 * To work around this, we pretend the surface is UNORM for
524 * 8 or 16-bit formats, and emit shader instructions to recover
525 * the real INT/UINT value. For 32-bit formats, we pretend
526 * the surface is FLOAT, and simply reinterpret the resulting
530 case ISL_FORMAT_R8_SINT
:
531 case ISL_FORMAT_R8_UINT
:
532 format
= ISL_FORMAT_R8_UNORM
;
535 case ISL_FORMAT_R16_SINT
:
536 case ISL_FORMAT_R16_UINT
:
537 format
= ISL_FORMAT_R16_UNORM
;
540 case ISL_FORMAT_R32_SINT
:
541 case ISL_FORMAT_R32_UINT
:
542 format
= ISL_FORMAT_R32_FLOAT
;
551 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
553 assert(mt
->r8stencil_mt
&& !mt
->stencil_mt
->r8stencil_needs_update
);
554 mt
= mt
->r8stencil_mt
;
558 format
= ISL_FORMAT_R8_UINT
;
559 } else if (brw
->gen
<= 7 && mt
->format
== MESA_FORMAT_S_UINT8
) {
560 assert(mt
->r8stencil_mt
&& !mt
->r8stencil_needs_update
);
561 mt
= mt
->r8stencil_mt
;
562 format
= ISL_FORMAT_R8_UINT
;
565 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
567 struct isl_view view
= {
569 .base_level
= obj
->MinLevel
+ obj
->BaseLevel
,
570 .levels
= intel_obj
->_MaxLevel
- obj
->BaseLevel
+ 1,
571 .base_array_layer
= obj
->MinLayer
,
572 .array_len
= view_num_layers
,
574 .r
= swizzle_to_scs(GET_SWZ(swizzle
, 0), need_green_to_blue
),
575 .g
= swizzle_to_scs(GET_SWZ(swizzle
, 1), need_green_to_blue
),
576 .b
= swizzle_to_scs(GET_SWZ(swizzle
, 2), need_green_to_blue
),
577 .a
= swizzle_to_scs(GET_SWZ(swizzle
, 3), need_green_to_blue
),
579 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
582 if (obj
->Target
== GL_TEXTURE_CUBE_MAP
||
583 obj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
584 view
.usage
|= ISL_SURF_USAGE_CUBE_BIT
;
586 enum isl_aux_usage aux_usage
=
587 intel_miptree_texture_aux_usage(brw
, mt
, format
);
589 if (brw_aux_surface_disabled(brw
, mt
))
590 aux_usage
= ISL_AUX_USAGE_NONE
;
592 brw_emit_surface_state(brw
, mt
, mt
->target
, view
, aux_usage
,
594 surf_offset
, surf_index
,
595 I915_GEM_DOMAIN_SAMPLER
, 0);
600 brw_emit_buffer_surface_state(struct brw_context
*brw
,
601 uint32_t *out_offset
,
603 unsigned buffer_offset
,
604 unsigned surface_format
,
605 unsigned buffer_size
,
609 uint32_t *dw
= brw_state_batch(brw
,
610 brw
->isl_dev
.ss
.size
,
611 brw
->isl_dev
.ss
.align
,
614 isl_buffer_fill_state(&brw
->isl_dev
, dw
,
615 .address
= !bo
? buffer_offset
:
616 brw_emit_reloc(&brw
->batch
,
617 *out_offset
+ brw
->isl_dev
.ss
.addr_offset
,
619 I915_GEM_DOMAIN_SAMPLER
,
620 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0)),
622 .format
= surface_format
,
624 .mocs
= tex_mocs
[brw
->gen
]);
628 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
630 uint32_t *surf_offset
)
632 struct brw_context
*brw
= brw_context(ctx
);
633 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
634 struct intel_buffer_object
*intel_obj
=
635 intel_buffer_object(tObj
->BufferObject
);
636 uint32_t size
= tObj
->BufferSize
;
637 struct brw_bo
*bo
= NULL
;
638 mesa_format format
= tObj
->_BufferObjectFormat
;
639 const enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
640 int texel_size
= _mesa_get_format_bytes(format
);
643 size
= MIN2(size
, intel_obj
->Base
.Size
);
644 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
,
648 /* The ARB_texture_buffer_specification says:
650 * "The number of texels in the buffer texture's texel array is given by
652 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
654 * where <buffer_size> is the size of the buffer object, in basic
655 * machine units and <components> and <base_type> are the element count
656 * and base data type for elements, as specified in Table X.1. The
657 * number of texels in the texel array is then clamped to the
658 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
660 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
661 * so that when ISL divides by stride to obtain the number of texels, that
662 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
664 size
= MIN2(size
, ctx
->Const
.MaxTextureBufferSize
* (unsigned) texel_size
);
666 if (isl_format
== ISL_FORMAT_UNSUPPORTED
) {
667 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
668 _mesa_get_format_name(format
));
671 brw_emit_buffer_surface_state(brw
, surf_offset
, bo
,
680 * Create the constant buffer surface. Vertex/fragment shader constants will be
681 * read from this buffer with Data Port Read instructions/messages.
684 brw_create_constant_surface(struct brw_context
*brw
,
688 uint32_t *out_offset
)
690 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
691 ISL_FORMAT_R32G32B32A32_FLOAT
,
696 * Create the buffer surface. Shader buffer variables will be
697 * read from / write to this buffer with Data Port Read/Write
698 * instructions/messages.
701 brw_create_buffer_surface(struct brw_context
*brw
,
705 uint32_t *out_offset
)
707 /* Use a raw surface so we can reuse existing untyped read/write/atomic
708 * messages. We need these specifically for the fragment shader since they
709 * include a pixel mask header that we need to ensure correct behavior
710 * with helper invocations, which cannot write to the buffer.
712 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
718 * Set up a binding table entry for use by stream output logic (transform
721 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
724 brw_update_sol_surface(struct brw_context
*brw
,
725 struct gl_buffer_object
*buffer_obj
,
726 uint32_t *out_offset
, unsigned num_vector_components
,
727 unsigned stride_dwords
, unsigned offset_dwords
)
729 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
730 uint32_t offset_bytes
= 4 * offset_dwords
;
731 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
733 buffer_obj
->Size
- offset_bytes
,
735 uint32_t *surf
= brw_state_batch(brw
, 6 * 4, 32, out_offset
);
736 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
737 size_t size_dwords
= buffer_obj
->Size
/ 4;
738 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
740 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
741 * too big to map using a single binding table entry?
743 assert((size_dwords
- offset_dwords
) / stride_dwords
744 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
746 if (size_dwords
> offset_dwords
+ num_vector_components
) {
747 /* There is room for at least 1 transform feedback output in the buffer.
748 * Compute the number of additional transform feedback outputs the
749 * buffer has room for.
751 buffer_size_minus_1
=
752 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
754 /* There isn't even room for a single transform feedback output in the
755 * buffer. We can't configure the binding table entry to prevent output
756 * entirely; we'll have to rely on the geometry shader to detect
757 * overflow. But to minimize the damage in case of a bug, set up the
758 * binding table entry to just allow a single output.
760 buffer_size_minus_1
= 0;
762 width
= buffer_size_minus_1
& 0x7f;
763 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
764 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
766 switch (num_vector_components
) {
768 surface_format
= ISL_FORMAT_R32_FLOAT
;
771 surface_format
= ISL_FORMAT_R32G32_FLOAT
;
774 surface_format
= ISL_FORMAT_R32G32B32_FLOAT
;
777 surface_format
= ISL_FORMAT_R32G32B32A32_FLOAT
;
780 unreachable("Invalid vector size for transform feedback output");
783 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
784 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
785 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
786 BRW_SURFACE_RC_READ_WRITE
;
787 surf
[1] = brw_emit_reloc(&brw
->batch
,
788 *out_offset
+ 4, bo
, offset_bytes
,
789 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
790 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
791 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
792 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
793 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
798 /* Creates a new WM constant buffer reflecting the current fragment program's
799 * constants, if needed by the fragment program.
801 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
805 brw_upload_wm_pull_constants(struct brw_context
*brw
)
807 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
808 /* BRW_NEW_FRAGMENT_PROGRAM */
809 struct brw_program
*fp
= (struct brw_program
*) brw
->fragment_program
;
810 /* BRW_NEW_FS_PROG_DATA */
811 struct brw_stage_prog_data
*prog_data
= brw
->wm
.base
.prog_data
;
813 _mesa_shader_write_subroutine_indices(&brw
->ctx
, MESA_SHADER_FRAGMENT
);
814 /* _NEW_PROGRAM_CONSTANTS */
815 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
,
816 stage_state
, prog_data
);
819 const struct brw_tracked_state brw_wm_pull_constants
= {
821 .mesa
= _NEW_PROGRAM_CONSTANTS
,
822 .brw
= BRW_NEW_BATCH
|
824 BRW_NEW_FRAGMENT_PROGRAM
|
825 BRW_NEW_FS_PROG_DATA
,
827 .emit
= brw_upload_wm_pull_constants
,
831 * Creates a null renderbuffer surface.
833 * This is used when the shader doesn't write to any color output. An FB
834 * write to target 0 will still be emitted, because that's how the thread is
835 * terminated (and computed depth is returned), so we need to have the
836 * hardware discard the target 0 color output..
839 brw_emit_null_surface_state(struct brw_context
*brw
,
843 uint32_t *out_offset
)
845 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
848 * A null surface will be used in instances where an actual surface is
849 * not bound. When a write message is generated to a null surface, no
850 * actual surface is written to. When a read message (including any
851 * sampling engine message) is generated to a null surface, the result
852 * is all zeros. Note that a null surface type is allowed to be used
853 * with all messages, even if it is not specificially indicated as
854 * supported. All of the remaining fields in surface state are ignored
855 * for null surfaces, with the following exceptions:
857 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
858 * depth buffer’s corresponding state for all render target surfaces,
861 * - Surface Format must be R8G8B8A8_UNORM.
863 unsigned surface_type
= BRW_SURFACE_NULL
;
864 struct brw_bo
*bo
= NULL
;
865 unsigned pitch_minus_1
= 0;
866 uint32_t multisampling_state
= 0;
867 uint32_t *surf
= brw_state_batch(brw
, 6 * 4, 32, out_offset
);
870 /* On Gen6, null render targets seem to cause GPU hangs when
871 * multisampling. So work around this problem by rendering into dummy
874 * To decrease the amount of memory needed by the workaround buffer, we
875 * set its pitch to 128 bytes (the width of a Y tile). This means that
876 * the amount of memory needed for the workaround buffer is
877 * (width_in_tiles + height_in_tiles - 1) tiles.
879 * Note that since the workaround buffer will be interpreted by the
880 * hardware as an interleaved multisampled buffer, we need to compute
881 * width_in_tiles and height_in_tiles by dividing the width and height
882 * by 16 rather than the normal Y-tile size of 32.
884 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
885 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
886 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
887 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
889 bo
= brw
->wm
.multisampled_null_render_target_bo
;
890 surface_type
= BRW_SURFACE_2D
;
892 multisampling_state
= brw_get_surface_num_multisamples(samples
);
895 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
896 ISL_FORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
898 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
899 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
900 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
901 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
904 brw_emit_reloc(&brw
->batch
, *out_offset
+ 4, bo
, 0,
905 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
906 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
907 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
909 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
912 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
914 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
915 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
916 surf
[4] = multisampling_state
;
921 * Sets up a surface state structure to point at the given region.
922 * While it is only used for the front/back buffer currently, it should be
923 * usable for further buffers when doing ARB_draw_buffer support.
926 gen4_update_renderbuffer_surface(struct brw_context
*brw
,
927 struct gl_renderbuffer
*rb
,
928 uint32_t flags
, unsigned unit
,
931 struct gl_context
*ctx
= &brw
->ctx
;
932 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
933 struct intel_mipmap_tree
*mt
= irb
->mt
;
935 uint32_t tile_x
, tile_y
;
936 enum isl_format format
;
939 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
940 /* BRW_NEW_FS_PROG_DATA */
942 assert(!(flags
& INTEL_RENDERBUFFER_LAYERED
));
943 assert(!(flags
& INTEL_AUX_BUFFER_DISABLED
));
945 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
946 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
948 if (tile_x
!= 0 || tile_y
!= 0) {
949 /* Original gen4 hardware couldn't draw to a non-tile-aligned
950 * destination in a miptree unless you actually setup your renderbuffer
951 * as a miptree and used the fragile lod/array_index/etc. controls to
952 * select the image. So, instead, we just make a new single-level
953 * miptree and render into that.
955 intel_renderbuffer_move_to_temp(brw
, irb
, false);
956 assert(irb
->align_wa_mt
);
957 mt
= irb
->align_wa_mt
;
961 surf
= brw_state_batch(brw
, 6 * 4, 32, &offset
);
963 format
= brw
->mesa_to_isl_render_format
[rb_format
];
964 if (unlikely(!brw
->mesa_format_supports_render
[rb_format
])) {
965 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
966 __func__
, _mesa_get_format_name(rb_format
));
969 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
970 format
<< BRW_SURFACE_FORMAT_SHIFT
);
973 assert(mt
->offset
% mt
->cpp
== 0);
974 surf
[1] = brw_emit_reloc(&brw
->batch
, offset
+ 4, mt
->bo
,
976 intel_renderbuffer_get_tile_offsets(irb
,
979 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
981 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
982 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
984 surf
[3] = (brw_get_surface_tiling_bits(mt
->surf
.tiling
) |
985 (mt
->surf
.row_pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
987 surf
[4] = brw_get_surface_num_multisamples(mt
->surf
.samples
);
989 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
990 /* Note that the low bits of these fields are missing, so
991 * there's the possibility of getting in trouble.
993 assert(tile_x
% 4 == 0);
994 assert(tile_y
% 2 == 0);
995 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
996 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
997 (mt
->surf
.image_alignment_el
.height
== 4 ?
998 BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
1002 if (!ctx
->Color
.ColorLogicOpEnabled
&& !ctx
->Color
._AdvancedBlendMode
&&
1003 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
1004 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
1006 if (!ctx
->Color
.ColorMask
[unit
][0])
1007 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
1008 if (!ctx
->Color
.ColorMask
[unit
][1])
1009 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
1010 if (!ctx
->Color
.ColorMask
[unit
][2])
1011 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
1013 /* As mentioned above, disable writes to the alpha component when the
1014 * renderbuffer is XRGB.
1016 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
1017 !ctx
->Color
.ColorMask
[unit
][3]) {
1018 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
1026 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1029 brw_update_renderbuffer_surfaces(struct brw_context
*brw
,
1030 const struct gl_framebuffer
*fb
,
1031 uint32_t render_target_start
,
1032 uint32_t *surf_offset
)
1035 const unsigned int w
= _mesa_geometric_width(fb
);
1036 const unsigned int h
= _mesa_geometric_height(fb
);
1037 const unsigned int s
= _mesa_geometric_samples(fb
);
1039 /* Update surfaces for drawing buffers */
1040 if (fb
->_NumColorDrawBuffers
>= 1) {
1041 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1042 const uint32_t surf_index
= render_target_start
+ i
;
1043 const int flags
= (_mesa_geometric_layers(fb
) > 0 ?
1044 INTEL_RENDERBUFFER_LAYERED
: 0) |
1045 (brw
->draw_aux_buffer_disabled
[i
] ?
1046 INTEL_AUX_BUFFER_DISABLED
: 0);
1048 if (intel_renderbuffer(fb
->_ColorDrawBuffers
[i
])) {
1049 surf_offset
[surf_index
] =
1050 brw
->vtbl
.update_renderbuffer_surface(
1051 brw
, fb
->_ColorDrawBuffers
[i
], flags
, i
, surf_index
);
1053 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1054 &surf_offset
[surf_index
]);
1058 const uint32_t surf_index
= render_target_start
;
1059 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
1060 &surf_offset
[surf_index
]);
1065 update_renderbuffer_surfaces(struct brw_context
*brw
)
1067 const struct gl_context
*ctx
= &brw
->ctx
;
1069 /* BRW_NEW_FS_PROG_DATA */
1070 const struct brw_wm_prog_data
*wm_prog_data
=
1071 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1073 /* _NEW_BUFFERS | _NEW_COLOR */
1074 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1075 brw_update_renderbuffer_surfaces(
1077 wm_prog_data
->binding_table
.render_target_start
,
1078 brw
->wm
.base
.surf_offset
);
1079 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1082 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
1084 .mesa
= _NEW_BUFFERS
|
1086 .brw
= BRW_NEW_BATCH
|
1088 BRW_NEW_FS_PROG_DATA
,
1090 .emit
= update_renderbuffer_surfaces
,
1093 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
1095 .mesa
= _NEW_BUFFERS
,
1096 .brw
= BRW_NEW_BATCH
|
1099 .emit
= update_renderbuffer_surfaces
,
1103 update_renderbuffer_read_surfaces(struct brw_context
*brw
)
1105 const struct gl_context
*ctx
= &brw
->ctx
;
1107 /* BRW_NEW_FS_PROG_DATA */
1108 const struct brw_wm_prog_data
*wm_prog_data
=
1109 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
1111 /* BRW_NEW_FRAGMENT_PROGRAM */
1112 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
1113 brw
->fragment_program
&& brw
->fragment_program
->info
.outputs_read
) {
1115 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1117 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1118 struct gl_renderbuffer
*rb
= fb
->_ColorDrawBuffers
[i
];
1119 const struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
1120 const unsigned surf_index
=
1121 wm_prog_data
->binding_table
.render_target_read_start
+ i
;
1122 uint32_t *surf_offset
= &brw
->wm
.base
.surf_offset
[surf_index
];
1125 const enum isl_format format
= brw
->mesa_to_isl_render_format
[
1126 _mesa_get_render_format(ctx
, intel_rb_format(irb
))];
1127 assert(isl_format_supports_sampling(&brw
->screen
->devinfo
,
1130 /* Override the target of the texture if the render buffer is a
1131 * single slice of a 3D texture (since the minimum array element
1132 * field of the surface state structure is ignored by the sampler
1133 * unit for 3D textures on some hardware), or if the render buffer
1134 * is a 1D array (since shaders always provide the array index
1135 * coordinate at the Z component to avoid state-dependent
1136 * recompiles when changing the texture target of the
1139 const GLenum target
=
1140 (irb
->mt
->target
== GL_TEXTURE_3D
&&
1141 irb
->layer_count
== 1) ? GL_TEXTURE_2D
:
1142 irb
->mt
->target
== GL_TEXTURE_1D_ARRAY
? GL_TEXTURE_2D_ARRAY
:
1145 const struct isl_view view
= {
1147 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
1149 .base_array_layer
= irb
->mt_layer
,
1150 .array_len
= irb
->layer_count
,
1151 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1152 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
1155 enum isl_aux_usage aux_usage
=
1156 intel_miptree_texture_aux_usage(brw
, irb
->mt
, format
);
1157 if (brw
->draw_aux_buffer_disabled
[i
])
1158 aux_usage
= ISL_AUX_USAGE_NONE
;
1160 brw_emit_surface_state(brw
, irb
->mt
, target
, view
, aux_usage
,
1162 surf_offset
, surf_index
,
1163 I915_GEM_DOMAIN_SAMPLER
, 0);
1166 brw
->vtbl
.emit_null_surface_state(
1167 brw
, _mesa_geometric_width(fb
), _mesa_geometric_height(fb
),
1168 _mesa_geometric_samples(fb
), surf_offset
);
1172 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1176 const struct brw_tracked_state brw_renderbuffer_read_surfaces
= {
1178 .mesa
= _NEW_BUFFERS
,
1179 .brw
= BRW_NEW_BATCH
|
1180 BRW_NEW_FRAGMENT_PROGRAM
|
1181 BRW_NEW_FS_PROG_DATA
,
1183 .emit
= update_renderbuffer_read_surfaces
,
1187 update_stage_texture_surfaces(struct brw_context
*brw
,
1188 const struct gl_program
*prog
,
1189 struct brw_stage_state
*stage_state
,
1190 bool for_gather
, uint32_t plane
)
1195 struct gl_context
*ctx
= &brw
->ctx
;
1197 uint32_t *surf_offset
= stage_state
->surf_offset
;
1199 /* BRW_NEW_*_PROG_DATA */
1201 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
1203 surf_offset
+= stage_state
->prog_data
->binding_table
.plane_start
[plane
];
1205 unsigned num_samplers
= util_last_bit(prog
->SamplersUsed
);
1206 for (unsigned s
= 0; s
< num_samplers
; s
++) {
1209 if (prog
->SamplersUsed
& (1 << s
)) {
1210 const unsigned unit
= prog
->SamplerUnits
[s
];
1213 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1214 brw_update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
, plane
);
1222 * Construct SURFACE_STATE objects for enabled textures.
1225 brw_update_texture_surfaces(struct brw_context
*brw
)
1227 /* BRW_NEW_VERTEX_PROGRAM */
1228 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
1230 /* BRW_NEW_TESS_PROGRAMS */
1231 struct gl_program
*tcs
= (struct gl_program
*) brw
->tess_ctrl_program
;
1232 struct gl_program
*tes
= (struct gl_program
*) brw
->tess_eval_program
;
1234 /* BRW_NEW_GEOMETRY_PROGRAM */
1235 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
1237 /* BRW_NEW_FRAGMENT_PROGRAM */
1238 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
1241 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false, 0);
1242 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, false, 0);
1243 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, false, 0);
1244 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false, 0);
1245 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 0);
1247 /* emit alternate set of surface state for gather. this
1248 * allows the surface format to be overriden for only the
1249 * gather4 messages. */
1251 if (vs
&& vs
->nir
->info
.uses_texture_gather
)
1252 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true, 0);
1253 if (tcs
&& tcs
->nir
->info
.uses_texture_gather
)
1254 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, true, 0);
1255 if (tes
&& tes
->nir
->info
.uses_texture_gather
)
1256 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, true, 0);
1257 if (gs
&& gs
->nir
->info
.uses_texture_gather
)
1258 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true, 0);
1259 if (fs
&& fs
->nir
->info
.uses_texture_gather
)
1260 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true, 0);
1264 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 1);
1265 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 2);
1268 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1271 const struct brw_tracked_state brw_texture_surfaces
= {
1273 .mesa
= _NEW_TEXTURE
,
1274 .brw
= BRW_NEW_BATCH
|
1276 BRW_NEW_FRAGMENT_PROGRAM
|
1277 BRW_NEW_FS_PROG_DATA
|
1278 BRW_NEW_GEOMETRY_PROGRAM
|
1279 BRW_NEW_GS_PROG_DATA
|
1280 BRW_NEW_TESS_PROGRAMS
|
1281 BRW_NEW_TCS_PROG_DATA
|
1282 BRW_NEW_TES_PROG_DATA
|
1283 BRW_NEW_TEXTURE_BUFFER
|
1284 BRW_NEW_VERTEX_PROGRAM
|
1285 BRW_NEW_VS_PROG_DATA
,
1287 .emit
= brw_update_texture_surfaces
,
1291 brw_update_cs_texture_surfaces(struct brw_context
*brw
)
1293 /* BRW_NEW_COMPUTE_PROGRAM */
1294 struct gl_program
*cs
= (struct gl_program
*) brw
->compute_program
;
1297 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, false, 0);
1299 /* emit alternate set of surface state for gather. this
1300 * allows the surface format to be overriden for only the
1304 if (cs
&& cs
->nir
->info
.uses_texture_gather
)
1305 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, true, 0);
1308 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1311 const struct brw_tracked_state brw_cs_texture_surfaces
= {
1313 .mesa
= _NEW_TEXTURE
,
1314 .brw
= BRW_NEW_BATCH
|
1316 BRW_NEW_COMPUTE_PROGRAM
,
1318 .emit
= brw_update_cs_texture_surfaces
,
1323 brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1324 struct brw_stage_state
*stage_state
,
1325 struct brw_stage_prog_data
*prog_data
)
1327 struct gl_context
*ctx
= &brw
->ctx
;
1332 uint32_t *ubo_surf_offsets
=
1333 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
1335 for (int i
= 0; i
< prog
->info
.num_ubos
; i
++) {
1336 struct gl_uniform_buffer_binding
*binding
=
1337 &ctx
->UniformBufferBindings
[prog
->sh
.UniformBlocks
[i
]->Binding
];
1339 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1340 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ubo_surf_offsets
[i
]);
1342 struct intel_buffer_object
*intel_bo
=
1343 intel_buffer_object(binding
->BufferObject
);
1344 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1345 if (!binding
->AutomaticSize
)
1346 size
= MIN2(size
, binding
->Size
);
1348 intel_bufferobj_buffer(brw
, intel_bo
,
1351 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
1353 &ubo_surf_offsets
[i
]);
1357 uint32_t *ssbo_surf_offsets
=
1358 &stage_state
->surf_offset
[prog_data
->binding_table
.ssbo_start
];
1360 for (int i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
1361 struct gl_shader_storage_buffer_binding
*binding
=
1362 &ctx
->ShaderStorageBufferBindings
[prog
->sh
.ShaderStorageBlocks
[i
]->Binding
];
1364 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1365 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ssbo_surf_offsets
[i
]);
1367 struct intel_buffer_object
*intel_bo
=
1368 intel_buffer_object(binding
->BufferObject
);
1369 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1370 if (!binding
->AutomaticSize
)
1371 size
= MIN2(size
, binding
->Size
);
1373 intel_bufferobj_buffer(brw
, intel_bo
,
1376 brw_create_buffer_surface(brw
, bo
, binding
->Offset
,
1378 &ssbo_surf_offsets
[i
]);
1382 stage_state
->push_constants_dirty
= true;
1384 if (prog
->info
.num_ubos
|| prog
->info
.num_ssbos
)
1385 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1389 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
1391 struct gl_context
*ctx
= &brw
->ctx
;
1393 struct gl_program
*prog
= ctx
->FragmentProgram
._Current
;
1395 /* BRW_NEW_FS_PROG_DATA */
1396 brw_upload_ubo_surfaces(brw
, prog
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1399 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
1401 .mesa
= _NEW_PROGRAM
,
1402 .brw
= BRW_NEW_BATCH
|
1404 BRW_NEW_FS_PROG_DATA
|
1405 BRW_NEW_UNIFORM_BUFFER
,
1407 .emit
= brw_upload_wm_ubo_surfaces
,
1411 brw_upload_cs_ubo_surfaces(struct brw_context
*brw
)
1413 struct gl_context
*ctx
= &brw
->ctx
;
1415 struct gl_program
*prog
=
1416 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1418 /* BRW_NEW_CS_PROG_DATA */
1419 brw_upload_ubo_surfaces(brw
, prog
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1422 const struct brw_tracked_state brw_cs_ubo_surfaces
= {
1424 .mesa
= _NEW_PROGRAM
,
1425 .brw
= BRW_NEW_BATCH
|
1427 BRW_NEW_CS_PROG_DATA
|
1428 BRW_NEW_UNIFORM_BUFFER
,
1430 .emit
= brw_upload_cs_ubo_surfaces
,
1434 brw_upload_abo_surfaces(struct brw_context
*brw
,
1435 const struct gl_program
*prog
,
1436 struct brw_stage_state
*stage_state
,
1437 struct brw_stage_prog_data
*prog_data
)
1439 struct gl_context
*ctx
= &brw
->ctx
;
1440 uint32_t *surf_offsets
=
1441 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
1443 if (prog
->info
.num_abos
) {
1444 for (unsigned i
= 0; i
< prog
->info
.num_abos
; i
++) {
1445 struct gl_atomic_buffer_binding
*binding
=
1446 &ctx
->AtomicBufferBindings
[prog
->sh
.AtomicBuffers
[i
]->Binding
];
1447 struct intel_buffer_object
*intel_bo
=
1448 intel_buffer_object(binding
->BufferObject
);
1450 intel_bufferobj_buffer(brw
, intel_bo
, binding
->Offset
,
1451 intel_bo
->Base
.Size
- binding
->Offset
,
1454 brw_emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
1455 binding
->Offset
, ISL_FORMAT_RAW
,
1456 bo
->size
- binding
->Offset
, 1, true);
1459 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1464 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
1467 const struct gl_program
*wm
= brw
->fragment_program
;
1470 /* BRW_NEW_FS_PROG_DATA */
1471 brw_upload_abo_surfaces(brw
, wm
, &brw
->wm
.base
, brw
->wm
.base
.prog_data
);
1475 const struct brw_tracked_state brw_wm_abo_surfaces
= {
1477 .mesa
= _NEW_PROGRAM
,
1478 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1481 BRW_NEW_FS_PROG_DATA
,
1483 .emit
= brw_upload_wm_abo_surfaces
,
1487 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1490 const struct gl_program
*cp
= brw
->compute_program
;
1493 /* BRW_NEW_CS_PROG_DATA */
1494 brw_upload_abo_surfaces(brw
, cp
, &brw
->cs
.base
, brw
->cs
.base
.prog_data
);
1498 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1500 .mesa
= _NEW_PROGRAM
,
1501 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1504 BRW_NEW_CS_PROG_DATA
,
1506 .emit
= brw_upload_cs_abo_surfaces
,
1510 brw_upload_cs_image_surfaces(struct brw_context
*brw
)
1513 const struct gl_program
*cp
= brw
->compute_program
;
1516 /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1517 brw_upload_image_surfaces(brw
, cp
, &brw
->cs
.base
,
1518 brw
->cs
.base
.prog_data
);
1522 const struct brw_tracked_state brw_cs_image_surfaces
= {
1524 .mesa
= _NEW_TEXTURE
| _NEW_PROGRAM
,
1525 .brw
= BRW_NEW_BATCH
|
1527 BRW_NEW_CS_PROG_DATA
|
1530 .emit
= brw_upload_cs_image_surfaces
,
1534 get_image_format(struct brw_context
*brw
, mesa_format format
, GLenum access
)
1536 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1537 enum isl_format hw_format
= brw_isl_format_for_mesa_format(format
);
1538 if (access
== GL_WRITE_ONLY
) {
1540 } else if (isl_has_matching_typed_storage_image_format(devinfo
, hw_format
)) {
1541 /* Typed surface reads support a very limited subset of the shader
1542 * image formats. Translate it into the closest format the
1543 * hardware supports.
1545 return isl_lower_storage_image_format(devinfo
, hw_format
);
1547 /* The hardware doesn't actually support a typed format that we can use
1548 * so we have to fall back to untyped read/write messages.
1550 return ISL_FORMAT_RAW
;
1555 update_default_image_param(struct brw_context
*brw
,
1556 struct gl_image_unit
*u
,
1557 unsigned surface_idx
,
1558 struct brw_image_param
*param
)
1560 memset(param
, 0, sizeof(*param
));
1561 param
->surface_idx
= surface_idx
;
1562 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1563 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1564 * detailed explanation of these parameters.
1566 param
->swizzling
[0] = 0xff;
1567 param
->swizzling
[1] = 0xff;
1571 update_buffer_image_param(struct brw_context
*brw
,
1572 struct gl_image_unit
*u
,
1573 unsigned surface_idx
,
1574 struct brw_image_param
*param
)
1576 struct gl_buffer_object
*obj
= u
->TexObj
->BufferObject
;
1577 const uint32_t size
= MIN2((uint32_t)u
->TexObj
->BufferSize
, obj
->Size
);
1578 update_default_image_param(brw
, u
, surface_idx
, param
);
1580 param
->size
[0] = size
/ _mesa_get_format_bytes(u
->_ActualFormat
);
1581 param
->stride
[0] = _mesa_get_format_bytes(u
->_ActualFormat
);
1585 get_image_num_layers(const struct intel_mipmap_tree
*mt
, GLenum target
,
1588 if (target
== GL_TEXTURE_CUBE_MAP
)
1591 return target
== GL_TEXTURE_3D
?
1592 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1593 mt
->surf
.logical_level0_px
.array_len
;
1597 update_image_surface(struct brw_context
*brw
,
1598 struct gl_image_unit
*u
,
1600 unsigned surface_idx
,
1601 uint32_t *surf_offset
,
1602 struct brw_image_param
*param
)
1604 if (_mesa_is_image_unit_valid(&brw
->ctx
, u
)) {
1605 struct gl_texture_object
*obj
= u
->TexObj
;
1606 const unsigned format
= get_image_format(brw
, u
->_ActualFormat
, access
);
1608 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
1609 struct intel_buffer_object
*intel_obj
=
1610 intel_buffer_object(obj
->BufferObject
);
1611 const unsigned texel_size
= (format
== ISL_FORMAT_RAW
? 1 :
1612 _mesa_get_format_bytes(u
->_ActualFormat
));
1614 brw_emit_buffer_surface_state(
1615 brw
, surf_offset
, intel_obj
->buffer
, obj
->BufferOffset
,
1616 format
, intel_obj
->Base
.Size
, texel_size
,
1617 access
!= GL_READ_ONLY
);
1619 update_buffer_image_param(brw
, u
, surface_idx
, param
);
1622 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
1623 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
1624 const unsigned num_layers
= u
->Layered
?
1625 get_image_num_layers(mt
, obj
->Target
, u
->Level
) : 1;
1627 struct isl_view view
= {
1629 .base_level
= obj
->MinLevel
+ u
->Level
,
1631 .base_array_layer
= obj
->MinLayer
+ u
->_Layer
,
1632 .array_len
= num_layers
,
1633 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1634 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
1637 if (format
== ISL_FORMAT_RAW
) {
1638 brw_emit_buffer_surface_state(
1639 brw
, surf_offset
, mt
->bo
, mt
->offset
,
1640 format
, mt
->bo
->size
- mt
->offset
, 1 /* pitch */,
1641 access
!= GL_READ_ONLY
);
1644 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
1645 assert(!intel_miptree_has_color_unresolved(mt
,
1647 view
.base_array_layer
,
1649 brw_emit_surface_state(brw
, mt
, mt
->target
, view
,
1650 ISL_AUX_USAGE_NONE
, tex_mocs
[brw
->gen
],
1651 surf_offset
, surf_index
,
1652 I915_GEM_DOMAIN_SAMPLER
,
1653 access
== GL_READ_ONLY
? 0 :
1654 I915_GEM_DOMAIN_SAMPLER
);
1657 isl_surf_fill_image_param(&brw
->isl_dev
, param
, &mt
->surf
, &view
);
1658 param
->surface_idx
= surface_idx
;
1662 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, surf_offset
);
1663 update_default_image_param(brw
, u
, surface_idx
, param
);
1668 brw_upload_image_surfaces(struct brw_context
*brw
,
1669 const struct gl_program
*prog
,
1670 struct brw_stage_state
*stage_state
,
1671 struct brw_stage_prog_data
*prog_data
)
1674 struct gl_context
*ctx
= &brw
->ctx
;
1676 if (prog
->info
.num_images
) {
1677 for (unsigned i
= 0; i
< prog
->info
.num_images
; i
++) {
1678 struct gl_image_unit
*u
= &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[i
]];
1679 const unsigned surf_idx
= prog_data
->binding_table
.image_start
+ i
;
1681 update_image_surface(brw
, u
, prog
->sh
.ImageAccess
[i
],
1683 &stage_state
->surf_offset
[surf_idx
],
1684 &prog_data
->image_param
[i
]);
1687 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1688 /* This may have changed the image metadata dependent on the context
1689 * image unit state and passed to the program as uniforms, make sure
1690 * that push and pull constants are reuploaded.
1692 brw
->NewGLState
|= _NEW_PROGRAM_CONSTANTS
;
1697 brw_upload_wm_image_surfaces(struct brw_context
*brw
)
1699 /* BRW_NEW_FRAGMENT_PROGRAM */
1700 const struct gl_program
*wm
= brw
->fragment_program
;
1703 /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1704 brw_upload_image_surfaces(brw
, wm
, &brw
->wm
.base
,
1705 brw
->wm
.base
.prog_data
);
1709 const struct brw_tracked_state brw_wm_image_surfaces
= {
1711 .mesa
= _NEW_TEXTURE
,
1712 .brw
= BRW_NEW_BATCH
|
1714 BRW_NEW_FRAGMENT_PROGRAM
|
1715 BRW_NEW_FS_PROG_DATA
|
1718 .emit
= brw_upload_wm_image_surfaces
,
1722 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
1724 brw
->vtbl
.update_renderbuffer_surface
= gen4_update_renderbuffer_surface
;
1725 brw
->vtbl
.emit_null_surface_state
= brw_emit_null_surface_state
;
1729 gen6_init_vtable_surface_functions(struct brw_context
*brw
)
1731 gen4_init_vtable_surface_functions(brw
);
1732 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
1736 brw_upload_cs_work_groups_surface(struct brw_context
*brw
)
1738 struct gl_context
*ctx
= &brw
->ctx
;
1740 struct gl_program
*prog
=
1741 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1742 /* BRW_NEW_CS_PROG_DATA */
1743 const struct brw_cs_prog_data
*cs_prog_data
=
1744 brw_cs_prog_data(brw
->cs
.base
.prog_data
);
1746 if (prog
&& cs_prog_data
->uses_num_work_groups
) {
1747 const unsigned surf_idx
=
1748 cs_prog_data
->binding_table
.work_groups_start
;
1749 uint32_t *surf_offset
= &brw
->cs
.base
.surf_offset
[surf_idx
];
1753 if (brw
->compute
.num_work_groups_bo
== NULL
) {
1755 intel_upload_data(brw
,
1756 (void *)brw
->compute
.num_work_groups
,
1762 bo
= brw
->compute
.num_work_groups_bo
;
1763 bo_offset
= brw
->compute
.num_work_groups_offset
;
1766 brw_emit_buffer_surface_state(brw
, surf_offset
,
1769 3 * sizeof(GLuint
), 1, true);
1770 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1774 const struct brw_tracked_state brw_cs_work_groups_surface
= {
1776 .brw
= BRW_NEW_BLORP
|
1777 BRW_NEW_CS_PROG_DATA
|
1778 BRW_NEW_CS_WORK_GROUPS
1780 .emit
= brw_upload_cs_work_groups_surface
,