src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45 #include "brw_wm.h"
  46
  47 GLuint
  48 translate_tex_target(GLenum target)
  49 {
  50    switch (target) {
  51    case GL_TEXTURE_1D:
  52    case GL_TEXTURE_1D_ARRAY_EXT:
  53       return BRW_SURFACE_1D;
  54
  55    case GL_TEXTURE_RECTANGLE_NV:
  56       return BRW_SURFACE_2D;
  57
  58    case GL_TEXTURE_2D:
  59    case GL_TEXTURE_2D_ARRAY_EXT:
  60       return BRW_SURFACE_2D;
  61
  62    case GL_TEXTURE_3D:
  63       return BRW_SURFACE_3D;
  64
  65    case GL_TEXTURE_CUBE_MAP:
  66       return BRW_SURFACE_CUBE;
  67
  68    default:
  69       assert(0);
  70       return 0;
  71    }
  72 }
  73
  74 uint32_t
  75 brw_format_for_mesa_format(gl_format mesa_format)
  76 {
  77    static const uint32_t table[MESA_FORMAT_COUNT] =
  78    {
  79       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
  80       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
  81       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
  82       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
  83       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
  84       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
  85       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
  86       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
  87       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
  88       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
  89       [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
  90       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
  91       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
  92       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
  93       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
  94       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
  95       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
  96       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
  97       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
  98       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
  99       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 100       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 101       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 102       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 103       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 104       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 105       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 106       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 107       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 108       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 109       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 110       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 111       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 112       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 113       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 114       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 115       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 116       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 117       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 118       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 119       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 120       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 121       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 122       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 123       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 124       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 125       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 126       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 127       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 128       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 129       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 130
 131       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 132       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 133       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 134       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 135
 136       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 137       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 138       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 139       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 140
 141       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 142       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 143       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 144       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 145       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 146       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 147
 148       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 149       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 150       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 151       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 152       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 153       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 154    };
 155    assert(mesa_format < MESA_FORMAT_COUNT);
 156    return table[mesa_format];
 157 }
 158
 159 bool
 160 brw_render_target_supported(gl_format format)
 161 {
 162    /* These are not color render targets like the table holds, but we
 163     * ask the question for FBO completeness.
 164     */
 165    if (format == MESA_FORMAT_S8_Z24 ||
 166        format == MESA_FORMAT_X8_Z24 ||
 167        format == MESA_FORMAT_S8 ||
 168        format == MESA_FORMAT_Z16) {
 169       return true;
 170    }
 171
 172    /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
 173     */
 174    if (format == MESA_FORMAT_RGBA_FLOAT32)
 175       return true;
 176
 177    /* Not exactly true, as some of those formats are not renderable.
 178     * But at least we know how to translate them.
 179     */
 180    return brw_format_for_mesa_format(format) != 0;
 181 }
 182
 183 GLuint
 184 translate_tex_format(gl_format mesa_format,
 185                      GLenum internal_format,
 186                      GLenum depth_mode,
 187                      GLenum srgb_decode)
 188 {
 189    switch( mesa_format ) {
 190
 191    case MESA_FORMAT_Z16:
 192       if (depth_mode == GL_INTENSITY)
 193           return BRW_SURFACEFORMAT_I16_UNORM;
 194       else if (depth_mode == GL_ALPHA)
 195           return BRW_SURFACEFORMAT_A16_UNORM;
 196       else if (depth_mode == GL_RED)
 197           return BRW_SURFACEFORMAT_R16_UNORM;
 198       else
 199           return BRW_SURFACEFORMAT_L16_UNORM;
 200
 201    case MESA_FORMAT_S8_Z24:
 202    case MESA_FORMAT_X8_Z24:
 203       /* XXX: these different surface formats don't seem to
 204        * make any difference for shadow sampler/compares.
 205        */
 206       if (depth_mode == GL_INTENSITY)
 207          return BRW_SURFACEFORMAT_I24X8_UNORM;
 208       else if (depth_mode == GL_ALPHA)
 209          return BRW_SURFACEFORMAT_A24X8_UNORM;
 210       else if (depth_mode == GL_RED)
 211          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 212       else
 213          return BRW_SURFACEFORMAT_L24X8_UNORM;
 214
 215    case MESA_FORMAT_SARGB8:
 216    case MESA_FORMAT_SLA8:
 217    case MESA_FORMAT_SL8:
 218       if (srgb_decode == GL_DECODE_EXT)
 219          return brw_format_for_mesa_format(mesa_format);
 220       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 221          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 222
 223    case MESA_FORMAT_RGBA8888_REV:
 224       /* This format is not renderable? */
 225       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 226
 227    case MESA_FORMAT_RGBA_FLOAT32:
 228       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 229        * assertion below.
 230        */
 231       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 232
 233    default:
 234       assert(brw_format_for_mesa_format(mesa_format) != 0);
 235       return brw_format_for_mesa_format(mesa_format);
 236    }
 237 }
 238
 239 static uint32_t
 240 brw_get_surface_tiling_bits(uint32_t tiling)
 241 {
 242    switch (tiling) {
 243    case I915_TILING_X:
 244       return BRW_SURFACE_TILED;
 245    case I915_TILING_Y:
 246       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 247    default:
 248       return 0;
 249    }
 250 }
 251
 252 static void
 253 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 254 {
 255    struct brw_context *brw = brw_context(ctx);
 256    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 257    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 258    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 259    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 260    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 261    uint32_t *surf;
 262    int width, height, depth;
 263
 264    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 265
 266    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 267                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 268
 269    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 270               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 271               BRW_SURFACE_CUBEFACE_ENABLES |
 272               (translate_tex_format(firstImage->TexFormat,
 273                                     firstImage->InternalFormat,
 274                                     sampler->DepthMode,
 275                                     sampler->sRGBDecode) <<
 276                BRW_SURFACE_FORMAT_SHIFT));
 277
 278    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 279
 280    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 281               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 282               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 283
 284    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 285               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 286               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 287               BRW_SURFACE_PITCH_SHIFT);
 288
 289    surf[4] = 0;
 290    surf[5] = 0;
 291
 292    /* Emit relocation to surface contents */
 293    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 294                            brw->wm.surf_offset[surf_index] + 4,
 295                            intelObj->mt->region->bo, 0,
 296                            I915_GEM_DOMAIN_SAMPLER, 0);
 297 }
 298
 299 /**
 300  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 301  * read from this buffer with Data Port Read instructions/messages.
 302  */
 303 void
 304 brw_create_constant_surface(struct brw_context *brw,
 305                             drm_intel_bo *bo,
 306                             int width,
 307                             uint32_t *out_offset)
 308 {
 309    struct intel_context *intel = &brw->intel;
 310    const GLint w = width - 1;
 311    uint32_t *surf;
 312
 313    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 314                           6 * 4, 32, out_offset);
 315
 316    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 317               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 318               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 319
 320    if (intel->gen >= 6)
 321       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 322
 323    surf[1] = bo->offset; /* reloc */
 324
 325    surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
 326               (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 327
 328    surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
 329               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 330
 331    surf[4] = 0;
 332    surf[5] = 0;
 333
 334    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 335     * bspec ("Data Cache") says that the data cache does not exist as
 336     * a separate cache and is just the sampler cache.
 337     */
 338    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 339                            *out_offset + 4,
 340                            bo, 0,
 341                            I915_GEM_DOMAIN_SAMPLER, 0);
 342 }
 343
 344 /* Creates a new WM constant buffer reflecting the current fragment program's
 345  * constants, if needed by the fragment program.
 346  *
 347  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 348  * state atom.
 349  */
 350 static void
 351 brw_upload_wm_pull_constants(struct brw_context *brw)
 352 {
 353    struct gl_context *ctx = &brw->intel.ctx;
 354    struct intel_context *intel = &brw->intel;
 355    struct brw_fragment_program *fp =
 356       (struct brw_fragment_program *) brw->fragment_program;
 357    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 358    float *constants;
 359    unsigned int i;
 360
 361    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 362
 363    /* BRW_NEW_FRAGMENT_PROGRAM */
 364    if (brw->wm.prog_data->nr_pull_params == 0) {
 365       if (brw->wm.const_bo) {
 366          drm_intel_bo_unreference(brw->wm.const_bo);
 367          brw->wm.const_bo = NULL;
 368          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 369       }
 370       return;
 371    }
 372
 373    drm_intel_bo_unreference(brw->wm.const_bo);
 374    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 375                                          size, 64);
 376
 377    /* _NEW_PROGRAM_CONSTANTS */
 378    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 379    constants = brw->wm.const_bo->virtual;
 380    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 381       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 382                                    brw->wm.prog_data->pull_param[i]);
 383    }
 384    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 385
 386    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 387 }
 388
 389 const struct brw_tracked_state brw_wm_constants = {
 390    .dirty = {
 391       .mesa = (_NEW_PROGRAM_CONSTANTS),
 392       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 393       .cache = 0
 394    },
 395    .emit = brw_upload_wm_pull_constants,
 396 };
 397
 398 /**
 399  * Updates surface / buffer for fragment shader constant buffer, if
 400  * one is required.
 401  *
 402  * This consumes the state updates for the constant buffer, and produces
 403  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 404  * inclusion in the binding table.
 405  */
 406 static void upload_wm_constant_surface(struct brw_context *brw )
 407 {
 408    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 409    struct brw_fragment_program *fp =
 410       (struct brw_fragment_program *) brw->fragment_program;
 411    const struct gl_program_parameter_list *params =
 412       fp->program.Base.Parameters;
 413
 414    /* If there's no constant buffer, then no surface BO is needed to point at
 415     * it.
 416     */
 417    if (brw->wm.const_bo == 0) {
 418       if (brw->wm.surf_offset[surf]) {
 419          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 420          brw->wm.surf_offset[surf] = 0;
 421       }
 422       return;
 423    }
 424
 425    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 426                                &brw->wm.surf_offset[surf]);
 427    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 428 }
 429
 430 const struct brw_tracked_state brw_wm_constant_surface = {
 431    .dirty = {
 432       .mesa = 0,
 433       .brw = (BRW_NEW_WM_CONSTBUF |
 434               BRW_NEW_BATCH),
 435       .cache = 0
 436    },
 437    .emit = upload_wm_constant_surface,
 438 };
 439
 440 static void
 441 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 442 {
 443    struct intel_context *intel = &brw->intel;
 444    uint32_t *surf;
 445
 446    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 447                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 448
 449    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 450               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 451    if (intel->gen < 6) {
 452       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 453                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 454                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 455                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 456    }
 457    surf[1] = 0;
 458    surf[2] = 0;
 459    surf[3] = 0;
 460    surf[4] = 0;
 461    surf[5] = 0;
 462 }
 463
 464 /**
 465  * Sets up a surface state structure to point at the given region.
 466  * While it is only used for the front/back buffer currently, it should be
 467  * usable for further buffers when doing ARB_draw_buffer support.
 468  */
 469 static void
 470 brw_update_renderbuffer_surface(struct brw_context *brw,
 471                                 struct gl_renderbuffer *rb,
 472                                 unsigned int unit)
 473 {
 474    struct intel_context *intel = &brw->intel;
 475    struct gl_context *ctx = &intel->ctx;
 476    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 477    struct intel_region *region = irb->region;
 478    uint32_t *surf;
 479    uint32_t tile_x, tile_y;
 480    uint32_t format = 0;
 481
 482    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 483                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 484
 485    switch (irb->Base.Format) {
 486    case MESA_FORMAT_XRGB8888:
 487       /* XRGB is handled as ARGB because the chips in this family
 488        * cannot render to XRGB targets.  This means that we have to
 489        * mask writes to alpha (ala glColorMask) and reconfigure the
 490        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 491        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 492        * used.
 493        */
 494       format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 495       break;
 496    case MESA_FORMAT_INTENSITY_FLOAT32:
 497    case MESA_FORMAT_LUMINANCE_FLOAT32:
 498       /* For these formats, we just need to read/write the first
 499        * channel into R, which is to say that we just treat them as
 500        * GL_RED.
 501        */
 502       format = BRW_SURFACEFORMAT_R32_FLOAT;
 503       break;
 504    case MESA_FORMAT_SARGB8:
 505       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 506          surfaces to the blend/update as sRGB */
 507       if (ctx->Color.sRGBEnabled)
 508          format = brw_format_for_mesa_format(irb->Base.Format);
 509       else
 510          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 511       break;
 512    default:
 513       assert(brw_render_target_supported(irb->Base.Format));
 514       format = brw_format_for_mesa_format(irb->Base.Format);
 515    }
 516
 517    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 518               format << BRW_SURFACE_FORMAT_SHIFT);
 519
 520    /* reloc */
 521    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 522               region->bo->offset);
 523
 524    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 525               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 526
 527    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 528               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 529
 530    surf[4] = 0;
 531
 532    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 533    /* Note that the low bits of these fields are missing, so
 534     * there's the possibility of getting in trouble.
 535     */
 536    assert(tile_x % 4 == 0);
 537    assert(tile_y % 2 == 0);
 538    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 539               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT);
 540
 541    if (intel->gen < 6) {
 542       /* _NEW_COLOR */
 543       if (!ctx->Color.ColorLogicOpEnabled &&
 544           (ctx->Color.BlendEnabled & (1 << unit)))
 545          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 546
 547       if (!ctx->Color.ColorMask[unit][0])
 548          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 549       if (!ctx->Color.ColorMask[unit][1])
 550          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 551       if (!ctx->Color.ColorMask[unit][2])
 552          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 553
 554       /* As mentioned above, disable writes to the alpha component when the
 555        * renderbuffer is XRGB.
 556        */
 557       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 558           !ctx->Color.ColorMask[unit][3]) {
 559          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 560       }
 561    }
 562
 563    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 564                            brw->wm.surf_offset[unit] + 4,
 565                            region->bo,
 566                            surf[1] - region->bo->offset,
 567                            I915_GEM_DOMAIN_RENDER,
 568                            I915_GEM_DOMAIN_RENDER);
 569 }
 570
 571 /**
 572  * Constructs the set of surface state objects pointed to by the
 573  * binding table.
 574  */
 575 static void
 576 brw_upload_wm_surfaces(struct brw_context *brw)
 577 {
 578    struct gl_context *ctx = &brw->intel.ctx;
 579    GLuint i;
 580    int nr_surfaces = 0;
 581
 582    /* _NEW_BUFFERS | _NEW_COLOR */
 583    /* Update surfaces for drawing buffers */
 584    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 585       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 586          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 587             brw_update_renderbuffer_surface(brw,
 588                                             ctx->DrawBuffer->_ColorDrawBuffers[i],
 589                                             i);
 590          } else {
 591             brw_update_null_renderbuffer_surface(brw, i);
 592          }
 593       }
 594       nr_surfaces = SURF_INDEX_DRAW(ctx->DrawBuffer->_NumColorDrawBuffers);
 595    } else {
 596       brw_update_null_renderbuffer_surface(brw, 0);
 597       nr_surfaces = SURF_INDEX_DRAW(0) + 1;
 598    }
 599
 600    /* BRW_NEW_WM_CONSTBUF */
 601    if (brw->wm.const_bo) {
 602       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 603    }
 604
 605    /* Update surfaces for textures */
 606    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 607       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 608       const GLuint surf = SURF_INDEX_TEXTURE(i);
 609
 610       /* _NEW_TEXTURE */
 611       if (texUnit->_ReallyEnabled) {
 612          brw_update_texture_surface(ctx, i);
 613          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 614       } else {
 615          brw->wm.surf_offset[surf] = 0;
 616       }
 617    }
 618
 619    if (brw->wm.nr_surfaces != nr_surfaces) {
 620       brw->wm.nr_surfaces = nr_surfaces;
 621       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 622    }
 623
 624    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 625 }
 626
 627 const struct brw_tracked_state brw_wm_surfaces = {
 628    .dirty = {
 629       .mesa = (_NEW_COLOR |
 630                _NEW_TEXTURE |
 631                _NEW_BUFFERS),
 632       .brw = (BRW_NEW_BATCH |
 633               BRW_NEW_WM_CONSTBUF),
 634       .cache = 0
 635    },
 636    .emit = brw_upload_wm_surfaces,
 637 };
 638
 639 /**
 640  * Constructs the binding table for the WM surface state, which maps unit
 641  * numbers to surface state objects.
 642  */
 643 static void
 644 brw_wm_upload_binding_table(struct brw_context *brw)
 645 {
 646    uint32_t *bind;
 647    int i;
 648
 649    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 650     * space for the binding table.
 651     */
 652    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 653                           sizeof(uint32_t) * BRW_WM_MAX_SURF,
 654                           32, &brw->wm.bind_bo_offset);
 655
 656    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 657       /* BRW_NEW_WM_SURFACES */
 658       bind[i] = brw->wm.surf_offset[i];
 659    }
 660
 661    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 662 }
 663
 664 const struct brw_tracked_state brw_wm_binding_table = {
 665    .dirty = {
 666       .mesa = 0,
 667       .brw = (BRW_NEW_BATCH |
 668               BRW_NEW_WM_SURFACES),
 669       .cache = 0
 670    },
 671    .emit = brw_wm_upload_binding_table,
 672 };