2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "texformat.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
47 static GLuint
translate_tex_target( GLenum target
)
51 return BRW_SURFACE_1D
;
53 case GL_TEXTURE_RECTANGLE_NV
:
54 return BRW_SURFACE_2D
;
57 return BRW_SURFACE_2D
;
60 return BRW_SURFACE_3D
;
62 case GL_TEXTURE_CUBE_MAP
:
63 return BRW_SURFACE_CUBE
;
72 static GLuint
translate_tex_format( GLuint mesa_format
, GLenum depth_mode
)
74 switch( mesa_format
) {
76 return BRW_SURFACEFORMAT_L8_UNORM
;
79 return BRW_SURFACEFORMAT_I8_UNORM
;
82 return BRW_SURFACEFORMAT_A8_UNORM
;
84 case MESA_FORMAT_AL88
:
85 return BRW_SURFACEFORMAT_L8A8_UNORM
;
87 case MESA_FORMAT_RGB888
:
88 assert(0); /* not supported for sampling */
89 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
91 case MESA_FORMAT_ARGB8888
:
92 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
94 case MESA_FORMAT_RGBA8888_REV
:
95 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
97 case MESA_FORMAT_RGB565
:
98 return BRW_SURFACEFORMAT_B5G6R5_UNORM
;
100 case MESA_FORMAT_ARGB1555
:
101 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM
;
103 case MESA_FORMAT_ARGB4444
:
104 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM
;
106 case MESA_FORMAT_YCBCR_REV
:
107 return BRW_SURFACEFORMAT_YCRCB_NORMAL
;
109 case MESA_FORMAT_YCBCR
:
110 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY
;
112 case MESA_FORMAT_RGB_FXT1
:
113 case MESA_FORMAT_RGBA_FXT1
:
114 return BRW_SURFACEFORMAT_FXT1
;
116 case MESA_FORMAT_Z16
:
117 if (depth_mode
== GL_INTENSITY
)
118 return BRW_SURFACEFORMAT_I16_UNORM
;
119 else if (depth_mode
== GL_ALPHA
)
120 return BRW_SURFACEFORMAT_A16_UNORM
;
122 return BRW_SURFACEFORMAT_L16_UNORM
;
124 case MESA_FORMAT_RGB_DXT1
:
125 return BRW_SURFACEFORMAT_DXT1_RGB
;
127 case MESA_FORMAT_RGBA_DXT1
:
128 return BRW_SURFACEFORMAT_BC1_UNORM
;
130 case MESA_FORMAT_RGBA_DXT3
:
131 return BRW_SURFACEFORMAT_BC2_UNORM
;
133 case MESA_FORMAT_RGBA_DXT5
:
134 return BRW_SURFACEFORMAT_BC3_UNORM
;
136 case MESA_FORMAT_SRGBA8
:
137 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB
;
138 case MESA_FORMAT_SRGB_DXT1
:
139 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB
;
141 case MESA_FORMAT_Z24_S8
:
142 return BRW_SURFACEFORMAT_I24X8_UNORM
;
150 struct brw_wm_surface_key
{
151 GLenum target
, depthmode
;
154 GLint first_level
, last_level
;
155 GLint width
, height
, depth
;
161 brw_create_texture_surface( struct brw_context
*brw
,
162 struct brw_wm_surface_key
*key
)
164 struct brw_surface_state surf
;
167 memset(&surf
, 0, sizeof(surf
));
169 surf
.ss0
.mipmap_layout_mode
= BRW_SURFACE_MIPMAPLAYOUT_BELOW
;
170 surf
.ss0
.surface_type
= translate_tex_target(key
->target
);
171 surf
.ss0
.surface_format
= translate_tex_format(key
->format
, key
->depthmode
);
173 /* This is ok for all textures with channel width 8bit or less:
175 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
177 surf
.ss1
.base_addr
= key
->bo
->offset
; /* reloc */
179 surf
.ss2
.mip_count
= key
->last_level
- key
->first_level
;
180 surf
.ss2
.width
= key
->width
- 1;
181 surf
.ss2
.height
= key
->height
- 1;
183 surf
.ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
184 surf
.ss3
.tiled_surface
= key
->tiled
;
185 surf
.ss3
.pitch
= (key
->pitch
* key
->cpp
) - 1;
186 surf
.ss3
.depth
= key
->depth
- 1;
188 surf
.ss4
.min_lod
= 0;
190 if (key
->target
== GL_TEXTURE_CUBE_MAP
) {
191 surf
.ss0
.cube_pos_x
= 1;
192 surf
.ss0
.cube_pos_y
= 1;
193 surf
.ss0
.cube_pos_z
= 1;
194 surf
.ss0
.cube_neg_x
= 1;
195 surf
.ss0
.cube_neg_y
= 1;
196 surf
.ss0
.cube_neg_z
= 1;
199 bo
= brw_upload_cache(&brw
->cache
, BRW_SS_SURFACE
,
205 /* Emit relocation to surface contents */
206 intel_bo_emit_reloc(bo
,
207 I915_GEM_DOMAIN_SAMPLER
, 0,
209 offsetof(struct brw_surface_state
, ss1
),
216 brw_update_texture_surface( GLcontext
*ctx
, GLuint unit
)
218 struct brw_context
*brw
= brw_context(ctx
);
219 struct gl_texture_object
*tObj
= brw
->attribs
.Texture
->Unit
[unit
]._Current
;
220 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
221 struct gl_texture_image
*firstImage
= tObj
->Image
[0][intelObj
->firstLevel
];
222 struct brw_wm_surface_key key
;
225 memset(&key
, 0, sizeof(key
));
226 key
.target
= tObj
->Target
;
227 key
.depthmode
= tObj
->DepthMode
;
228 key
.format
= firstImage
->TexFormat
->MesaFormat
;
229 key
.bo
= intelObj
->mt
->region
->buffer
;
230 key
.first_level
= intelObj
->firstLevel
;
231 key
.last_level
= intelObj
->lastLevel
;
232 key
.width
= firstImage
->Width
;
233 key
.height
= firstImage
->Height
;
234 key
.pitch
= intelObj
->mt
->pitch
;
235 key
.cpp
= intelObj
->mt
->cpp
;
236 key
.depth
= firstImage
->Depth
;
237 key
.tiled
= intelObj
->mt
->region
->tiled
;
239 ret
|= dri_bufmgr_check_aperture_space(key
.bo
);
241 dri_bo_unreference(brw
->wm
.surf_bo
[unit
+ MAX_DRAW_BUFFERS
]);
242 brw
->wm
.surf_bo
[unit
+ MAX_DRAW_BUFFERS
] = brw_search_cache(&brw
->cache
, BRW_SS_SURFACE
,
246 if (brw
->wm
.surf_bo
[unit
+ MAX_DRAW_BUFFERS
] == NULL
) {
247 brw
->wm
.surf_bo
[unit
+ MAX_DRAW_BUFFERS
] = brw_create_texture_surface(brw
, &key
);
250 ret
|= dri_bufmgr_check_aperture_space(brw
->wm
.surf_bo
[unit
+ MAX_DRAW_BUFFERS
]);
255 * Sets up a surface state structure to point at the given region.
256 * While it is only used for the front/back buffer currently, it should be
257 * usable for further buffers when doing ARB_draw_buffer support.
260 brw_update_region_surface(struct brw_context
*brw
, struct intel_region
*region
,
261 unsigned int unit
, GLboolean cached
)
263 dri_bo
*region_bo
= NULL
;
266 unsigned int surface_type
;
267 unsigned int surface_format
;
268 unsigned int width
, height
, cpp
;
269 GLubyte color_mask
[4];
270 GLboolean tiled
, color_blend
;
273 memset(&key
, 0, sizeof(key
));
275 if (region
!= NULL
) {
276 region_bo
= region
->buffer
;
278 key
.surface_type
= BRW_SURFACE_2D
;
279 if (region
->cpp
== 4)
280 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
282 key
.surface_format
= BRW_SURFACEFORMAT_B5G6R5_UNORM
;
283 key
.tiled
= region
->tiled
;
284 key
.width
= region
->pitch
; /* XXX: not really! */
285 key
.height
= region
->height
;
286 key
.cpp
= region
->cpp
;
288 ret
|= dri_bufmgr_check_aperture_space(region
->buffer
);
290 key
.surface_type
= BRW_SURFACE_NULL
;
291 key
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
297 memcpy(key
.color_mask
, brw
->attribs
.Color
->ColorMask
,
298 sizeof(key
.color_mask
));
299 key
.color_blend
= (!brw
->attribs
.Color
->_LogicOpEnabled
&&
300 brw
->attribs
.Color
->BlendEnabled
);
302 dri_bo_unreference(brw
->wm
.surf_bo
[unit
]);
303 brw
->wm
.surf_bo
[unit
] = NULL
;
305 brw
->wm
.surf_bo
[unit
] = brw_search_cache(&brw
->cache
, BRW_SS_SURFACE
,
310 if (brw
->wm
.surf_bo
[unit
] == NULL
) {
311 struct brw_surface_state surf
;
313 memset(&surf
, 0, sizeof(surf
));
315 surf
.ss0
.surface_format
= key
.surface_format
;
316 surf
.ss0
.surface_type
= key
.surface_type
;
317 if (region_bo
!= NULL
)
318 surf
.ss1
.base_addr
= region_bo
->offset
; /* reloc */
320 surf
.ss2
.width
= key
.width
- 1;
321 surf
.ss2
.height
= key
.height
- 1;
322 surf
.ss3
.tile_walk
= BRW_TILEWALK_XMAJOR
;
323 surf
.ss3
.tiled_surface
= key
.tiled
;
324 surf
.ss3
.pitch
= (key
.width
* key
.cpp
) - 1;
327 surf
.ss0
.color_blend
= key
.color_blend
;
328 surf
.ss0
.writedisable_red
= !key
.color_mask
[0];
329 surf
.ss0
.writedisable_green
= !key
.color_mask
[1];
330 surf
.ss0
.writedisable_blue
= !key
.color_mask
[2];
331 surf
.ss0
.writedisable_alpha
= !key
.color_mask
[3];
333 /* Key size will never match key size for textures, so we're safe. */
334 brw
->wm
.surf_bo
[unit
] = brw_upload_cache(&brw
->cache
, BRW_SS_SURFACE
,
339 if (region_bo
!= NULL
) {
340 /* We might sample from it, and we might render to it, so flag
341 * them both. We might be able to figure out from other state
342 * a more restrictive relocation to emit.
344 intel_bo_emit_reloc(brw
->wm
.surf_bo
[unit
],
345 I915_GEM_DOMAIN_RENDER
|
346 I915_GEM_DOMAIN_SAMPLER
,
347 I915_GEM_DOMAIN_RENDER
,
349 offsetof(struct brw_surface_state
, ss1
),
354 ret
|= dri_bufmgr_check_aperture_space(brw
->wm
.surf_bo
[unit
]);
361 * Constructs the binding table for the WM surface state, which maps unit
362 * numbers to surface state objects.
365 brw_wm_get_binding_table(struct brw_context
*brw
)
369 bind_bo
= brw_search_cache(&brw
->cache
, BRW_SS_SURF_BIND
,
371 brw
->wm
.surf_bo
, brw
->wm
.nr_surfaces
,
374 if (bind_bo
== NULL
) {
375 GLuint data_size
= brw
->wm
.nr_surfaces
* sizeof(GLuint
);
376 uint32_t *data
= malloc(data_size
);
379 for (i
= 0; i
< brw
->wm
.nr_surfaces
; i
++)
380 if (brw
->wm
.surf_bo
[i
])
381 data
[i
] = brw
->wm
.surf_bo
[i
]->offset
;
385 bind_bo
= brw_upload_cache( &brw
->cache
, BRW_SS_SURF_BIND
,
387 brw
->wm
.surf_bo
, brw
->wm
.nr_surfaces
,
391 /* Emit binding table relocations to surface state */
392 for (i
= 0; i
< BRW_WM_MAX_SURF
; i
++) {
393 if (brw
->wm
.surf_bo
[i
] != NULL
) {
394 intel_bo_emit_reloc(bind_bo
,
395 I915_GEM_DOMAIN_INSTRUCTION
, 0,
408 static int prepare_wm_surfaces(struct brw_context
*brw
)
410 GLcontext
*ctx
= &brw
->intel
.ctx
;
411 struct intel_context
*intel
= &brw
->intel
;
414 if (brw
->state
.nr_draw_regions
> 1) {
415 for (i
= 0; i
< brw
->state
.nr_draw_regions
; i
++) {
416 ret
= brw_update_region_surface(brw
, brw
->state
.draw_regions
[i
], i
,
422 ret
= brw_update_region_surface(brw
, brw
->state
.draw_regions
[0], 0, GL_TRUE
);
427 brw
->wm
.nr_surfaces
= MAX_DRAW_BUFFERS
;
429 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
430 struct gl_texture_unit
*texUnit
= &brw
->attribs
.Texture
->Unit
[i
];
432 /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
433 if(texUnit
->_ReallyEnabled
) {
434 if (texUnit
->_Current
== intel
->frame_buffer_texobj
) {
435 dri_bo_unreference(brw
->wm
.surf_bo
[i
+MAX_DRAW_BUFFERS
]);
436 brw
->wm
.surf_bo
[i
+MAX_DRAW_BUFFERS
] = brw
->wm
.surf_bo
[0];
437 dri_bo_reference(brw
->wm
.surf_bo
[i
+MAX_DRAW_BUFFERS
]);
438 brw
->wm
.nr_surfaces
= i
+ MAX_DRAW_BUFFERS
+ 1;
440 ret
= brw_update_texture_surface(ctx
, i
);
441 brw
->wm
.nr_surfaces
= i
+ MAX_DRAW_BUFFERS
+ 1;
447 dri_bo_unreference(brw
->wm
.surf_bo
[i
+MAX_DRAW_BUFFERS
]);
448 brw
->wm
.surf_bo
[i
+MAX_DRAW_BUFFERS
] = NULL
;
453 dri_bo_unreference(brw
->wm
.bind_bo
);
454 brw
->wm
.bind_bo
= brw_wm_get_binding_table(brw
);
456 return dri_bufmgr_check_aperture_space(brw
->wm
.bind_bo
);
460 const struct brw_tracked_state brw_wm_surfaces
= {
462 .mesa
= _NEW_COLOR
| _NEW_TEXTURE
| _NEW_BUFFERS
,
463 .brw
= BRW_NEW_CONTEXT
,
466 .prepare
= prepare_wm_surfaces
,