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i965: Account for offsets when updating SURFACE_STATE.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/context.h"
34 #include "main/mtypes.h"
35 #include "main/samplerobj.h"
36 #include "program/prog_parameter.h"
37
38 #include "intel_mipmap_tree.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_fbo.h"
42 #include "intel_buffer_objects.h"
43
44 #include "brw_context.h"
45 #include "brw_state.h"
46 #include "brw_defines.h"
47 #include "brw_wm.h"
48
49 GLuint
50 translate_tex_target(GLenum target)
51 {
52 switch (target) {
53 case GL_TEXTURE_1D:
54 case GL_TEXTURE_1D_ARRAY_EXT:
55 return BRW_SURFACE_1D;
56
57 case GL_TEXTURE_RECTANGLE_NV:
58 return BRW_SURFACE_2D;
59
60 case GL_TEXTURE_2D:
61 case GL_TEXTURE_2D_ARRAY_EXT:
62 case GL_TEXTURE_EXTERNAL_OES:
63 return BRW_SURFACE_2D;
64
65 case GL_TEXTURE_3D:
66 return BRW_SURFACE_3D;
67
68 case GL_TEXTURE_CUBE_MAP:
69 case GL_TEXTURE_CUBE_MAP_ARRAY:
70 return BRW_SURFACE_CUBE;
71
72 default:
73 assert(0);
74 return 0;
75 }
76 }
77
78 struct surface_format_info {
79 bool exists;
80 int sampling;
81 int filtering;
82 int shadow_compare;
83 int chroma_key;
84 int render_target;
85 int alpha_blend;
86 int input_vb;
87 int streamed_output_vb;
88 int color_processing;
89 };
90
91 /* This macro allows us to write the table almost as it appears in the PRM,
92 * while restructuring it to turn it into the C code we want.
93 */
94 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
95 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
96
97 #define Y 0
98 #define x 999
99 /**
100 * This is the table of support for surface (texture, renderbuffer, and vertex
101 * buffer, but not depthbuffer) formats across the various hardware generations.
102 *
103 * The table is formatted to match the documentation, except that the docs have
104 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put
105 * it in our table, here's the mapping:
106 *
107 * Y*: 45
108 * Y+: 45 (g45/gm45)
109 * Y~: 50 (gen5)
110 * Y^: 60 (gen6)
111 * Y#: 70 (gen7)
112 *
113 * The abbreviations in the header below are:
114 * smpl - Sampling Engine
115 * filt - Sampling Engine Filtering
116 * shad - Sampling Engine Shadow Map
117 * CK - Sampling Engine Chroma Key
118 * RT - Render Target
119 * AB - Alpha Blend Render Target
120 * VB - Input Vertex Buffer
121 * SO - Steamed Output Vertex Buffers (transform feedback)
122 * color - Color Processing
123 *
124 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
125 */
126 const struct surface_format_info surface_formats[] = {
127 /* smpl filt shad CK RT AB VB SO color */
128 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
129 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
130 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
131 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
132 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
133 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT)
134 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
135 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
136 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
137 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
138 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT)
139 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT)
140 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
141 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
144 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
145 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
146 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
147 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
148 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
149 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT)
150 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT)
151 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT)
152 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
153 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
154 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT)
155 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM)
156 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM)
157 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT)
158 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
159 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
160 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT)
161 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT)
162 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT)
163 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
164 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
165 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED)
166 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED)
167 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
168 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
169 /* smpl filt shad CK RT AB VB SO color */
170 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
171 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
172 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
173 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
174 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
175 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
176 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
177 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
178 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
179 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM)
180 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM)
181 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT)
182 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT)
183 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT)
184 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
185 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
186 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
187 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT)
188 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT)
189 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT)
190 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
191 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
192 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM)
193 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM)
194 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM)
195 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM)
196 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT)
197 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT)
198 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT)
199 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
200 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
201 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
202 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
203 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
204 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
205 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT)
206 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM)
207 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM)
208 /* smpl filt shad CK RT AB VB SO color */
209 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
210 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
211 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
212 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED)
213 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED)
214 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED)
215 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED)
216 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
217 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
218 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
219 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
220 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
221 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
222 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM)
223 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM)
224 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT)
225 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT)
226 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM)
227 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM)
228 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT)
229 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT)
230 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT)
231 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM)
232 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM)
233 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM)
234 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM)
235 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT)
236 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT)
237 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT)
238 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
239 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
240 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
241 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
242 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED)
243 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED)
244 /* smpl filt shad CK RT AB VB SO color */
245 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED)
246 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED)
247 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM)
248 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM)
249 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT)
250 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT)
251 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM)
252 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM)
253 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM)
254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM)
255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM)
256 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED)
257 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED)
258 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
259 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
260 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT)
261 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
262 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
263 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM)
264 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM)
265 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM)
266 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM)
267 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM)
268 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
269 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
271 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8)
272 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
273 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
274 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB)
275 /* smpl filt shad CK RT AB VB SO color */
276 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1)
277 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
278 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
279 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
280 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
281 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
282 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
283 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
284 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
285 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
286 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
287 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
288 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
289 };
290 #undef x
291 #undef Y
292
293 uint32_t
294 brw_format_for_mesa_format(gl_format mesa_format)
295 {
296 /* This table is ordered according to the enum ordering in formats.h. We do
297 * expect that enum to be extended without our explicit initialization
298 * staying in sync, so we initialize to 0 even though
299 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
300 */
301 static const uint32_t table[MESA_FORMAT_COUNT] =
302 {
303 [MESA_FORMAT_RGBA8888] = 0,
304 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
305 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
306 [MESA_FORMAT_ARGB8888_REV] = 0,
307 [MESA_FORMAT_RGBX8888] = 0,
308 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
309 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
310 [MESA_FORMAT_XRGB8888_REV] = 0,
311 [MESA_FORMAT_RGB888] = 0,
312 [MESA_FORMAT_BGR888] = 0,
313 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
314 [MESA_FORMAT_RGB565_REV] = 0,
315 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
316 [MESA_FORMAT_ARGB4444_REV] = 0,
317 [MESA_FORMAT_RGBA5551] = 0,
318 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
319 [MESA_FORMAT_ARGB1555_REV] = 0,
320 [MESA_FORMAT_AL44] = 0,
321 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
322 [MESA_FORMAT_AL88_REV] = 0,
323 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
324 [MESA_FORMAT_AL1616_REV] = 0,
325 [MESA_FORMAT_RGB332] = 0,
326 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
327 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
328 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
329 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
330 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
331 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
332 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
333 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
334 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
335 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
336 [MESA_FORMAT_RG88] = 0,
337 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
338 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
339 [MESA_FORMAT_RG1616_REV] = 0,
340 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
341 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
342 [MESA_FORMAT_Z24_S8] = 0,
343 [MESA_FORMAT_S8_Z24] = 0,
344 [MESA_FORMAT_Z16] = 0,
345 [MESA_FORMAT_X8_Z24] = 0,
346 [MESA_FORMAT_Z24_X8] = 0,
347 [MESA_FORMAT_Z32] = 0,
348 [MESA_FORMAT_S8] = 0,
349
350 [MESA_FORMAT_SRGB8] = 0,
351 [MESA_FORMAT_SRGBA8] = 0,
352 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
353 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
354 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
355 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
356 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
357 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
358 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
359
360 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
361 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
362 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
363 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
364 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
365 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
366
367 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
368 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
369 [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
370 [MESA_FORMAT_RGB_FLOAT16] = 0,
371 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
372 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
373 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
374 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
375 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
376 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
377 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
378 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
379 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
380 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
381 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
382 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
383
384 [MESA_FORMAT_ALPHA_UINT8] = 0,
385 [MESA_FORMAT_ALPHA_UINT16] = 0,
386 [MESA_FORMAT_ALPHA_UINT32] = 0,
387 [MESA_FORMAT_ALPHA_INT8] = 0,
388 [MESA_FORMAT_ALPHA_INT16] = 0,
389 [MESA_FORMAT_ALPHA_INT32] = 0,
390
391 [MESA_FORMAT_INTENSITY_UINT8] = 0,
392 [MESA_FORMAT_INTENSITY_UINT16] = 0,
393 [MESA_FORMAT_INTENSITY_UINT32] = 0,
394 [MESA_FORMAT_INTENSITY_INT8] = 0,
395 [MESA_FORMAT_INTENSITY_INT16] = 0,
396 [MESA_FORMAT_INTENSITY_INT32] = 0,
397
398 [MESA_FORMAT_LUMINANCE_UINT8] = 0,
399 [MESA_FORMAT_LUMINANCE_UINT16] = 0,
400 [MESA_FORMAT_LUMINANCE_UINT32] = 0,
401 [MESA_FORMAT_LUMINANCE_INT8] = 0,
402 [MESA_FORMAT_LUMINANCE_INT16] = 0,
403 [MESA_FORMAT_LUMINANCE_INT32] = 0,
404
405 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
406 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
407 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
408 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
409 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
410 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
411
412 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
413 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
414 [MESA_FORMAT_RGB_INT8] = 0,
415 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
416 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
417 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
418 [MESA_FORMAT_RGB_INT16] = 0,
419 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
420 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
421 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
422 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
423 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
424
425 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
426 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
427 [MESA_FORMAT_RGB_UINT8] = 0,
428 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
429 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
430 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
431 [MESA_FORMAT_RGB_UINT16] = 0,
432 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
433 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
434 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
435 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
436 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
437
438 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
439 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
440 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
441 [MESA_FORMAT_SIGNED_RGBX8888] = 0,
442 [MESA_FORMAT_SIGNED_RGBA8888] = 0,
443 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
444 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
445 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
446 [MESA_FORMAT_SIGNED_RGB_16] = 0,
447 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
448 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
449
450 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
451 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
452 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
453 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
454
455 [MESA_FORMAT_L_LATC1] = 0,
456 [MESA_FORMAT_SIGNED_L_LATC1] = 0,
457 [MESA_FORMAT_LA_LATC2] = 0,
458 [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
459
460 [MESA_FORMAT_SIGNED_A8] = 0,
461 [MESA_FORMAT_SIGNED_L8] = 0,
462 [MESA_FORMAT_SIGNED_AL88] = 0,
463 [MESA_FORMAT_SIGNED_I8] = 0,
464 [MESA_FORMAT_SIGNED_A16] = 0,
465 [MESA_FORMAT_SIGNED_L16] = 0,
466 [MESA_FORMAT_SIGNED_AL1616] = 0,
467 [MESA_FORMAT_SIGNED_I16] = 0,
468
469 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
470 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
471
472 [MESA_FORMAT_Z32_FLOAT] = 0,
473 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
474 };
475 assert(mesa_format < MESA_FORMAT_COUNT);
476 return table[mesa_format];
477 }
478
479 void
480 brw_init_surface_formats(struct brw_context *brw)
481 {
482 struct intel_context *intel = &brw->intel;
483 struct gl_context *ctx = &intel->ctx;
484 int gen;
485 gl_format format;
486
487 gen = intel->gen * 10;
488 if (intel->is_g4x)
489 gen += 5;
490
491 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
492 uint32_t texture, render;
493 const struct surface_format_info *rinfo, *tinfo;
494 bool is_integer = _mesa_is_format_integer_color(format);
495
496 render = texture = brw_format_for_mesa_format(format);
497 tinfo = &surface_formats[texture];
498
499 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
500 * it.
501 */
502 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
503 continue;
504
505 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
506 ctx->TextureFormatSupported[format] = true;
507
508 /* Re-map some render target formats to make them supported when they
509 * wouldn't be using their format for texturing.
510 */
511 switch (render) {
512 /* For these formats, we just need to read/write the first
513 * channel into R, which is to say that we just treat them as
514 * GL_RED.
515 */
516 case BRW_SURFACEFORMAT_I32_FLOAT:
517 case BRW_SURFACEFORMAT_L32_FLOAT:
518 render = BRW_SURFACEFORMAT_R32_FLOAT;
519 break;
520 case BRW_SURFACEFORMAT_I16_FLOAT:
521 case BRW_SURFACEFORMAT_L16_FLOAT:
522 render = BRW_SURFACEFORMAT_R16_FLOAT;
523 break;
524 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
525 /* XRGB is handled as ARGB because the chips in this family
526 * cannot render to XRGB targets. This means that we have to
527 * mask writes to alpha (ala glColorMask) and reconfigure the
528 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
529 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
530 * used.
531 */
532 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
533 break;
534 }
535
536 rinfo = &surface_formats[render];
537
538 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
539 * integer, so we don't need hardware support for blending on it. Other
540 * than that, GL in general requires alpha blending for render targets,
541 * even though we don't support it for some formats.
542 */
543 if (gen >= rinfo->render_target &&
544 (gen >= rinfo->alpha_blend || is_integer)) {
545 brw->render_target_format[format] = render;
546 brw->format_supported_as_render_target[format] = true;
547 }
548 }
549
550 /* We will check this table for FBO completeness, but the surface format
551 * table above only covered color rendering.
552 */
553 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
554 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
555 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
556 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
557 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
558 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
559
560 /* We remap depth formats to a supported texturing format in
561 * translate_tex_format().
562 */
563 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
564 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
565 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
566 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
567 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
568
569 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
570 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
571 */
572 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
573
574 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
575 * MESA_FORMAT during glCompressedTexImage2D().
576 * See intel_mipmap_tree::wraps_etc2.
577 */
578 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
579 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
580 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
581 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
582 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
583 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
584 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
585 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
586 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
587 ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
588 }
589
590 bool
591 brw_render_target_supported(struct intel_context *intel,
592 struct gl_renderbuffer *rb)
593 {
594 struct brw_context *brw = brw_context(&intel->ctx);
595 gl_format format = rb->Format;
596
597 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
598 * we would consider them renderable even though we don't have surface
599 * support for their alpha behavior and don't have the blending unit
600 * available to fake it like we do for XRGB8888. Force them to being
601 * unsupported.
602 */
603 if ((rb->_BaseFormat != GL_RGBA &&
604 rb->_BaseFormat != GL_RG &&
605 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
606 return false;
607
608 /* Under some conditions, MSAA is not supported for formats whose width is
609 * more than 64 bits.
610 */
611 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
612 /* Gen6: MSAA on >64 bit formats is unsupported. */
613 if (intel->gen <= 6)
614 return false;
615
616 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
617 if (rb->NumSamples >= 8)
618 return false;
619 }
620
621 return brw->format_supported_as_render_target[format];
622 }
623
624 GLuint
625 translate_tex_format(gl_format mesa_format,
626 GLenum internal_format,
627 GLenum depth_mode,
628 GLenum srgb_decode)
629 {
630 if (srgb_decode == GL_SKIP_DECODE_EXT)
631 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
632
633 switch( mesa_format ) {
634
635 case MESA_FORMAT_Z16:
636 return BRW_SURFACEFORMAT_I16_UNORM;
637
638 case MESA_FORMAT_S8_Z24:
639 case MESA_FORMAT_X8_Z24:
640 return BRW_SURFACEFORMAT_I24X8_UNORM;
641
642 case MESA_FORMAT_Z32_FLOAT:
643 return BRW_SURFACEFORMAT_I32_FLOAT;
644
645 case MESA_FORMAT_Z32_FLOAT_X24S8:
646 return BRW_SURFACEFORMAT_R32G32_FLOAT;
647
648 case MESA_FORMAT_RGBA_FLOAT32:
649 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
650 * assertion below.
651 */
652 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
653
654 default:
655 assert(brw_format_for_mesa_format(mesa_format) != 0);
656 return brw_format_for_mesa_format(mesa_format);
657 }
658 }
659
660 uint32_t
661 brw_get_surface_tiling_bits(uint32_t tiling)
662 {
663 switch (tiling) {
664 case I915_TILING_X:
665 return BRW_SURFACE_TILED;
666 case I915_TILING_Y:
667 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
668 default:
669 return 0;
670 }
671 }
672
673
674 uint32_t
675 brw_get_surface_num_multisamples(unsigned num_samples)
676 {
677 if (num_samples > 1)
678 return BRW_SURFACE_MULTISAMPLECOUNT_4;
679 else
680 return BRW_SURFACE_MULTISAMPLECOUNT_1;
681 }
682
683
684 /**
685 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
686 * swizzling.
687 */
688 int
689 brw_get_texture_swizzle(const struct gl_context *ctx,
690 const struct gl_texture_object *t)
691 {
692 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
693
694 int swizzles[SWIZZLE_NIL + 1] = {
695 SWIZZLE_X,
696 SWIZZLE_Y,
697 SWIZZLE_Z,
698 SWIZZLE_W,
699 SWIZZLE_ZERO,
700 SWIZZLE_ONE,
701 SWIZZLE_NIL
702 };
703
704 if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
705 img->_BaseFormat == GL_DEPTH_STENCIL) {
706 GLenum depth_mode = t->DepthMode;
707
708 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
709 * with depth component data specified with a sized internal format.
710 * Otherwise, it's left at the old default, GL_LUMINANCE.
711 */
712 if (_mesa_is_gles3(ctx) &&
713 img->InternalFormat != GL_DEPTH_COMPONENT &&
714 img->InternalFormat != GL_DEPTH_STENCIL) {
715 depth_mode = GL_RED;
716 }
717
718 switch (depth_mode) {
719 case GL_ALPHA:
720 swizzles[0] = SWIZZLE_ZERO;
721 swizzles[1] = SWIZZLE_ZERO;
722 swizzles[2] = SWIZZLE_ZERO;
723 swizzles[3] = SWIZZLE_X;
724 break;
725 case GL_LUMINANCE:
726 swizzles[0] = SWIZZLE_X;
727 swizzles[1] = SWIZZLE_X;
728 swizzles[2] = SWIZZLE_X;
729 swizzles[3] = SWIZZLE_ONE;
730 break;
731 case GL_INTENSITY:
732 swizzles[0] = SWIZZLE_X;
733 swizzles[1] = SWIZZLE_X;
734 swizzles[2] = SWIZZLE_X;
735 swizzles[3] = SWIZZLE_X;
736 break;
737 case GL_RED:
738 swizzles[0] = SWIZZLE_X;
739 swizzles[1] = SWIZZLE_ZERO;
740 swizzles[2] = SWIZZLE_ZERO;
741 swizzles[3] = SWIZZLE_ONE;
742 break;
743 }
744 }
745
746 /* If the texture's format is alpha-only, force R, G, and B to
747 * 0.0. Similarly, if the texture's format has no alpha channel,
748 * force the alpha value read to 1.0. This allows for the
749 * implementation to use an RGBA texture for any of these formats
750 * without leaking any unexpected values.
751 */
752 switch (img->_BaseFormat) {
753 case GL_ALPHA:
754 swizzles[0] = SWIZZLE_ZERO;
755 swizzles[1] = SWIZZLE_ZERO;
756 swizzles[2] = SWIZZLE_ZERO;
757 break;
758 case GL_RED:
759 case GL_RG:
760 case GL_RGB:
761 swizzles[3] = SWIZZLE_ONE;
762 break;
763 }
764
765 return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
766 swizzles[GET_SWZ(t->_Swizzle, 1)],
767 swizzles[GET_SWZ(t->_Swizzle, 2)],
768 swizzles[GET_SWZ(t->_Swizzle, 3)]);
769 }
770
771
772 static void
773 brw_update_buffer_texture_surface(struct gl_context *ctx,
774 unsigned unit,
775 uint32_t *binding_table,
776 unsigned surf_index)
777 {
778 struct brw_context *brw = brw_context(ctx);
779 struct intel_context *intel = &brw->intel;
780 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
781 uint32_t *surf;
782 struct intel_buffer_object *intel_obj =
783 intel_buffer_object(tObj->BufferObject);
784 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
785 gl_format format = tObj->_BufferObjectFormat;
786 uint32_t brw_format = brw_format_for_mesa_format(format);
787 int texel_size = _mesa_get_format_bytes(format);
788
789 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
790 _mesa_problem(NULL, "bad format %s for texture buffer\n",
791 _mesa_get_format_name(format));
792 }
793
794 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
795 6 * 4, 32, &binding_table[surf_index]);
796
797 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
798 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
799
800 if (intel->gen >= 6)
801 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
802
803 if (bo) {
804 surf[1] = bo->offset; /* reloc */
805
806 /* Emit relocation to surface contents. */
807 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
808 binding_table[surf_index] + 4,
809 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
810
811 int w = intel_obj->Base.Size / texel_size;
812 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
813 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
814 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
815 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
816 } else {
817 surf[1] = 0;
818 surf[2] = 0;
819 surf[3] = 0;
820 }
821
822 surf[4] = 0;
823 surf[5] = 0;
824 }
825
826 static void
827 brw_update_texture_surface(struct gl_context *ctx,
828 unsigned unit,
829 uint32_t *binding_table,
830 unsigned surf_index)
831 {
832 struct brw_context *brw = brw_context(ctx);
833 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
834 struct intel_texture_object *intelObj = intel_texture_object(tObj);
835 struct intel_mipmap_tree *mt = intelObj->mt;
836 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
837 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
838 uint32_t *surf;
839 int width, height, depth;
840 uint32_t tile_x, tile_y;
841
842 if (tObj->Target == GL_TEXTURE_BUFFER) {
843 brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
844 return;
845 }
846
847 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
848
849 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
850 6 * 4, 32, &binding_table[surf_index]);
851
852 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
853 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
854 BRW_SURFACE_CUBEFACE_ENABLES |
855 (translate_tex_format(mt->format,
856 firstImage->InternalFormat,
857 tObj->DepthMode,
858 sampler->sRGBDecode) <<
859 BRW_SURFACE_FORMAT_SHIFT));
860
861 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
862
863 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
864 (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
865 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
866
867 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
868 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
869 (intelObj->mt->region->pitch - 1) <<
870 BRW_SURFACE_PITCH_SHIFT);
871
872 surf[4] = 0;
873
874 intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y);
875 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
876 /* Note that the low bits of these fields are missing, so
877 * there's the possibility of getting in trouble.
878 */
879 assert(tile_x % 4 == 0);
880 assert(tile_y % 2 == 0);
881 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
882 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
883 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
884
885 /* Emit relocation to surface contents */
886 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
887 binding_table[surf_index] + 4,
888 intelObj->mt->region->bo,
889 intelObj->mt->offset,
890 I915_GEM_DOMAIN_SAMPLER, 0);
891 }
892
893 /**
894 * Create the constant buffer surface. Vertex/fragment shader constants will be
895 * read from this buffer with Data Port Read instructions/messages.
896 */
897 void
898 brw_create_constant_surface(struct brw_context *brw,
899 drm_intel_bo *bo,
900 uint32_t offset,
901 int width,
902 uint32_t *out_offset)
903 {
904 struct intel_context *intel = &brw->intel;
905 const GLint w = width - 1;
906 uint32_t *surf;
907
908 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
909 6 * 4, 32, out_offset);
910
911 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
912 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
913 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
914
915 if (intel->gen >= 6)
916 surf[0] |= BRW_SURFACE_RC_READ_WRITE;
917
918 surf[1] = bo->offset + offset; /* reloc */
919
920 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
921 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
922
923 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
924 (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
925
926 surf[4] = 0;
927 surf[5] = 0;
928
929 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
930 * bspec ("Data Cache") says that the data cache does not exist as
931 * a separate cache and is just the sampler cache.
932 */
933 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
934 *out_offset + 4,
935 bo, offset,
936 I915_GEM_DOMAIN_SAMPLER, 0);
937 }
938
939 /**
940 * Set up a binding table entry for use by stream output logic (transform
941 * feedback).
942 *
943 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
944 */
945 void
946 brw_update_sol_surface(struct brw_context *brw,
947 struct gl_buffer_object *buffer_obj,
948 uint32_t *out_offset, unsigned num_vector_components,
949 unsigned stride_dwords, unsigned offset_dwords)
950 {
951 struct intel_context *intel = &brw->intel;
952 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
953 drm_intel_bo *bo =
954 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
955 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
956 out_offset);
957 uint32_t pitch_minus_1 = 4*stride_dwords - 1;
958 uint32_t offset_bytes = 4 * offset_dwords;
959 size_t size_dwords = buffer_obj->Size / 4;
960 uint32_t buffer_size_minus_1, width, height, depth, surface_format;
961
962 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
963 * too big to map using a single binding table entry?
964 */
965 assert((size_dwords - offset_dwords) / stride_dwords
966 <= BRW_MAX_NUM_BUFFER_ENTRIES);
967
968 if (size_dwords > offset_dwords + num_vector_components) {
969 /* There is room for at least 1 transform feedback output in the buffer.
970 * Compute the number of additional transform feedback outputs the
971 * buffer has room for.
972 */
973 buffer_size_minus_1 =
974 (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
975 } else {
976 /* There isn't even room for a single transform feedback output in the
977 * buffer. We can't configure the binding table entry to prevent output
978 * entirely; we'll have to rely on the geometry shader to detect
979 * overflow. But to minimize the damage in case of a bug, set up the
980 * binding table entry to just allow a single output.
981 */
982 buffer_size_minus_1 = 0;
983 }
984 width = buffer_size_minus_1 & 0x7f;
985 height = (buffer_size_minus_1 & 0xfff80) >> 7;
986 depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
987
988 switch (num_vector_components) {
989 case 1:
990 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
991 break;
992 case 2:
993 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
994 break;
995 case 3:
996 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
997 break;
998 case 4:
999 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
1000 break;
1001 default:
1002 assert(!"Invalid vector size for transform feedback output");
1003 surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1004 break;
1005 }
1006
1007 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1008 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1009 surface_format << BRW_SURFACE_FORMAT_SHIFT |
1010 BRW_SURFACE_RC_READ_WRITE;
1011 surf[1] = bo->offset + offset_bytes; /* reloc */
1012 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
1013 height << BRW_SURFACE_HEIGHT_SHIFT);
1014 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1015 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1016 surf[4] = 0;
1017 surf[5] = 0;
1018
1019 /* Emit relocation to surface contents. */
1020 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1021 *out_offset + 4,
1022 bo, offset_bytes,
1023 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1024 }
1025
1026 /* Creates a new WM constant buffer reflecting the current fragment program's
1027 * constants, if needed by the fragment program.
1028 *
1029 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
1030 * state atom.
1031 */
1032 static void
1033 brw_upload_wm_pull_constants(struct brw_context *brw)
1034 {
1035 struct gl_context *ctx = &brw->intel.ctx;
1036 struct intel_context *intel = &brw->intel;
1037 /* BRW_NEW_FRAGMENT_PROGRAM */
1038 struct brw_fragment_program *fp =
1039 (struct brw_fragment_program *) brw->fragment_program;
1040 struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1041 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1042 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1043 float *constants;
1044 unsigned int i;
1045
1046 _mesa_load_state_parameters(ctx, params);
1047
1048 /* CACHE_NEW_WM_PROG */
1049 if (brw->wm.prog_data->nr_pull_params == 0) {
1050 if (brw->wm.const_bo) {
1051 drm_intel_bo_unreference(brw->wm.const_bo);
1052 brw->wm.const_bo = NULL;
1053 brw->wm.surf_offset[surf_index] = 0;
1054 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1055 }
1056 return;
1057 }
1058
1059 drm_intel_bo_unreference(brw->wm.const_bo);
1060 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1061 size, 64);
1062
1063 /* _NEW_PROGRAM_CONSTANTS */
1064 drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1065 constants = brw->wm.const_bo->virtual;
1066 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1067 constants[i] = *brw->wm.prog_data->pull_param[i];
1068 }
1069 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1070
1071 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1072 ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4,
1073 &brw->wm.surf_offset[surf_index]);
1074
1075 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1076 }
1077
1078 const struct brw_tracked_state brw_wm_pull_constants = {
1079 .dirty = {
1080 .mesa = (_NEW_PROGRAM_CONSTANTS),
1081 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1082 .cache = CACHE_NEW_WM_PROG,
1083 },
1084 .emit = brw_upload_wm_pull_constants,
1085 };
1086
1087 static void
1088 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1089 {
1090 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1091 * Notes):
1092 *
1093 * A null surface will be used in instances where an actual surface is
1094 * not bound. When a write message is generated to a null surface, no
1095 * actual surface is written to. When a read message (including any
1096 * sampling engine message) is generated to a null surface, the result
1097 * is all zeros. Note that a null surface type is allowed to be used
1098 * with all messages, even if it is not specificially indicated as
1099 * supported. All of the remaining fields in surface state are ignored
1100 * for null surfaces, with the following exceptions:
1101 *
1102 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1103 * depth buffer’s corresponding state for all render target surfaces,
1104 * including null.
1105 *
1106 * - Surface Format must be R8G8B8A8_UNORM.
1107 */
1108 struct intel_context *intel = &brw->intel;
1109 struct gl_context *ctx = &intel->ctx;
1110 uint32_t *surf;
1111 unsigned surface_type = BRW_SURFACE_NULL;
1112 drm_intel_bo *bo = NULL;
1113 unsigned pitch_minus_1 = 0;
1114 uint32_t multisampling_state = 0;
1115
1116 /* _NEW_BUFFERS */
1117 const struct gl_framebuffer *fb = ctx->DrawBuffer;
1118
1119 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1120 6 * 4, 32, &brw->wm.surf_offset[unit]);
1121
1122 if (fb->Visual.samples > 1) {
1123 /* On Gen6, null render targets seem to cause GPU hangs when
1124 * multisampling. So work around this problem by rendering into dummy
1125 * color buffer.
1126 *
1127 * To decrease the amount of memory needed by the workaround buffer, we
1128 * set its pitch to 128 bytes (the width of a Y tile). This means that
1129 * the amount of memory needed for the workaround buffer is
1130 * (width_in_tiles + height_in_tiles - 1) tiles.
1131 *
1132 * Note that since the workaround buffer will be interpreted by the
1133 * hardware as an interleaved multisampled buffer, we need to compute
1134 * width_in_tiles and height_in_tiles by dividing the width and height
1135 * by 16 rather than the normal Y-tile size of 32.
1136 */
1137 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1138 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1139 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1140 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1141 size_needed);
1142 bo = brw->wm.multisampled_null_render_target_bo;
1143 surface_type = BRW_SURFACE_2D;
1144 pitch_minus_1 = 127;
1145 multisampling_state =
1146 brw_get_surface_num_multisamples(fb->Visual.samples);
1147 }
1148
1149 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1150 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1151 if (intel->gen < 6) {
1152 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1153 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1154 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1155 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1156 }
1157 surf[1] = bo ? bo->offset : 0;
1158 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1159 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1160
1161 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1162 * Notes):
1163 *
1164 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
1165 */
1166 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1167 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1168 surf[4] = multisampling_state;
1169 surf[5] = 0;
1170
1171 if (bo) {
1172 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1173 brw->wm.surf_offset[unit] + 4,
1174 bo, 0,
1175 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1176 }
1177 }
1178
1179 /**
1180 * Sets up a surface state structure to point at the given region.
1181 * While it is only used for the front/back buffer currently, it should be
1182 * usable for further buffers when doing ARB_draw_buffer support.
1183 */
1184 static void
1185 brw_update_renderbuffer_surface(struct brw_context *brw,
1186 struct gl_renderbuffer *rb,
1187 unsigned int unit)
1188 {
1189 struct intel_context *intel = &brw->intel;
1190 struct gl_context *ctx = &intel->ctx;
1191 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1192 struct intel_mipmap_tree *mt = irb->mt;
1193 struct intel_region *region;
1194 uint32_t *surf;
1195 uint32_t tile_x, tile_y;
1196 uint32_t format = 0;
1197 gl_format rb_format = intel_rb_format(irb);
1198
1199 if (irb->tex_image && !brw->has_surface_tile_offset) {
1200 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1201
1202 if (tile_x != 0 || tile_y != 0) {
1203 /* Original gen4 hardware couldn't draw to a non-tile-aligned
1204 * destination in a miptree unless you actually setup your renderbuffer
1205 * as a miptree and used the fragile lod/array_index/etc. controls to
1206 * select the image. So, instead, we just make a new single-level
1207 * miptree and render into that.
1208 */
1209 intel_renderbuffer_move_to_temp(intel, irb);
1210 mt = irb->mt;
1211 }
1212 }
1213
1214 region = irb->mt->region;
1215
1216 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1217 6 * 4, 32, &brw->wm.surf_offset[unit]);
1218
1219 switch (rb_format) {
1220 case MESA_FORMAT_SARGB8:
1221 /* _NEW_BUFFERS
1222 *
1223 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1224 * blend/update as sRGB.
1225 */
1226 if (ctx->Color.sRGBEnabled)
1227 format = brw_format_for_mesa_format(rb_format);
1228 else
1229 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1230 break;
1231 default:
1232 format = brw->render_target_format[rb_format];
1233 if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1234 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1235 __FUNCTION__, _mesa_get_format_name(rb_format));
1236 }
1237 break;
1238 }
1239
1240 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1241 format << BRW_SURFACE_FORMAT_SHIFT);
1242
1243 /* reloc */
1244 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1245 region->bo->offset);
1246
1247 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1248 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1249
1250 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1251 (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1252
1253 surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1254
1255 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1256 /* Note that the low bits of these fields are missing, so
1257 * there's the possibility of getting in trouble.
1258 */
1259 assert(tile_x % 4 == 0);
1260 assert(tile_y % 2 == 0);
1261 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1262 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1263 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1264
1265 if (intel->gen < 6) {
1266 /* _NEW_COLOR */
1267 if (!ctx->Color.ColorLogicOpEnabled &&
1268 (ctx->Color.BlendEnabled & (1 << unit)))
1269 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1270
1271 if (!ctx->Color.ColorMask[unit][0])
1272 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1273 if (!ctx->Color.ColorMask[unit][1])
1274 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1275 if (!ctx->Color.ColorMask[unit][2])
1276 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1277
1278 /* As mentioned above, disable writes to the alpha component when the
1279 * renderbuffer is XRGB.
1280 */
1281 if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1282 !ctx->Color.ColorMask[unit][3]) {
1283 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1284 }
1285 }
1286
1287 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1288 brw->wm.surf_offset[unit] + 4,
1289 region->bo,
1290 surf[1] - region->bo->offset,
1291 I915_GEM_DOMAIN_RENDER,
1292 I915_GEM_DOMAIN_RENDER);
1293 }
1294
1295 /**
1296 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1297 */
1298 static void
1299 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1300 {
1301 struct intel_context *intel = &brw->intel;
1302 struct gl_context *ctx = &brw->intel.ctx;
1303 GLuint i;
1304
1305 /* _NEW_BUFFERS | _NEW_COLOR */
1306 /* Update surfaces for drawing buffers */
1307 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1308 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1309 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1310 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1311 } else {
1312 intel->vtbl.update_null_renderbuffer_surface(brw, i);
1313 }
1314 }
1315 } else {
1316 intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1317 }
1318 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1319 }
1320
1321 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1322 .dirty = {
1323 .mesa = (_NEW_COLOR |
1324 _NEW_BUFFERS),
1325 .brw = BRW_NEW_BATCH,
1326 .cache = 0
1327 },
1328 .emit = brw_update_renderbuffer_surfaces,
1329 };
1330
1331 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1332 .dirty = {
1333 .mesa = _NEW_BUFFERS,
1334 .brw = BRW_NEW_BATCH,
1335 .cache = 0
1336 },
1337 .emit = brw_update_renderbuffer_surfaces,
1338 };
1339
1340 /**
1341 * Construct SURFACE_STATE objects for enabled textures.
1342 */
1343 static void
1344 brw_update_texture_surfaces(struct brw_context *brw)
1345 {
1346 struct intel_context *intel = &brw->intel;
1347 struct gl_context *ctx = &intel->ctx;
1348
1349 /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1350 * Unfortunately, we're stuck using the gl_program structs until the
1351 * ARB_fragment_program front-end gets converted to GLSL IR. These
1352 * have the downside that SamplerUnits is split and only contains the
1353 * mappings for samplers active in that stage.
1354 */
1355 struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1356 struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1357
1358 unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1359
1360 for (unsigned s = 0; s < num_samplers; s++) {
1361 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1362 brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1363
1364 if (vs->SamplersUsed & (1 << s)) {
1365 const unsigned unit = vs->SamplerUnits[s];
1366
1367 /* _NEW_TEXTURE */
1368 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1369 intel->vtbl.update_texture_surface(ctx, unit,
1370 brw->vs.surf_offset,
1371 SURF_INDEX_VS_TEXTURE(s));
1372 }
1373 }
1374
1375 if (fs->SamplersUsed & (1 << s)) {
1376 const unsigned unit = fs->SamplerUnits[s];
1377
1378 /* _NEW_TEXTURE */
1379 if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1380 intel->vtbl.update_texture_surface(ctx, unit,
1381 brw->wm.surf_offset,
1382 SURF_INDEX_TEXTURE(s));
1383 }
1384 }
1385 }
1386
1387 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1388 }
1389
1390 const struct brw_tracked_state brw_texture_surfaces = {
1391 .dirty = {
1392 .mesa = _NEW_TEXTURE,
1393 .brw = BRW_NEW_BATCH |
1394 BRW_NEW_VERTEX_PROGRAM |
1395 BRW_NEW_FRAGMENT_PROGRAM,
1396 .cache = 0
1397 },
1398 .emit = brw_update_texture_surfaces,
1399 };
1400
1401 void
1402 brw_upload_ubo_surfaces(struct brw_context *brw,
1403 struct gl_shader *shader,
1404 uint32_t *surf_offsets)
1405 {
1406 struct gl_context *ctx = &brw->intel.ctx;
1407 struct intel_context *intel = &brw->intel;
1408
1409 if (!shader)
1410 return;
1411
1412 for (int i = 0; i < shader->NumUniformBlocks; i++) {
1413 struct gl_uniform_buffer_binding *binding;
1414 struct intel_buffer_object *intel_bo;
1415
1416 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1417 intel_bo = intel_buffer_object(binding->BufferObject);
1418 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1419
1420 /* Because behavior for referencing outside of the binding's size in the
1421 * glBindBufferRange case is undefined, we can just bind the whole buffer
1422 * glBindBufferBase wants and be a correct implementation.
1423 */
1424 int size = bo->size - binding->Offset;
1425 size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1426
1427 intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1428 size,
1429 &surf_offsets[i]);
1430 }
1431
1432 if (shader->NumUniformBlocks)
1433 brw->state.dirty.brw |= BRW_NEW_SURFACES;
1434 }
1435
1436 static void
1437 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1438 {
1439 struct gl_context *ctx = &brw->intel.ctx;
1440 /* _NEW_PROGRAM */
1441 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1442
1443 if (!prog)
1444 return;
1445
1446 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1447 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1448 }
1449
1450 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1451 .dirty = {
1452 .mesa = (_NEW_PROGRAM |
1453 _NEW_BUFFER_OBJECT),
1454 .brw = BRW_NEW_BATCH,
1455 .cache = 0,
1456 },
1457 .emit = brw_upload_wm_ubo_surfaces,
1458 };
1459
1460 /**
1461 * Constructs the binding table for the WM surface state, which maps unit
1462 * numbers to surface state objects.
1463 */
1464 static void
1465 brw_upload_wm_binding_table(struct brw_context *brw)
1466 {
1467 struct intel_context *intel = &brw->intel;
1468 uint32_t *bind;
1469 int i;
1470
1471 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1472 intel->vtbl.create_constant_surface(brw, brw->shader_time.bo, 0,
1473 brw->shader_time.bo->size,
1474 &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1475 }
1476
1477 /* Might want to calculate nr_surfaces first, to avoid taking up so much
1478 * space for the binding table.
1479 */
1480 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1481 sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1482 32, &brw->wm.bind_bo_offset);
1483
1484 /* BRW_NEW_SURFACES */
1485 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1486 bind[i] = brw->wm.surf_offset[i];
1487 }
1488
1489 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1490 }
1491
1492 const struct brw_tracked_state brw_wm_binding_table = {
1493 .dirty = {
1494 .mesa = 0,
1495 .brw = (BRW_NEW_BATCH |
1496 BRW_NEW_SURFACES),
1497 .cache = 0
1498 },
1499 .emit = brw_upload_wm_binding_table,
1500 };
1501
1502 void
1503 gen4_init_vtable_surface_functions(struct brw_context *brw)
1504 {
1505 struct intel_context *intel = &brw->intel;
1506
1507 intel->vtbl.update_texture_surface = brw_update_texture_surface;
1508 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1509 intel->vtbl.update_null_renderbuffer_surface =
1510 brw_update_null_renderbuffer_surface;
1511 intel->vtbl.create_constant_surface = brw_create_constant_surface;
1512 }