2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/samplerobj.h"
35 #include "program/prog_parameter.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
48 translate_tex_target(GLenum target
)
52 case GL_TEXTURE_1D_ARRAY_EXT
:
53 return BRW_SURFACE_1D
;
55 case GL_TEXTURE_RECTANGLE_NV
:
56 return BRW_SURFACE_2D
;
59 case GL_TEXTURE_2D_ARRAY_EXT
:
60 return BRW_SURFACE_2D
;
63 return BRW_SURFACE_3D
;
65 case GL_TEXTURE_CUBE_MAP
:
66 return BRW_SURFACE_CUBE
;
75 brw_format_for_mesa_format(gl_format mesa_format
)
77 static const uint32_t table
[MESA_FORMAT_COUNT
] =
79 [MESA_FORMAT_L8
] = BRW_SURFACEFORMAT_L8_UNORM
,
80 [MESA_FORMAT_I8
] = BRW_SURFACEFORMAT_I8_UNORM
,
81 [MESA_FORMAT_A8
] = BRW_SURFACEFORMAT_A8_UNORM
,
82 [MESA_FORMAT_AL88
] = BRW_SURFACEFORMAT_L8A8_UNORM
,
83 [MESA_FORMAT_L16
] = BRW_SURFACEFORMAT_L16_UNORM
,
84 [MESA_FORMAT_A16
] = BRW_SURFACEFORMAT_A16_UNORM
,
85 [MESA_FORMAT_I16
] = BRW_SURFACEFORMAT_I16_UNORM
,
86 [MESA_FORMAT_AL1616
] = BRW_SURFACEFORMAT_L16A16_UNORM
,
87 [MESA_FORMAT_R8
] = BRW_SURFACEFORMAT_R8_UNORM
,
88 [MESA_FORMAT_R16
] = BRW_SURFACEFORMAT_R16_UNORM
,
89 [MESA_FORMAT_RG88
] = BRW_SURFACEFORMAT_R8G8_UNORM
,
90 [MESA_FORMAT_RG1616
] = BRW_SURFACEFORMAT_R16G16_UNORM
,
91 [MESA_FORMAT_ARGB8888
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM
,
92 [MESA_FORMAT_XRGB8888
] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM
,
93 [MESA_FORMAT_RGB565
] = BRW_SURFACEFORMAT_B5G6R5_UNORM
,
94 [MESA_FORMAT_ARGB1555
] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM
,
95 [MESA_FORMAT_ARGB4444
] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM
,
96 [MESA_FORMAT_YCBCR_REV
] = BRW_SURFACEFORMAT_YCRCB_NORMAL
,
97 [MESA_FORMAT_YCBCR
] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY
,
98 [MESA_FORMAT_RGB_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
99 [MESA_FORMAT_RGBA_FXT1
] = BRW_SURFACEFORMAT_FXT1
,
100 [MESA_FORMAT_RGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB
,
101 [MESA_FORMAT_RGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM
,
102 [MESA_FORMAT_RGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM
,
103 [MESA_FORMAT_RGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM
,
104 [MESA_FORMAT_SRGB_DXT1
] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB
,
105 [MESA_FORMAT_SRGBA_DXT1
] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB
,
106 [MESA_FORMAT_SRGBA_DXT3
] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB
,
107 [MESA_FORMAT_SRGBA_DXT5
] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB
,
108 [MESA_FORMAT_SARGB8
] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB
,
109 [MESA_FORMAT_SLA8
] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB
,
110 [MESA_FORMAT_SL8
] = BRW_SURFACEFORMAT_L8_UNORM_SRGB
,
111 [MESA_FORMAT_DUDV8
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
112 [MESA_FORMAT_SIGNED_R8
] = BRW_SURFACEFORMAT_R8_SNORM
,
113 [MESA_FORMAT_SIGNED_RG88_REV
] = BRW_SURFACEFORMAT_R8G8_SNORM
,
114 [MESA_FORMAT_SIGNED_RGBA8888_REV
] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM
,
115 [MESA_FORMAT_SIGNED_R16
] = BRW_SURFACEFORMAT_R16_SNORM
,
116 [MESA_FORMAT_SIGNED_GR1616
] = BRW_SURFACEFORMAT_R16G16_SNORM
,
117 [MESA_FORMAT_RGBA_FLOAT32
] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
118 [MESA_FORMAT_RG_FLOAT32
] = BRW_SURFACEFORMAT_R32G32_FLOAT
,
119 [MESA_FORMAT_R_FLOAT32
] = BRW_SURFACEFORMAT_R32_FLOAT
,
120 [MESA_FORMAT_INTENSITY_FLOAT32
] = BRW_SURFACEFORMAT_I32_FLOAT
,
121 [MESA_FORMAT_LUMINANCE_FLOAT32
] = BRW_SURFACEFORMAT_L32_FLOAT
,
122 [MESA_FORMAT_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_A32_FLOAT
,
123 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
] = BRW_SURFACEFORMAT_L32A32_FLOAT
,
124 [MESA_FORMAT_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_UNORM
,
125 [MESA_FORMAT_SIGNED_RED_RGTC1
] = BRW_SURFACEFORMAT_BC4_SNORM
,
126 [MESA_FORMAT_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_UNORM
,
127 [MESA_FORMAT_SIGNED_RG_RGTC2
] = BRW_SURFACEFORMAT_BC5_SNORM
,
128 [MESA_FORMAT_RGB9_E5_FLOAT
] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP
,
129 [MESA_FORMAT_R11_G11_B10_FLOAT
] = BRW_SURFACEFORMAT_R11G11B10_FLOAT
,
131 [MESA_FORMAT_R_INT32
] = BRW_SURFACEFORMAT_R32_SINT
,
132 [MESA_FORMAT_RG_INT32
] = BRW_SURFACEFORMAT_R32G32_SINT
,
133 [MESA_FORMAT_RGB_INT32
] = BRW_SURFACEFORMAT_R32G32B32_SINT
,
134 [MESA_FORMAT_RGBA_INT32
] = BRW_SURFACEFORMAT_R32G32B32A32_SINT
,
136 [MESA_FORMAT_R_UINT32
] = BRW_SURFACEFORMAT_R32_UINT
,
137 [MESA_FORMAT_RG_UINT32
] = BRW_SURFACEFORMAT_R32G32_UINT
,
138 [MESA_FORMAT_RGB_UINT32
] = BRW_SURFACEFORMAT_R32G32B32_UINT
,
139 [MESA_FORMAT_RGBA_UINT32
] = BRW_SURFACEFORMAT_R32G32B32A32_UINT
,
141 [MESA_FORMAT_RGBA_UINT16
] = BRW_SURFACEFORMAT_R16G16B16A16_UINT
,
142 [MESA_FORMAT_RGBA_INT16
] = BRW_SURFACEFORMAT_R16G16B16A16_SINT
,
143 [MESA_FORMAT_RG_UINT16
] = BRW_SURFACEFORMAT_R16G16_UINT
,
144 [MESA_FORMAT_RG_INT16
] = BRW_SURFACEFORMAT_R16G16_SINT
,
145 [MESA_FORMAT_R_UINT16
] = BRW_SURFACEFORMAT_R16_UINT
,
146 [MESA_FORMAT_R_INT16
] = BRW_SURFACEFORMAT_R16_SINT
,
148 [MESA_FORMAT_RGBA_UINT8
] = BRW_SURFACEFORMAT_R8G8B8A8_UINT
,
149 [MESA_FORMAT_RGBA_INT8
] = BRW_SURFACEFORMAT_R8G8B8A8_SINT
,
150 [MESA_FORMAT_RG_UINT8
] = BRW_SURFACEFORMAT_R8G8_UINT
,
151 [MESA_FORMAT_RG_INT8
] = BRW_SURFACEFORMAT_R8G8_SINT
,
152 [MESA_FORMAT_R_UINT8
] = BRW_SURFACEFORMAT_R8_UINT
,
153 [MESA_FORMAT_R_INT8
] = BRW_SURFACEFORMAT_R8_SINT
,
155 assert(mesa_format
< MESA_FORMAT_COUNT
);
156 return table
[mesa_format
];
160 brw_render_target_supported(gl_format format
)
162 /* These are not color render targets like the table holds, but we
163 * ask the question for FBO completeness.
165 if (format
== MESA_FORMAT_S8_Z24
||
166 format
== MESA_FORMAT_X8_Z24
||
167 format
== MESA_FORMAT_S8
||
168 format
== MESA_FORMAT_Z16
) {
172 /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
174 if (format
== MESA_FORMAT_RGBA_FLOAT32
)
177 /* While we can texture from these formats, they're not actually supported
180 if (format
== MESA_FORMAT_RGB_UINT32
||
181 format
== MESA_FORMAT_RGB_INT32
)
184 /* Not exactly true, as some of those formats are not renderable.
185 * But at least we know how to translate them.
187 return brw_format_for_mesa_format(format
) != 0;
191 translate_tex_format(gl_format mesa_format
,
192 GLenum internal_format
,
196 switch( mesa_format
) {
198 case MESA_FORMAT_Z16
:
199 if (depth_mode
== GL_INTENSITY
)
200 return BRW_SURFACEFORMAT_I16_UNORM
;
201 else if (depth_mode
== GL_ALPHA
)
202 return BRW_SURFACEFORMAT_A16_UNORM
;
203 else if (depth_mode
== GL_RED
)
204 return BRW_SURFACEFORMAT_R16_UNORM
;
206 return BRW_SURFACEFORMAT_L16_UNORM
;
208 case MESA_FORMAT_S8_Z24
:
209 case MESA_FORMAT_X8_Z24
:
210 /* XXX: these different surface formats don't seem to
211 * make any difference for shadow sampler/compares.
213 if (depth_mode
== GL_INTENSITY
)
214 return BRW_SURFACEFORMAT_I24X8_UNORM
;
215 else if (depth_mode
== GL_ALPHA
)
216 return BRW_SURFACEFORMAT_A24X8_UNORM
;
217 else if (depth_mode
== GL_RED
)
218 return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
;
220 return BRW_SURFACEFORMAT_L24X8_UNORM
;
222 case MESA_FORMAT_SARGB8
:
223 case MESA_FORMAT_SLA8
:
224 case MESA_FORMAT_SL8
:
225 if (srgb_decode
== GL_DECODE_EXT
)
226 return brw_format_for_mesa_format(mesa_format
);
227 else if (srgb_decode
== GL_SKIP_DECODE_EXT
)
228 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format
));
230 case MESA_FORMAT_RGBA8888_REV
:
231 /* This format is not renderable? */
232 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
234 case MESA_FORMAT_RGBA_FLOAT32
:
235 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
238 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
241 assert(brw_format_for_mesa_format(mesa_format
) != 0);
242 return brw_format_for_mesa_format(mesa_format
);
247 brw_get_surface_tiling_bits(uint32_t tiling
)
251 return BRW_SURFACE_TILED
;
253 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
260 brw_update_texture_surface( struct gl_context
*ctx
, GLuint unit
)
262 struct brw_context
*brw
= brw_context(ctx
);
263 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
264 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
265 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
266 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
267 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
268 const GLuint surf_index
= SURF_INDEX_TEXTURE(unit
);
270 int width
, height
, depth
;
272 intel_miptree_get_dimensions_for_image(firstImage
, &width
, &height
, &depth
);
274 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
275 6 * 4, 32, &brw
->bind
.surf_offset
[surf_index
]);
277 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
278 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
279 BRW_SURFACE_CUBEFACE_ENABLES
|
280 (translate_tex_format(firstImage
->TexFormat
,
281 firstImage
->InternalFormat
,
283 sampler
->sRGBDecode
) <<
284 BRW_SURFACE_FORMAT_SHIFT
));
286 surf
[1] = intelObj
->mt
->region
->bo
->offset
; /* reloc */
288 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
289 (width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
290 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
292 surf
[3] = (brw_get_surface_tiling_bits(intelObj
->mt
->region
->tiling
) |
293 (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
294 ((intelObj
->mt
->region
->pitch
* intelObj
->mt
->cpp
) - 1) <<
295 BRW_SURFACE_PITCH_SHIFT
);
299 surf
[5] = (mt
->align_h
== 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0;
301 /* Emit relocation to surface contents */
302 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
303 brw
->bind
.surf_offset
[surf_index
] + 4,
304 intelObj
->mt
->region
->bo
, 0,
305 I915_GEM_DOMAIN_SAMPLER
, 0);
309 * Create the constant buffer surface. Vertex/fragment shader constants will be
310 * read from this buffer with Data Port Read instructions/messages.
313 brw_create_constant_surface(struct brw_context
*brw
,
316 uint32_t *out_offset
)
318 struct intel_context
*intel
= &brw
->intel
;
319 const GLint w
= width
- 1;
322 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
323 6 * 4, 32, out_offset
);
325 surf
[0] = (BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
326 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
327 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_SURFACE_FORMAT_SHIFT
);
330 surf
[0] |= BRW_SURFACE_RC_READ_WRITE
;
332 surf
[1] = bo
->offset
; /* reloc */
334 surf
[2] = (((w
& 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT
|
335 (((w
>> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT
);
337 surf
[3] = ((((w
>> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT
|
338 (width
* 16 - 1) << BRW_SURFACE_PITCH_SHIFT
);
343 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
344 * bspec ("Data Cache") says that the data cache does not exist as
345 * a separate cache and is just the sampler cache.
347 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
350 I915_GEM_DOMAIN_SAMPLER
, 0);
353 /* Creates a new WM constant buffer reflecting the current fragment program's
354 * constants, if needed by the fragment program.
356 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
360 brw_upload_wm_pull_constants(struct brw_context
*brw
)
362 struct gl_context
*ctx
= &brw
->intel
.ctx
;
363 struct intel_context
*intel
= &brw
->intel
;
364 /* BRW_NEW_FRAGMENT_PROGRAM */
365 struct brw_fragment_program
*fp
=
366 (struct brw_fragment_program
*) brw
->fragment_program
;
367 struct gl_program_parameter_list
*params
= fp
->program
.Base
.Parameters
;
368 const int size
= brw
->wm
.prog_data
->nr_pull_params
* sizeof(float);
369 const int surf_index
= SURF_INDEX_FRAG_CONST_BUFFER
;
373 _mesa_load_state_parameters(ctx
, params
);
375 /* CACHE_NEW_WM_PROG */
376 if (brw
->wm
.prog_data
->nr_pull_params
== 0) {
377 if (brw
->wm
.const_bo
) {
378 drm_intel_bo_unreference(brw
->wm
.const_bo
);
379 brw
->wm
.const_bo
= NULL
;
380 brw
->bind
.surf_offset
[surf_index
] = 0;
381 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
386 drm_intel_bo_unreference(brw
->wm
.const_bo
);
387 brw
->wm
.const_bo
= drm_intel_bo_alloc(intel
->bufmgr
, "WM const bo",
390 /* _NEW_PROGRAM_CONSTANTS */
391 drm_intel_gem_bo_map_gtt(brw
->wm
.const_bo
);
392 constants
= brw
->wm
.const_bo
->virtual;
393 for (i
= 0; i
< brw
->wm
.prog_data
->nr_pull_params
; i
++) {
394 constants
[i
] = convert_param(brw
->wm
.prog_data
->pull_param_convert
[i
],
395 brw
->wm
.prog_data
->pull_param
[i
]);
397 drm_intel_gem_bo_unmap_gtt(brw
->wm
.const_bo
);
399 intel
->vtbl
.create_constant_surface(brw
, brw
->wm
.const_bo
,
400 params
->NumParameters
,
401 &brw
->bind
.surf_offset
[surf_index
]);
403 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
406 const struct brw_tracked_state brw_wm_pull_constants
= {
408 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
409 .brw
= (BRW_NEW_BATCH
| BRW_NEW_FRAGMENT_PROGRAM
),
410 .cache
= CACHE_NEW_WM_PROG
,
412 .emit
= brw_upload_wm_pull_constants
,
416 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
418 struct intel_context
*intel
= &brw
->intel
;
421 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
422 6 * 4, 32, &brw
->bind
.surf_offset
[unit
]);
424 surf
[0] = (BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
425 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
426 if (intel
->gen
< 6) {
427 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
428 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
429 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
430 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
440 * Sets up a surface state structure to point at the given region.
441 * While it is only used for the front/back buffer currently, it should be
442 * usable for further buffers when doing ARB_draw_buffer support.
445 brw_update_renderbuffer_surface(struct brw_context
*brw
,
446 struct gl_renderbuffer
*rb
,
449 struct intel_context
*intel
= &brw
->intel
;
450 struct gl_context
*ctx
= &intel
->ctx
;
451 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
452 struct intel_mipmap_tree
*mt
= irb
->mt
;
453 struct intel_region
*region
= irb
->mt
->region
;
455 uint32_t tile_x
, tile_y
;
458 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
459 6 * 4, 32, &brw
->bind
.surf_offset
[unit
]);
461 switch (irb
->Base
.Format
) {
462 case MESA_FORMAT_XRGB8888
:
463 /* XRGB is handled as ARGB because the chips in this family
464 * cannot render to XRGB targets. This means that we have to
465 * mask writes to alpha (ala glColorMask) and reconfigure the
466 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
467 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
470 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
472 case MESA_FORMAT_INTENSITY_FLOAT32
:
473 case MESA_FORMAT_LUMINANCE_FLOAT32
:
474 /* For these formats, we just need to read/write the first
475 * channel into R, which is to say that we just treat them as
478 format
= BRW_SURFACEFORMAT_R32_FLOAT
;
480 case MESA_FORMAT_SARGB8
:
481 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
482 surfaces to the blend/update as sRGB */
483 if (ctx
->Color
.sRGBEnabled
)
484 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
486 format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
489 assert(brw_render_target_supported(irb
->Base
.Format
));
490 format
= brw_format_for_mesa_format(irb
->Base
.Format
);
493 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
494 format
<< BRW_SURFACE_FORMAT_SHIFT
);
497 surf
[1] = (intel_renderbuffer_tile_offsets(irb
, &tile_x
, &tile_y
) +
500 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
501 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
503 surf
[3] = (brw_get_surface_tiling_bits(region
->tiling
) |
504 ((region
->pitch
* region
->cpp
) - 1) << BRW_SURFACE_PITCH_SHIFT
);
508 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
509 /* Note that the low bits of these fields are missing, so
510 * there's the possibility of getting in trouble.
512 assert(tile_x
% 4 == 0);
513 assert(tile_y
% 2 == 0);
514 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
515 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
516 (mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
518 if (intel
->gen
< 6) {
520 if (!ctx
->Color
.ColorLogicOpEnabled
&&
521 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
522 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
524 if (!ctx
->Color
.ColorMask
[unit
][0])
525 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
526 if (!ctx
->Color
.ColorMask
[unit
][1])
527 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
528 if (!ctx
->Color
.ColorMask
[unit
][2])
529 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
531 /* As mentioned above, disable writes to the alpha component when the
532 * renderbuffer is XRGB.
534 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
535 !ctx
->Color
.ColorMask
[unit
][3]) {
536 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
540 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
541 brw
->bind
.surf_offset
[unit
] + 4,
543 surf
[1] - region
->bo
->offset
,
544 I915_GEM_DOMAIN_RENDER
,
545 I915_GEM_DOMAIN_RENDER
);
549 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
552 brw_update_renderbuffer_surfaces(struct brw_context
*brw
)
554 struct intel_context
*intel
= &brw
->intel
;
555 struct gl_context
*ctx
= &brw
->intel
.ctx
;
558 /* _NEW_BUFFERS | _NEW_COLOR */
559 /* Update surfaces for drawing buffers */
560 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
561 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
562 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
563 intel
->vtbl
.update_renderbuffer_surface(brw
, ctx
->DrawBuffer
->_ColorDrawBuffers
[i
], i
);
565 intel
->vtbl
.update_null_renderbuffer_surface(brw
, i
);
569 intel
->vtbl
.update_null_renderbuffer_surface(brw
, 0);
571 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
574 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
576 .mesa
= (_NEW_COLOR
|
578 .brw
= BRW_NEW_BATCH
,
581 .emit
= brw_update_renderbuffer_surfaces
,
584 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
586 .mesa
= _NEW_BUFFERS
,
587 .brw
= BRW_NEW_BATCH
,
590 .emit
= brw_update_renderbuffer_surfaces
,
594 * Construct SURFACE_STATE objects for enabled textures.
597 brw_update_texture_surfaces(struct brw_context
*brw
)
599 struct gl_context
*ctx
= &brw
->intel
.ctx
;
601 for (unsigned i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
602 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[i
];
603 const GLuint surf
= SURF_INDEX_TEXTURE(i
);
606 if (texUnit
->_ReallyEnabled
) {
607 brw
->intel
.vtbl
.update_texture_surface(ctx
, i
);
609 brw
->bind
.surf_offset
[surf
] = 0;
613 brw
->state
.dirty
.brw
|= BRW_NEW_WM_SURFACES
;
616 const struct brw_tracked_state brw_texture_surfaces
= {
618 .mesa
= _NEW_TEXTURE
,
619 .brw
= BRW_NEW_BATCH
,
622 .emit
= brw_update_texture_surfaces
,
626 * Constructs the binding table for the WM surface state, which maps unit
627 * numbers to surface state objects.
630 brw_upload_binding_table(struct brw_context
*brw
)
635 /* Might want to calculate nr_surfaces first, to avoid taking up so much
636 * space for the binding table.
638 bind
= brw_state_batch(brw
, AUB_TRACE_BINDING_TABLE
,
639 sizeof(uint32_t) * BRW_MAX_SURFACES
,
640 32, &brw
->bind
.bo_offset
);
642 /* BRW_NEW_WM_SURFACES and BRW_NEW_VS_CONSTBUF */
643 for (i
= 0; i
< BRW_MAX_SURFACES
; i
++) {
644 bind
[i
] = brw
->bind
.surf_offset
[i
];
647 brw
->state
.dirty
.brw
|= BRW_NEW_VS_BINDING_TABLE
;
648 brw
->state
.dirty
.brw
|= BRW_NEW_PS_BINDING_TABLE
;
651 const struct brw_tracked_state brw_binding_table
= {
654 .brw
= (BRW_NEW_BATCH
|
655 BRW_NEW_VS_CONSTBUF
|
656 BRW_NEW_WM_SURFACES
),
659 .emit
= brw_upload_binding_table
,
663 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
665 struct intel_context
*intel
= &brw
->intel
;
667 intel
->vtbl
.update_texture_surface
= brw_update_texture_surface
;
668 intel
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
669 intel
->vtbl
.update_null_renderbuffer_surface
=
670 brw_update_null_renderbuffer_surface
;
671 intel
->vtbl
.create_constant_surface
= brw_create_constant_surface
;