2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "program/prog_parameter.h"
39 #include "intel_mipmap_tree.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_fbo.h"
43 #include "intel_buffer_objects.h"
45 #include "brw_context.h"
46 #include "brw_state.h"
47 #include "brw_defines.h"
51 translate_tex_target(GLenum target
)
55 case GL_TEXTURE_1D_ARRAY_EXT
:
56 return BRW_SURFACE_1D
;
58 case GL_TEXTURE_RECTANGLE_NV
:
59 return BRW_SURFACE_2D
;
62 case GL_TEXTURE_2D_ARRAY_EXT
:
63 case GL_TEXTURE_EXTERNAL_OES
:
64 case GL_TEXTURE_2D_MULTISAMPLE
:
65 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
66 return BRW_SURFACE_2D
;
69 return BRW_SURFACE_3D
;
71 case GL_TEXTURE_CUBE_MAP
:
72 case GL_TEXTURE_CUBE_MAP_ARRAY
:
73 return BRW_SURFACE_CUBE
;
82 brw_get_surface_tiling_bits(uint32_t tiling
)
86 return BRW_SURFACE_TILED
;
88 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
96 brw_get_surface_num_multisamples(unsigned num_samples
)
99 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
101 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
106 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
110 brw_get_texture_swizzle(const struct gl_context
*ctx
,
111 const struct gl_texture_object
*t
)
113 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
115 int swizzles
[SWIZZLE_NIL
+ 1] = {
125 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
126 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
127 GLenum depth_mode
= t
->DepthMode
;
129 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
130 * with depth component data specified with a sized internal format.
131 * Otherwise, it's left at the old default, GL_LUMINANCE.
133 if (_mesa_is_gles3(ctx
) &&
134 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
135 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
139 switch (depth_mode
) {
141 swizzles
[0] = SWIZZLE_ZERO
;
142 swizzles
[1] = SWIZZLE_ZERO
;
143 swizzles
[2] = SWIZZLE_ZERO
;
144 swizzles
[3] = SWIZZLE_X
;
147 swizzles
[0] = SWIZZLE_X
;
148 swizzles
[1] = SWIZZLE_X
;
149 swizzles
[2] = SWIZZLE_X
;
150 swizzles
[3] = SWIZZLE_ONE
;
153 swizzles
[0] = SWIZZLE_X
;
154 swizzles
[1] = SWIZZLE_X
;
155 swizzles
[2] = SWIZZLE_X
;
156 swizzles
[3] = SWIZZLE_X
;
159 swizzles
[0] = SWIZZLE_X
;
160 swizzles
[1] = SWIZZLE_ZERO
;
161 swizzles
[2] = SWIZZLE_ZERO
;
162 swizzles
[3] = SWIZZLE_ONE
;
167 /* If the texture's format is alpha-only, force R, G, and B to
168 * 0.0. Similarly, if the texture's format has no alpha channel,
169 * force the alpha value read to 1.0. This allows for the
170 * implementation to use an RGBA texture for any of these formats
171 * without leaking any unexpected values.
173 switch (img
->_BaseFormat
) {
175 swizzles
[0] = SWIZZLE_ZERO
;
176 swizzles
[1] = SWIZZLE_ZERO
;
177 swizzles
[2] = SWIZZLE_ZERO
;
182 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
183 swizzles
[3] = SWIZZLE_ONE
;
187 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
188 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
189 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
190 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
194 gen4_emit_buffer_surface_state(struct brw_context
*brw
,
195 uint32_t *out_offset
,
197 unsigned buffer_offset
,
198 unsigned surface_format
,
199 unsigned buffer_size
,
204 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
205 6 * 4, 32, out_offset
);
206 memset(surf
, 0, 6 * 4);
208 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
209 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
210 (brw
->gen
>= 6 ? BRW_SURFACE_RC_READ_WRITE
: 0);
211 surf
[1] = (bo
? bo
->offset
: 0) + buffer_offset
; /* reloc */
212 surf
[2] = (buffer_size
& 0x7f) << BRW_SURFACE_WIDTH_SHIFT
|
213 ((buffer_size
>> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT
;
214 surf
[3] = ((buffer_size
>> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT
|
215 (pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
;
217 /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
218 * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
219 * physical cache. It is mapped in hardware to the sampler cache."
222 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
224 I915_GEM_DOMAIN_SAMPLER
,
225 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
230 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
232 uint32_t *surf_offset
)
234 struct brw_context
*brw
= brw_context(ctx
);
235 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
236 struct intel_buffer_object
*intel_obj
=
237 intel_buffer_object(tObj
->BufferObject
);
238 uint32_t size
= tObj
->BufferSize
;
239 drm_intel_bo
*bo
= NULL
;
240 gl_format format
= tObj
->_BufferObjectFormat
;
241 uint32_t brw_format
= brw_format_for_mesa_format(format
);
242 int texel_size
= _mesa_get_format_bytes(format
);
245 size
= MIN2(size
, intel_obj
->Base
.Size
);
246 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
249 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
250 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
251 _mesa_get_format_name(format
));
254 brw
->vtbl
.emit_buffer_surface_state(brw
, surf_offset
, bo
,
264 brw_update_texture_surface(struct gl_context
*ctx
,
266 uint32_t *surf_offset
,
269 struct brw_context
*brw
= brw_context(ctx
);
270 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
271 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
272 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
273 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
276 /* BRW_NEW_UNIFORM_BUFFER */
277 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
278 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
282 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
283 6 * 4, 32, surf_offset
);
285 (void) for_gather
; /* no w/a to apply for this gen */
287 surf
[0] = (translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
288 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
289 BRW_SURFACE_CUBEFACE_ENABLES
|
290 (translate_tex_format(brw
,
292 sampler
->sRGBDecode
) <<
293 BRW_SURFACE_FORMAT_SHIFT
));
295 surf
[1] = intelObj
->mt
->region
->bo
->offset
+ intelObj
->mt
->offset
; /* reloc */
297 surf
[2] = ((intelObj
->_MaxLevel
- tObj
->BaseLevel
) << BRW_SURFACE_LOD_SHIFT
|
298 (mt
->logical_width0
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
299 (mt
->logical_height0
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
301 surf
[3] = (brw_get_surface_tiling_bits(intelObj
->mt
->region
->tiling
) |
302 (mt
->logical_depth0
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
303 (intelObj
->mt
->region
->pitch
- 1) <<
304 BRW_SURFACE_PITCH_SHIFT
);
306 surf
[4] = (brw_get_surface_num_multisamples(intelObj
->mt
->num_samples
) |
307 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
, BRW_SURFACE_MIN_LOD
));
309 surf
[5] = mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0;
311 /* Emit relocation to surface contents */
312 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
314 intelObj
->mt
->region
->bo
,
315 surf
[1] - intelObj
->mt
->region
->bo
->offset
,
316 I915_GEM_DOMAIN_SAMPLER
, 0);
320 * Create the constant buffer surface. Vertex/fragment shader constants will be
321 * read from this buffer with Data Port Read instructions/messages.
324 brw_create_constant_surface(struct brw_context
*brw
,
328 uint32_t *out_offset
,
331 uint32_t stride
= dword_pitch
? 4 : 16;
332 uint32_t elements
= ALIGN(size
, stride
) / stride
;
334 brw
->vtbl
.emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
335 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
336 elements
, stride
, 0, false);
340 * Set up a binding table entry for use by stream output logic (transform
343 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
346 brw_update_sol_surface(struct brw_context
*brw
,
347 struct gl_buffer_object
*buffer_obj
,
348 uint32_t *out_offset
, unsigned num_vector_components
,
349 unsigned stride_dwords
, unsigned offset_dwords
)
351 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
352 uint32_t offset_bytes
= 4 * offset_dwords
;
353 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
355 buffer_obj
->Size
- offset_bytes
);
356 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
358 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
359 size_t size_dwords
= buffer_obj
->Size
/ 4;
360 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
362 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
363 * too big to map using a single binding table entry?
365 assert((size_dwords
- offset_dwords
) / stride_dwords
366 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
368 if (size_dwords
> offset_dwords
+ num_vector_components
) {
369 /* There is room for at least 1 transform feedback output in the buffer.
370 * Compute the number of additional transform feedback outputs the
371 * buffer has room for.
373 buffer_size_minus_1
=
374 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
376 /* There isn't even room for a single transform feedback output in the
377 * buffer. We can't configure the binding table entry to prevent output
378 * entirely; we'll have to rely on the geometry shader to detect
379 * overflow. But to minimize the damage in case of a bug, set up the
380 * binding table entry to just allow a single output.
382 buffer_size_minus_1
= 0;
384 width
= buffer_size_minus_1
& 0x7f;
385 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
386 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
388 switch (num_vector_components
) {
390 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
393 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
396 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
399 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
402 assert(!"Invalid vector size for transform feedback output");
403 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
407 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
408 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
409 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
410 BRW_SURFACE_RC_READ_WRITE
;
411 surf
[1] = bo
->offset
+ offset_bytes
; /* reloc */
412 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
413 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
414 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
415 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
419 /* Emit relocation to surface contents. */
420 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
423 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
426 /* Creates a new WM constant buffer reflecting the current fragment program's
427 * constants, if needed by the fragment program.
429 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
433 brw_upload_wm_pull_constants(struct brw_context
*brw
)
435 struct gl_context
*ctx
= &brw
->ctx
;
436 /* BRW_NEW_FRAGMENT_PROGRAM */
437 struct brw_fragment_program
*fp
=
438 (struct brw_fragment_program
*) brw
->fragment_program
;
439 struct gl_program_parameter_list
*params
= fp
->program
.Base
.Parameters
;
440 const int size
= brw
->wm
.prog_data
->nr_pull_params
* sizeof(float);
441 const int surf_index
=
442 brw
->wm
.prog_data
->base
.binding_table
.pull_constants_start
;
446 _mesa_load_state_parameters(ctx
, params
);
448 /* CACHE_NEW_WM_PROG */
449 if (brw
->wm
.prog_data
->nr_pull_params
== 0) {
450 if (brw
->wm
.base
.const_bo
) {
451 drm_intel_bo_unreference(brw
->wm
.base
.const_bo
);
452 brw
->wm
.base
.const_bo
= NULL
;
453 brw
->wm
.base
.surf_offset
[surf_index
] = 0;
454 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
459 drm_intel_bo_unreference(brw
->wm
.base
.const_bo
);
460 brw
->wm
.base
.const_bo
= drm_intel_bo_alloc(brw
->bufmgr
, "WM const bo",
463 /* _NEW_PROGRAM_CONSTANTS */
464 drm_intel_gem_bo_map_gtt(brw
->wm
.base
.const_bo
);
465 constants
= brw
->wm
.base
.const_bo
->virtual;
466 for (i
= 0; i
< brw
->wm
.prog_data
->nr_pull_params
; i
++) {
467 constants
[i
] = *brw
->wm
.prog_data
->pull_param
[i
];
469 drm_intel_gem_bo_unmap_gtt(brw
->wm
.base
.const_bo
);
471 brw_create_constant_surface(brw
, brw
->wm
.base
.const_bo
, 0, size
,
472 &brw
->wm
.base
.surf_offset
[surf_index
],
475 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
478 const struct brw_tracked_state brw_wm_pull_constants
= {
480 .mesa
= (_NEW_PROGRAM_CONSTANTS
),
481 .brw
= (BRW_NEW_BATCH
| BRW_NEW_FRAGMENT_PROGRAM
),
482 .cache
= CACHE_NEW_WM_PROG
,
484 .emit
= brw_upload_wm_pull_constants
,
488 brw_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned int unit
)
490 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
493 * A null surface will be used in instances where an actual surface is
494 * not bound. When a write message is generated to a null surface, no
495 * actual surface is written to. When a read message (including any
496 * sampling engine message) is generated to a null surface, the result
497 * is all zeros. Note that a null surface type is allowed to be used
498 * with all messages, even if it is not specificially indicated as
499 * supported. All of the remaining fields in surface state are ignored
500 * for null surfaces, with the following exceptions:
502 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
503 * depth buffer’s corresponding state for all render target surfaces,
506 * - Surface Format must be R8G8B8A8_UNORM.
508 struct gl_context
*ctx
= &brw
->ctx
;
510 unsigned surface_type
= BRW_SURFACE_NULL
;
511 drm_intel_bo
*bo
= NULL
;
512 unsigned pitch_minus_1
= 0;
513 uint32_t multisampling_state
= 0;
514 uint32_t surf_index
=
515 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
518 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
520 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
521 &brw
->wm
.base
.surf_offset
[surf_index
]);
523 if (fb
->Visual
.samples
> 1) {
524 /* On Gen6, null render targets seem to cause GPU hangs when
525 * multisampling. So work around this problem by rendering into dummy
528 * To decrease the amount of memory needed by the workaround buffer, we
529 * set its pitch to 128 bytes (the width of a Y tile). This means that
530 * the amount of memory needed for the workaround buffer is
531 * (width_in_tiles + height_in_tiles - 1) tiles.
533 * Note that since the workaround buffer will be interpreted by the
534 * hardware as an interleaved multisampled buffer, we need to compute
535 * width_in_tiles and height_in_tiles by dividing the width and height
536 * by 16 rather than the normal Y-tile size of 32.
538 unsigned width_in_tiles
= ALIGN(fb
->Width
, 16) / 16;
539 unsigned height_in_tiles
= ALIGN(fb
->Height
, 16) / 16;
540 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
541 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
543 bo
= brw
->wm
.multisampled_null_render_target_bo
;
544 surface_type
= BRW_SURFACE_2D
;
546 multisampling_state
=
547 brw_get_surface_num_multisamples(fb
->Visual
.samples
);
550 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
551 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
553 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
554 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
555 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
556 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
558 surf
[1] = bo
? bo
->offset
: 0;
559 surf
[2] = ((fb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
560 (fb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
562 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
565 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
567 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
568 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
569 surf
[4] = multisampling_state
;
573 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
574 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
576 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
581 * Sets up a surface state structure to point at the given region.
582 * While it is only used for the front/back buffer currently, it should be
583 * usable for further buffers when doing ARB_draw_buffer support.
586 brw_update_renderbuffer_surface(struct brw_context
*brw
,
587 struct gl_renderbuffer
*rb
,
591 struct gl_context
*ctx
= &brw
->ctx
;
592 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
593 struct intel_mipmap_tree
*mt
= irb
->mt
;
594 struct intel_region
*region
;
596 uint32_t tile_x
, tile_y
;
599 gl_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
600 uint32_t surf_index
=
601 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
605 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
606 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
608 if (tile_x
!= 0 || tile_y
!= 0) {
609 /* Original gen4 hardware couldn't draw to a non-tile-aligned
610 * destination in a miptree unless you actually setup your renderbuffer
611 * as a miptree and used the fragile lod/array_index/etc. controls to
612 * select the image. So, instead, we just make a new single-level
613 * miptree and render into that.
615 intel_renderbuffer_move_to_temp(brw
, irb
, false);
620 intel_miptree_used_for_rendering(irb
->mt
);
622 region
= irb
->mt
->region
;
624 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
625 &brw
->wm
.base
.surf_offset
[surf_index
]);
627 format
= brw
->render_target_format
[rb_format
];
628 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
629 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
630 __FUNCTION__
, _mesa_get_format_name(rb_format
));
633 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
634 format
<< BRW_SURFACE_FORMAT_SHIFT
);
637 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
640 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
641 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
643 surf
[3] = (brw_get_surface_tiling_bits(region
->tiling
) |
644 (region
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
646 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
648 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
649 /* Note that the low bits of these fields are missing, so
650 * there's the possibility of getting in trouble.
652 assert(tile_x
% 4 == 0);
653 assert(tile_y
% 2 == 0);
654 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
655 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
656 (mt
->align_h
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
660 if (!ctx
->Color
.ColorLogicOpEnabled
&&
661 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
662 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
664 if (!ctx
->Color
.ColorMask
[unit
][0])
665 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
666 if (!ctx
->Color
.ColorMask
[unit
][1])
667 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
668 if (!ctx
->Color
.ColorMask
[unit
][2])
669 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
671 /* As mentioned above, disable writes to the alpha component when the
672 * renderbuffer is XRGB.
674 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
675 !ctx
->Color
.ColorMask
[unit
][3]) {
676 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
680 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
681 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
683 surf
[1] - region
->bo
->offset
,
684 I915_GEM_DOMAIN_RENDER
,
685 I915_GEM_DOMAIN_RENDER
);
689 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
692 brw_update_renderbuffer_surfaces(struct brw_context
*brw
)
694 struct gl_context
*ctx
= &brw
->ctx
;
697 /* _NEW_BUFFERS | _NEW_COLOR */
698 /* Update surfaces for drawing buffers */
699 if (ctx
->DrawBuffer
->_NumColorDrawBuffers
>= 1) {
700 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
701 if (intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
])) {
702 brw
->vtbl
.update_renderbuffer_surface(brw
, ctx
->DrawBuffer
->_ColorDrawBuffers
[i
],
703 ctx
->DrawBuffer
->MaxNumLayers
> 0, i
);
705 brw
->vtbl
.update_null_renderbuffer_surface(brw
, i
);
709 brw
->vtbl
.update_null_renderbuffer_surface(brw
, 0);
711 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
714 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
716 .mesa
= (_NEW_COLOR
|
718 .brw
= BRW_NEW_BATCH
,
721 .emit
= brw_update_renderbuffer_surfaces
,
724 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
726 .mesa
= _NEW_BUFFERS
,
727 .brw
= BRW_NEW_BATCH
,
730 .emit
= brw_update_renderbuffer_surfaces
,
735 update_stage_texture_surfaces(struct brw_context
*brw
,
736 const struct gl_program
*prog
,
737 struct brw_stage_state
*stage_state
,
743 struct gl_context
*ctx
= &brw
->ctx
;
745 uint32_t *surf_offset
= stage_state
->surf_offset
;
747 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
749 surf_offset
+= stage_state
->prog_data
->binding_table
.texture_start
;
751 unsigned num_samplers
= _mesa_fls(prog
->SamplersUsed
);
752 for (unsigned s
= 0; s
< num_samplers
; s
++) {
755 if (prog
->SamplersUsed
& (1 << s
)) {
756 const unsigned unit
= prog
->SamplerUnits
[s
];
759 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
760 brw
->vtbl
.update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
);
768 * Construct SURFACE_STATE objects for enabled textures.
771 brw_update_texture_surfaces(struct brw_context
*brw
)
773 /* BRW_NEW_VERTEX_PROGRAM */
774 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
776 /* BRW_NEW_GEOMETRY_PROGRAM */
777 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
779 /* BRW_NEW_FRAGMENT_PROGRAM */
780 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
783 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false);
784 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false);
785 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false);
787 /* emit alternate set of surface state for gather. this
788 * allows the surface format to be overriden for only the
789 * gather4 messages. */
790 if (vs
&& vs
->UsesGather
)
791 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true);
792 if (gs
&& gs
->UsesGather
)
793 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true);
794 if (fs
&& fs
->UsesGather
)
795 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true);
797 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
800 const struct brw_tracked_state brw_texture_surfaces
= {
802 .mesa
= _NEW_TEXTURE
,
803 .brw
= BRW_NEW_BATCH
|
804 BRW_NEW_UNIFORM_BUFFER
|
805 BRW_NEW_VERTEX_PROGRAM
|
806 BRW_NEW_GEOMETRY_PROGRAM
|
807 BRW_NEW_FRAGMENT_PROGRAM
,
810 .emit
= brw_update_texture_surfaces
,
814 brw_upload_ubo_surfaces(struct brw_context
*brw
,
815 struct gl_shader
*shader
,
816 struct brw_stage_state
*stage_state
,
817 struct brw_stage_prog_data
*prog_data
)
819 struct gl_context
*ctx
= &brw
->ctx
;
824 uint32_t *surf_offsets
=
825 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
827 for (int i
= 0; i
< shader
->NumUniformBlocks
; i
++) {
828 struct gl_uniform_buffer_binding
*binding
;
829 struct intel_buffer_object
*intel_bo
;
831 binding
= &ctx
->UniformBufferBindings
[shader
->UniformBlocks
[i
].Binding
];
832 intel_bo
= intel_buffer_object(binding
->BufferObject
);
834 intel_bufferobj_buffer(brw
, intel_bo
,
836 binding
->BufferObject
->Size
- binding
->Offset
);
838 /* Because behavior for referencing outside of the binding's size in the
839 * glBindBufferRange case is undefined, we can just bind the whole buffer
840 * glBindBufferBase wants and be a correct implementation.
842 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
843 bo
->size
- binding
->Offset
,
845 shader
->Stage
== MESA_SHADER_FRAGMENT
);
848 if (shader
->NumUniformBlocks
)
849 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
853 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
855 struct gl_context
*ctx
= &brw
->ctx
;
857 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
862 /* CACHE_NEW_WM_PROG */
863 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
864 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
867 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
869 .mesa
= _NEW_PROGRAM
,
870 .brw
= BRW_NEW_BATCH
| BRW_NEW_UNIFORM_BUFFER
,
871 .cache
= CACHE_NEW_WM_PROG
,
873 .emit
= brw_upload_wm_ubo_surfaces
,
877 brw_upload_abo_surfaces(struct brw_context
*brw
,
878 struct gl_shader_program
*prog
,
879 struct brw_stage_state
*stage_state
,
880 struct brw_stage_prog_data
*prog_data
)
882 struct gl_context
*ctx
= &brw
->ctx
;
883 uint32_t *surf_offsets
=
884 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
886 for (int i
= 0; i
< prog
->NumAtomicBuffers
; i
++) {
887 struct gl_atomic_buffer_binding
*binding
=
888 &ctx
->AtomicBufferBindings
[prog
->AtomicBuffers
[i
].Binding
];
889 struct intel_buffer_object
*intel_bo
=
890 intel_buffer_object(binding
->BufferObject
);
891 drm_intel_bo
*bo
= intel_bufferobj_buffer(
892 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
894 brw
->vtbl
.create_raw_surface(brw
, bo
, binding
->Offset
,
895 bo
->size
- binding
->Offset
,
896 &surf_offsets
[i
], true);
899 if (prog
->NumUniformBlocks
)
900 brw
->state
.dirty
.brw
|= BRW_NEW_SURFACES
;
904 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
906 struct gl_context
*ctx
= &brw
->ctx
;
908 struct gl_shader_program
*prog
= ctx
->Shader
._CurrentFragmentProgram
;
911 /* CACHE_NEW_WM_PROG */
912 brw_upload_abo_surfaces(brw
, prog
, &brw
->wm
.base
,
913 &brw
->wm
.prog_data
->base
);
917 const struct brw_tracked_state brw_wm_abo_surfaces
= {
919 .mesa
= _NEW_PROGRAM
,
920 .brw
= BRW_NEW_BATCH
| BRW_NEW_ATOMIC_BUFFER
,
921 .cache
= CACHE_NEW_WM_PROG
,
923 .emit
= brw_upload_wm_abo_surfaces
,
927 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
929 brw
->vtbl
.update_texture_surface
= brw_update_texture_surface
;
930 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
931 brw
->vtbl
.update_null_renderbuffer_surface
=
932 brw_update_null_renderbuffer_surface
;
933 brw
->vtbl
.emit_buffer_surface_state
= gen4_emit_buffer_surface_state
;