src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "shader/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( gl_format mesa_format,
  73                                     GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_AL1616:
  90       return BRW_SURFACEFORMAT_L16A16_UNORM;
  91
  92    case MESA_FORMAT_RGB888:
  93       assert(0);                /* not supported for sampling */
  94       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  95
  96    case MESA_FORMAT_ARGB8888:
  97       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  98
  99    case MESA_FORMAT_XRGB8888:
 100       return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 101
 102    case MESA_FORMAT_RGBA8888_REV:
 103       _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
 104       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 105
 106    case MESA_FORMAT_RGB565:
 107       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 108
 109    case MESA_FORMAT_ARGB1555:
 110       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 111
 112    case MESA_FORMAT_ARGB4444:
 113       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 114
 115    case MESA_FORMAT_YCBCR_REV:
 116       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 117
 118    case MESA_FORMAT_YCBCR:
 119       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 120
 121    case MESA_FORMAT_RGB_FXT1:
 122    case MESA_FORMAT_RGBA_FXT1:
 123       return BRW_SURFACEFORMAT_FXT1;
 124
 125    case MESA_FORMAT_Z16:
 126       if (depth_mode == GL_INTENSITY)
 127           return BRW_SURFACEFORMAT_I16_UNORM;
 128       else if (depth_mode == GL_ALPHA)
 129           return BRW_SURFACEFORMAT_A16_UNORM;
 130       else
 131           return BRW_SURFACEFORMAT_L16_UNORM;
 132
 133    case MESA_FORMAT_RGB_DXT1:
 134        return BRW_SURFACEFORMAT_DXT1_RGB;
 135
 136    case MESA_FORMAT_RGBA_DXT1:
 137        return BRW_SURFACEFORMAT_BC1_UNORM;
 138
 139    case MESA_FORMAT_RGBA_DXT3:
 140        return BRW_SURFACEFORMAT_BC2_UNORM;
 141
 142    case MESA_FORMAT_RGBA_DXT5:
 143        return BRW_SURFACEFORMAT_BC3_UNORM;
 144
 145    case MESA_FORMAT_SARGB8:
 146       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 147
 148    case MESA_FORMAT_SLA8:
 149       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 150
 151    case MESA_FORMAT_SL8:
 152       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 153
 154    case MESA_FORMAT_SRGB_DXT1:
 155       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 156
 157    case MESA_FORMAT_S8_Z24:
 158       /* XXX: these different surface formats don't seem to
 159        * make any difference for shadow sampler/compares.
 160        */
 161       if (depth_mode == GL_INTENSITY)
 162          return BRW_SURFACEFORMAT_I24X8_UNORM;
 163       else if (depth_mode == GL_ALPHA)
 164          return BRW_SURFACEFORMAT_A24X8_UNORM;
 165       else
 166          return BRW_SURFACEFORMAT_L24X8_UNORM;
 167
 168    case MESA_FORMAT_DUDV8:
 169       return BRW_SURFACEFORMAT_R8G8_SNORM;
 170
 171    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 172       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 173
 174    default:
 175       assert(0);
 176       return 0;
 177    }
 178 }
 179
 180 static void
 181 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 182 {
 183    switch (tiling) {
 184    case I915_TILING_NONE:
 185       surf->ss3.tiled_surface = 0;
 186       surf->ss3.tile_walk = 0;
 187       break;
 188    case I915_TILING_X:
 189       surf->ss3.tiled_surface = 1;
 190       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 191       break;
 192    case I915_TILING_Y:
 193       surf->ss3.tiled_surface = 1;
 194       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 195       break;
 196    }
 197 }
 198
 199 static dri_bo *
 200 brw_create_texture_surface( struct brw_context *brw,
 201                             struct brw_surface_key *key )
 202 {
 203    struct brw_surface_state surf;
 204    dri_bo *bo;
 205
 206    memset(&surf, 0, sizeof(surf));
 207
 208    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 209    surf.ss0.surface_type = translate_tex_target(key->target);
 210    if (key->bo) {
 211       surf.ss0.surface_format = translate_tex_format(key->format,
 212                                                      key->internal_format,
 213                                                      key->depthmode);
 214    }
 215    else {
 216       switch (key->depth) {
 217       case 32:
 218          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 219          break;
 220       default:
 221       case 24:
 222          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 223          break;
 224       case 16:
 225          surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 226          break;
 227       }
 228    }
 229
 230    /* This is ok for all textures with channel width 8bit or less:
 231     */
 232 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 233    if (key->bo)
 234       surf.ss1.base_addr = key->bo->offset; /* reloc */
 235    else
 236       surf.ss1.base_addr = key->offset;
 237
 238    surf.ss2.mip_count = key->last_level - key->first_level;
 239    surf.ss2.width = key->width - 1;
 240    surf.ss2.height = key->height - 1;
 241    brw_set_surface_tiling(&surf, key->tiling);
 242    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 243    surf.ss3.depth = key->depth - 1;
 244
 245    surf.ss4.min_lod = 0;
 246
 247    if (key->target == GL_TEXTURE_CUBE_MAP) {
 248       surf.ss0.cube_pos_x = 1;
 249       surf.ss0.cube_pos_y = 1;
 250       surf.ss0.cube_pos_z = 1;
 251       surf.ss0.cube_neg_x = 1;
 252       surf.ss0.cube_neg_y = 1;
 253       surf.ss0.cube_neg_z = 1;
 254    }
 255
 256    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 257                          key, sizeof(*key),
 258                          &key->bo, key->bo ? 1 : 0,
 259                          &surf, sizeof(surf),
 260                          NULL, NULL);
 261
 262    if (key->bo) {
 263       /* Emit relocation to surface contents */
 264       dri_bo_emit_reloc(bo,
 265                         I915_GEM_DOMAIN_SAMPLER, 0,
 266                         0,
 267                         offsetof(struct brw_surface_state, ss1),
 268                         key->bo);
 269    }
 270    return bo;
 271 }
 272
 273 static void
 274 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 275 {
 276    struct brw_context *brw = brw_context(ctx);
 277    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 278    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 279    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 280    struct brw_surface_key key;
 281    const GLuint surf = SURF_INDEX_TEXTURE(unit);
 282
 283    memset(&key, 0, sizeof(key));
 284
 285    if (intelObj->imageOverride) {
 286       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 287       key.depth = intelObj->depthOverride;
 288       key.bo = NULL;
 289       key.offset = intelObj->textureOffset;
 290    } else {
 291       key.format = firstImage->TexFormat;
 292       key.internal_format = firstImage->InternalFormat;
 293       key.pitch = intelObj->mt->pitch;
 294       key.depth = firstImage->Depth;
 295       key.bo = intelObj->mt->region->buffer;
 296       key.offset = 0;
 297    }
 298
 299    key.target = tObj->Target;
 300    key.depthmode = tObj->DepthMode;
 301    key.first_level = intelObj->firstLevel;
 302    key.last_level = intelObj->lastLevel;
 303    key.width = firstImage->Width;
 304    key.height = firstImage->Height;
 305    key.cpp = intelObj->mt->cpp;
 306    key.tiling = intelObj->mt->region->tiling;
 307
 308    dri_bo_unreference(brw->wm.surf_bo[surf]);
 309    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 310                                             BRW_SS_SURFACE,
 311                                             &key, sizeof(key),
 312                                             &key.bo, key.bo ? 1 : 0,
 313                                             NULL);
 314    if (brw->wm.surf_bo[surf] == NULL) {
 315       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
 316    }
 317 }
 318
 319
 320
 321 /**
 322  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 323  * read from this buffer with Data Port Read instructions/messages.
 324  */
 325 dri_bo *
 326 brw_create_constant_surface( struct brw_context *brw,
 327                              struct brw_surface_key *key )
 328 {
 329    const GLint w = key->width - 1;
 330    struct brw_surface_state surf;
 331    dri_bo *bo;
 332
 333    memset(&surf, 0, sizeof(surf));
 334
 335    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 336    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 337    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 338
 339    assert(key->bo);
 340    if (key->bo)
 341       surf.ss1.base_addr = key->bo->offset; /* reloc */
 342    else
 343       surf.ss1.base_addr = key->offset;
 344
 345    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 346    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 347    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 348    surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
 349    brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
 350
 351    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 352                          key, sizeof(*key),
 353                          &key->bo, key->bo ? 1 : 0,
 354                          &surf, sizeof(surf),
 355                          NULL, NULL);
 356
 357    if (key->bo) {
 358       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 359        * bspec ("Data Cache") says that the data cache does not exist as
 360        * a separate cache and is just the sampler cache.
 361        */
 362       dri_bo_emit_reloc(bo,
 363                         I915_GEM_DOMAIN_SAMPLER, 0,
 364                         0,
 365                         offsetof(struct brw_surface_state, ss1),
 366                         key->bo);
 367    }
 368
 369    return bo;
 370 }
 371
 372 /* Creates a new WM constant buffer reflecting the current fragment program's
 373  * constants, if needed by the fragment program.
 374  *
 375  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 376  * state atom.
 377  */
 378 static drm_intel_bo *
 379 brw_wm_update_constant_buffer(struct brw_context *brw)
 380 {
 381    struct intel_context *intel = &brw->intel;
 382    struct brw_fragment_program *fp =
 383       (struct brw_fragment_program *) brw->fragment_program;
 384    const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 385    const int size = params->NumParameters * 4 * sizeof(GLfloat);
 386    drm_intel_bo *const_buffer;
 387
 388    /* BRW_NEW_FRAGMENT_PROGRAM */
 389    if (!fp->use_const_buffer)
 390       return NULL;
 391
 392    const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
 393                                      size, 64);
 394
 395    /* _NEW_PROGRAM_CONSTANTS */
 396    dri_bo_subdata(const_buffer, 0, size, params->ParameterValues);
 397
 398    return const_buffer;
 399 }
 400
 401 /**
 402  * Update the surface state for a WM constant buffer.
 403  * The constant buffer will be (re)allocated here if needed.
 404  */
 405 static void
 406 brw_update_wm_constant_surface( GLcontext *ctx,
 407                                 GLuint surf)
 408 {
 409    struct brw_context *brw = brw_context(ctx);
 410    struct brw_surface_key key;
 411    struct brw_fragment_program *fp =
 412       (struct brw_fragment_program *) brw->fragment_program;
 413    const struct gl_program_parameter_list *params =
 414       fp->program.Base.Parameters;
 415
 416    /* If we're in this state update atom, we need to update WM constants, so
 417     * free the old buffer and create a new one for the new contents.
 418     */
 419    dri_bo_unreference(fp->const_buffer);
 420    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 421
 422    /* If there's no constant buffer, then no surface BO is needed to point at
 423     * it.
 424     */
 425    if (fp->const_buffer == 0) {
 426       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 427       brw->wm.surf_bo[surf] = NULL;
 428       return;
 429    }
 430
 431    memset(&key, 0, sizeof(key));
 432
 433    key.format = MESA_FORMAT_RGBA_FLOAT32;
 434    key.internal_format = GL_RGBA;
 435    key.bo = fp->const_buffer;
 436    key.depthmode = GL_NONE;
 437    key.pitch = params->NumParameters;
 438    key.width = params->NumParameters;
 439    key.height = 1;
 440    key.depth = 1;
 441    key.cpp = 16;
 442
 443    /*
 444    printf("%s:\n", __FUNCTION__);
 445    printf("  width %d  height %d  depth %d  cpp %d  pitch %d\n",
 446           key.width, key.height, key.depth, key.cpp, key.pitch);
 447    */
 448
 449    dri_bo_unreference(brw->wm.surf_bo[surf]);
 450    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 451                                             BRW_SS_SURFACE,
 452                                             &key, sizeof(key),
 453                                             &key.bo, key.bo ? 1 : 0,
 454                                             NULL);
 455    if (brw->wm.surf_bo[surf] == NULL) {
 456       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
 457    }
 458    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 459 }
 460
 461 /**
 462  * Updates surface / buffer for fragment shader constant buffer, if
 463  * one is required.
 464  *
 465  * This consumes the state updates for the constant buffer, and produces
 466  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 467  * inclusion in the binding table.
 468  */
 469 static void prepare_wm_constant_surface(struct brw_context *brw )
 470 {
 471    GLcontext *ctx = &brw->intel.ctx;
 472    struct brw_fragment_program *fp =
 473       (struct brw_fragment_program *) brw->fragment_program;
 474    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 475
 476    drm_intel_bo_unreference(fp->const_buffer);
 477    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 478
 479    /* If there's no constant buffer, then no surface BO is needed to point at
 480     * it.
 481     */
 482    if (fp->const_buffer == 0) {
 483       if (brw->wm.surf_bo[surf] != NULL) {
 484          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 485          brw->wm.surf_bo[surf] = NULL;
 486          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 487       }
 488       return;
 489    }
 490
 491    brw_update_wm_constant_surface(ctx, surf);
 492 }
 493
 494 const struct brw_tracked_state brw_wm_constant_surface = {
 495    .dirty = {
 496       .mesa = (_NEW_PROGRAM_CONSTANTS),
 497       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 498       .cache = 0
 499    },
 500    .prepare = prepare_wm_constant_surface,
 501 };
 502
 503
 504 /**
 505  * Sets up a surface state structure to point at the given region.
 506  * While it is only used for the front/back buffer currently, it should be
 507  * usable for further buffers when doing ARB_draw_buffer support.
 508  */
 509 static void
 510 brw_update_renderbuffer_surface(struct brw_context *brw,
 511                                 struct gl_renderbuffer *rb,
 512                                 unsigned int unit)
 513 {
 514    GLcontext *ctx = &brw->intel.ctx;
 515    dri_bo *region_bo = NULL;
 516    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 517    struct intel_region *region = irb ? irb->region : NULL;
 518    struct {
 519       unsigned int surface_type;
 520       unsigned int surface_format;
 521       unsigned int width, height, pitch, cpp;
 522       GLubyte color_mask[4];
 523       GLboolean color_blend;
 524       uint32_t tiling;
 525       uint32_t draw_x;
 526       uint32_t draw_y;
 527    } key;
 528
 529    memset(&key, 0, sizeof(key));
 530
 531    if (region != NULL) {
 532       region_bo = region->buffer;
 533
 534       key.surface_type = BRW_SURFACE_2D;
 535       switch (irb->Base.Format) {
 536       /* XRGB and ARGB are treated the same here because the chips in this
 537        * family cannot render to XRGB targets.  This means that we have to
 538        * mask writes to alpha (ala glColorMask) and reconfigure the alpha
 539        * blending hardware to use GL_ONE (or GL_ZERO) for cases where
 540        * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
 541        */
 542       case MESA_FORMAT_ARGB8888:
 543       case MESA_FORMAT_XRGB8888:
 544          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 545          break;
 546       case MESA_FORMAT_RGB565:
 547          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 548          break;
 549       case MESA_FORMAT_ARGB1555:
 550          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 551          break;
 552       case MESA_FORMAT_ARGB4444:
 553          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 554          break;
 555       default:
 556          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
 557       }
 558       key.tiling = region->tiling;
 559       if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
 560          key.width = rb->Width;
 561          key.height = rb->Height;
 562       } else {
 563          key.width = region->width;
 564          key.height = region->height;
 565       }
 566       key.pitch = region->pitch;
 567       key.cpp = region->cpp;
 568       key.draw_x = region->draw_x;
 569       key.draw_y = region->draw_y;
 570    } else {
 571       key.surface_type = BRW_SURFACE_NULL;
 572       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 573       key.tiling = I915_TILING_X;
 574       key.width = 1;
 575       key.height = 1;
 576       key.cpp = 4;
 577       key.draw_x = 0;
 578       key.draw_y = 0;
 579    }
 580    /* _NEW_COLOR */
 581    memcpy(key.color_mask, ctx->Color.ColorMask,
 582           sizeof(key.color_mask));
 583
 584    /* As mentioned above, disable writes to the alpha component when the
 585     * renderbuffer is XRGB.
 586     */
 587    if (ctx->DrawBuffer->Visual.alphaBits == 0)
 588      key.color_mask[3] = GL_FALSE;
 589
 590    key.color_blend = (!ctx->Color._LogicOpEnabled &&
 591                       ctx->Color.BlendEnabled);
 592
 593    dri_bo_unreference(brw->wm.surf_bo[unit]);
 594    brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
 595                                             BRW_SS_SURFACE,
 596                                             &key, sizeof(key),
 597                                             &region_bo, 1,
 598                                             NULL);
 599
 600    if (brw->wm.surf_bo[unit] == NULL) {
 601       struct brw_surface_state surf;
 602
 603       memset(&surf, 0, sizeof(surf));
 604
 605       surf.ss0.surface_format = key.surface_format;
 606       surf.ss0.surface_type = key.surface_type;
 607       if (key.tiling == I915_TILING_NONE) {
 608          surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp;
 609       } else {
 610          uint32_t tile_base, tile_x, tile_y;
 611          uint32_t pitch = key.pitch * key.cpp;
 612
 613          if (key.tiling == I915_TILING_X) {
 614             tile_x = key.draw_x % (512 / key.cpp);
 615             tile_y = key.draw_y % 8;
 616             tile_base = ((key.draw_y / 8) * (8 * pitch));
 617             tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096;
 618          } else {
 619             /* Y */
 620             tile_x = key.draw_x % (128 / key.cpp);
 621             tile_y = key.draw_y % 32;
 622             tile_base = ((key.draw_y / 32) * (32 * pitch));
 623             tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
 624          }
 625          assert(BRW_IS_G4X(brw) || (tile_x == 0 && tile_y == 0));
 626          assert(tile_x % 4 == 0);
 627          assert(tile_y % 2 == 0);
 628          /* Note that the low bits of these fields are missing, so
 629           * there's the possibility of getting in trouble.
 630           */
 631          surf.ss1.base_addr = tile_base;
 632          surf.ss5.x_offset = tile_x / 4;
 633          surf.ss5.y_offset = tile_y / 2;
 634       }
 635       if (region_bo != NULL)
 636          surf.ss1.base_addr += region_bo->offset; /* reloc */
 637
 638       surf.ss2.width = key.width - 1;
 639       surf.ss2.height = key.height - 1;
 640       brw_set_surface_tiling(&surf, key.tiling);
 641       surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 642
 643       /* _NEW_COLOR */
 644       surf.ss0.color_blend = key.color_blend;
 645       surf.ss0.writedisable_red =   !key.color_mask[0];
 646       surf.ss0.writedisable_green = !key.color_mask[1];
 647       surf.ss0.writedisable_blue =  !key.color_mask[2];
 648       surf.ss0.writedisable_alpha = !key.color_mask[3];
 649
 650       /* Key size will never match key size for textures, so we're safe. */
 651       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
 652                                                BRW_SS_SURFACE,
 653                                                &key, sizeof(key),
 654                                                &region_bo, 1,
 655                                                &surf, sizeof(surf),
 656                                                NULL, NULL);
 657       if (region_bo != NULL) {
 658          /* We might sample from it, and we might render to it, so flag
 659           * them both.  We might be able to figure out from other state
 660           * a more restrictive relocation to emit.
 661           */
 662          drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 663                                  offsetof(struct brw_surface_state, ss1),
 664                                  region_bo,
 665                                  surf.ss1.base_addr - region_bo->offset,
 666                                  I915_GEM_DOMAIN_RENDER,
 667                                  I915_GEM_DOMAIN_RENDER);
 668       }
 669    }
 670 }
 671
 672
 673 /**
 674  * Constructs the binding table for the WM surface state, which maps unit
 675  * numbers to surface state objects.
 676  */
 677 static dri_bo *
 678 brw_wm_get_binding_table(struct brw_context *brw)
 679 {
 680    dri_bo *bind_bo;
 681
 682    assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF);
 683
 684    bind_bo = brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND,
 685                               NULL, 0,
 686                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 687                               NULL);
 688
 689    if (bind_bo == NULL) {
 690       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 691       uint32_t data[BRW_WM_MAX_SURF];
 692       int i;
 693
 694       for (i = 0; i < brw->wm.nr_surfaces; i++)
 695          if (brw->wm.surf_bo[i])
 696             data[i] = brw->wm.surf_bo[i]->offset;
 697          else
 698             data[i] = 0;
 699
 700       bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
 701                                   NULL, 0,
 702                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 703                                   data, data_size,
 704                                   NULL, NULL);
 705
 706       /* Emit binding table relocations to surface state */
 707       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 708          if (brw->wm.surf_bo[i] != NULL) {
 709             dri_bo_emit_reloc(bind_bo,
 710                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 711                               0,
 712                               i * sizeof(GLuint),
 713                               brw->wm.surf_bo[i]);
 714          }
 715       }
 716    }
 717
 718    return bind_bo;
 719 }
 720
 721 static void prepare_wm_surfaces(struct brw_context *brw )
 722 {
 723    GLcontext *ctx = &brw->intel.ctx;
 724    GLuint i;
 725    int old_nr_surfaces;
 726
 727    /* _NEW_BUFFERS | _NEW_COLOR */
 728    /* Update surfaces for drawing buffers */
 729    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 730       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 731          brw_update_renderbuffer_surface(brw,
 732                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 733                                          i);
 734       }
 735    } else {
 736       brw_update_renderbuffer_surface(brw, NULL, 0);
 737    }
 738
 739    old_nr_surfaces = brw->wm.nr_surfaces;
 740    brw->wm.nr_surfaces = BRW_MAX_DRAW_BUFFERS;
 741
 742    if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
 743        brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 744
 745    /* Update surfaces for textures */
 746    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 747       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 748       const GLuint surf = SURF_INDEX_TEXTURE(i);
 749
 750       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 751       if (texUnit->_ReallyEnabled) {
 752          brw_update_texture_surface(ctx, i);
 753          brw->wm.nr_surfaces = surf + 1;
 754       } else {
 755          dri_bo_unreference(brw->wm.surf_bo[surf]);
 756          brw->wm.surf_bo[surf] = NULL;
 757       }
 758    }
 759
 760    dri_bo_unreference(brw->wm.bind_bo);
 761    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 762
 763    if (brw->wm.nr_surfaces != old_nr_surfaces)
 764       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 765 }
 766
 767 const struct brw_tracked_state brw_wm_surfaces = {
 768    .dirty = {
 769       .mesa = (_NEW_COLOR |
 770                _NEW_TEXTURE |
 771                _NEW_BUFFERS),
 772       .brw = (BRW_NEW_CONTEXT |
 773               BRW_NEW_WM_SURFACES),
 774       .cache = 0
 775    },
 776    .prepare = prepare_wm_surfaces,
 777 };
 778
 779
 780