src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45 #include "brw_wm.h"
  46
  47 GLuint
  48 translate_tex_target(GLenum target)
  49 {
  50    switch (target) {
  51    case GL_TEXTURE_1D:
  52    case GL_TEXTURE_1D_ARRAY_EXT:
  53       return BRW_SURFACE_1D;
  54
  55    case GL_TEXTURE_RECTANGLE_NV:
  56       return BRW_SURFACE_2D;
  57
  58    case GL_TEXTURE_2D:
  59    case GL_TEXTURE_2D_ARRAY_EXT:
  60       return BRW_SURFACE_2D;
  61
  62    case GL_TEXTURE_3D:
  63       return BRW_SURFACE_3D;
  64
  65    case GL_TEXTURE_CUBE_MAP:
  66       return BRW_SURFACE_CUBE;
  67
  68    default:
  69       assert(0);
  70       return 0;
  71    }
  72 }
  73
  74 struct surface_format_info {
  75    bool exists;
  76    int sampling;
  77    int filtering;
  78    int shadow_compare;
  79    int chroma_key;
  80    int render_target;
  81    int alpha_blend;
  82    int input_vb;
  83    int streamed_output_vb;
  84    int color_processing;
  85 };
  86
  87 /* This macro allows us to write the table almost as it appears in the PRM,
  88  * while restructuring it to turn it into the C code we want.
  89  */
  90 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  91    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  92
  93 #define Y 0
  94 #define x 999
  95 /**
  96  * This is the table of support for surface (texture, renderbuffer, and vertex
  97  * buffer, but not depthbuffer) formats across the various hardware generations.
  98  *
  99  * The table is formatted to match the documentation, except that the docs have
 100  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 101  * it in our table, here's the mapping:
 102  *
 103  * Y*: 45
 104  * Y+: 45 (g45/gm45)
 105  * Y~: 50 (gen5)
 106  * Y^: 60 (gen6)
 107  * Y#: 70 (gen7)
 108  *
 109  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 110  */
 111 const struct surface_format_info surface_formats[] = {
 112 /* smpl filt shad CK  RT  AB  VB  SO  color */
 113    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 114    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 115    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 116    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 117    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 119    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 121    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 122    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 123    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 124    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 125    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 126    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 129    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 130    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 131    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 132    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 133    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 134    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 135    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 136    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 137    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 138    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 139    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 140    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 141    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 143    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 144    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 145    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 146    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 148    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 149    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 152    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 153    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 154 /* smpl filt shad CK  RT  AB  VB  SO  color */
 155    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 156    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 157    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 158    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 159    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 160    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 161    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 162    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 163    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 164    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 165    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 166    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 167    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 168    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 169    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 172    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 173    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 174    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 175    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 176    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 177    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 178    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 179    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 184    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 185    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 186    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 191    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 192    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 193 /* smpl filt shad CK  RT  AB  VB  SO  color */
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 195    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 201    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 202    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 207    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 208    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 209    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 210    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 211    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 212    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 213    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 214    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 215    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 216    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 217    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 219    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 221    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 223    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 224    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 225    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 226    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 227    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 228    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 229 /* smpl filt shad CK  RT  AB  VB  SO  color */
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 231    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 232    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 233    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 234    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 235    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 236    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 237    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 238    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 240    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 241    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 242    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 243    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 244    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 245    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 246    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 247    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 248    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 249    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 251    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 252    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 256    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 257    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 258    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 259    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 260 /* smpl filt shad CK  RT  AB  VB  SO  color */
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 262    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 263    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 268    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 269    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 270    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 271    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 274 };
 275 #undef x
 276 #undef Y
 277
 278 uint32_t
 279 brw_format_for_mesa_format(gl_format mesa_format)
 280 {
 281    static const uint32_t table[MESA_FORMAT_COUNT] =
 282    {
 283       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 284       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 285       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 286       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 287       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 288       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 289       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 290       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 291       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 292       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 293       [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 294       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 295       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 296       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 297       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 298       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 299       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 300       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 301       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 302       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 303       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 304       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 305       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 306       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 307       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 308       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 309       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 310       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 311       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 312       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 313       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 314       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 315       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 316       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 317       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 318       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 319       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 320       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 321       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 322       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 323       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 324       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 325       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 326       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 327       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 328       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 329       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 330       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 331       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 332       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 333       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 334
 335       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 336       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 337       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 338       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 339
 340       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 341       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 342       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 343       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 344
 345       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 346       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 347       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 348       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 349       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 350       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 351
 352       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 353       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 354       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 355       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 356       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 357       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 358    };
 359    assert(mesa_format < MESA_FORMAT_COUNT);
 360    return table[mesa_format];
 361 }
 362
 363 bool
 364 brw_render_target_supported(struct intel_context *intel, gl_format format)
 365 {
 366    /* These are not color render targets like the table holds, but we
 367     * ask the question for FBO completeness.
 368     */
 369    if (format == MESA_FORMAT_S8_Z24 ||
 370        format == MESA_FORMAT_X8_Z24 ||
 371        format == MESA_FORMAT_S8 ||
 372        format == MESA_FORMAT_Z16) {
 373       return true;
 374    }
 375
 376    /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
 377     */
 378    if (format == MESA_FORMAT_RGBA_FLOAT32)
 379       return true;
 380
 381    /* While we can texture from these formats, they're not actually supported
 382     * for rendering.
 383     */
 384    if (format == MESA_FORMAT_RGB_UINT32 ||
 385        format == MESA_FORMAT_RGB_INT32)
 386       return false;
 387
 388    /* Not exactly true, as some of those formats are not renderable.
 389     * But at least we know how to translate them.
 390     */
 391    return brw_format_for_mesa_format(format) != 0;
 392 }
 393
 394 GLuint
 395 translate_tex_format(gl_format mesa_format,
 396                      GLenum internal_format,
 397                      GLenum depth_mode,
 398                      GLenum srgb_decode)
 399 {
 400    switch( mesa_format ) {
 401
 402    case MESA_FORMAT_Z16:
 403       if (depth_mode == GL_INTENSITY)
 404           return BRW_SURFACEFORMAT_I16_UNORM;
 405       else if (depth_mode == GL_ALPHA)
 406           return BRW_SURFACEFORMAT_A16_UNORM;
 407       else if (depth_mode == GL_RED)
 408           return BRW_SURFACEFORMAT_R16_UNORM;
 409       else
 410           return BRW_SURFACEFORMAT_L16_UNORM;
 411
 412    case MESA_FORMAT_S8_Z24:
 413    case MESA_FORMAT_X8_Z24:
 414       /* XXX: these different surface formats don't seem to
 415        * make any difference for shadow sampler/compares.
 416        */
 417       if (depth_mode == GL_INTENSITY)
 418          return BRW_SURFACEFORMAT_I24X8_UNORM;
 419       else if (depth_mode == GL_ALPHA)
 420          return BRW_SURFACEFORMAT_A24X8_UNORM;
 421       else if (depth_mode == GL_RED)
 422          return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
 423       else
 424          return BRW_SURFACEFORMAT_L24X8_UNORM;
 425
 426    case MESA_FORMAT_SARGB8:
 427    case MESA_FORMAT_SLA8:
 428    case MESA_FORMAT_SL8:
 429       if (srgb_decode == GL_DECODE_EXT)
 430          return brw_format_for_mesa_format(mesa_format);
 431       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 432          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 433
 434    case MESA_FORMAT_RGBA8888_REV:
 435       /* This format is not renderable? */
 436       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 437
 438    case MESA_FORMAT_RGBA_FLOAT32:
 439       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 440        * assertion below.
 441        */
 442       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 443
 444    default:
 445       assert(brw_format_for_mesa_format(mesa_format) != 0);
 446       return brw_format_for_mesa_format(mesa_format);
 447    }
 448 }
 449
 450 static uint32_t
 451 brw_get_surface_tiling_bits(uint32_t tiling)
 452 {
 453    switch (tiling) {
 454    case I915_TILING_X:
 455       return BRW_SURFACE_TILED;
 456    case I915_TILING_Y:
 457       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 458    default:
 459       return 0;
 460    }
 461 }
 462
 463 static void
 464 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 465 {
 466    struct brw_context *brw = brw_context(ctx);
 467    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 468    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 469    struct intel_mipmap_tree *mt = intelObj->mt;
 470    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 471    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 472    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 473    uint32_t *surf;
 474    int width, height, depth;
 475
 476    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 477
 478    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 479                           6 * 4, 32, &brw->bind.surf_offset[surf_index]);
 480
 481    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 482               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 483               BRW_SURFACE_CUBEFACE_ENABLES |
 484               (translate_tex_format(firstImage->TexFormat,
 485                                     firstImage->InternalFormat,
 486                                     sampler->DepthMode,
 487                                     sampler->sRGBDecode) <<
 488                BRW_SURFACE_FORMAT_SHIFT));
 489
 490    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 491
 492    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 493               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 494               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 495
 496    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 497               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 498               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 499               BRW_SURFACE_PITCH_SHIFT);
 500
 501    surf[4] = 0;
 502
 503    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 504
 505    /* Emit relocation to surface contents */
 506    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 507                            brw->bind.surf_offset[surf_index] + 4,
 508                            intelObj->mt->region->bo, 0,
 509                            I915_GEM_DOMAIN_SAMPLER, 0);
 510 }
 511
 512 /**
 513  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 514  * read from this buffer with Data Port Read instructions/messages.
 515  */
 516 void
 517 brw_create_constant_surface(struct brw_context *brw,
 518                             drm_intel_bo *bo,
 519                             int width,
 520                             uint32_t *out_offset)
 521 {
 522    struct intel_context *intel = &brw->intel;
 523    const GLint w = width - 1;
 524    uint32_t *surf;
 525
 526    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 527                           6 * 4, 32, out_offset);
 528
 529    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 530               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 531               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 532
 533    if (intel->gen >= 6)
 534       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 535
 536    surf[1] = bo->offset; /* reloc */
 537
 538    surf[2] = (((w & 0x7f) - 1) << BRW_SURFACE_WIDTH_SHIFT |
 539               (((w >> 7) & 0x1fff) - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 540
 541    surf[3] = ((((w >> 20) & 0x7f) - 1) << BRW_SURFACE_DEPTH_SHIFT |
 542               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 543
 544    surf[4] = 0;
 545    surf[5] = 0;
 546
 547    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 548     * bspec ("Data Cache") says that the data cache does not exist as
 549     * a separate cache and is just the sampler cache.
 550     */
 551    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 552                            *out_offset + 4,
 553                            bo, 0,
 554                            I915_GEM_DOMAIN_SAMPLER, 0);
 555 }
 556
 557 /* Creates a new WM constant buffer reflecting the current fragment program's
 558  * constants, if needed by the fragment program.
 559  *
 560  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 561  * state atom.
 562  */
 563 static void
 564 brw_upload_wm_pull_constants(struct brw_context *brw)
 565 {
 566    struct gl_context *ctx = &brw->intel.ctx;
 567    struct intel_context *intel = &brw->intel;
 568    /* BRW_NEW_FRAGMENT_PROGRAM */
 569    struct brw_fragment_program *fp =
 570       (struct brw_fragment_program *) brw->fragment_program;
 571    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 572    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 573    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 574    float *constants;
 575    unsigned int i;
 576
 577    _mesa_load_state_parameters(ctx, params);
 578
 579    /* CACHE_NEW_WM_PROG */
 580    if (brw->wm.prog_data->nr_pull_params == 0) {
 581       if (brw->wm.const_bo) {
 582          drm_intel_bo_unreference(brw->wm.const_bo);
 583          brw->wm.const_bo = NULL;
 584          brw->bind.surf_offset[surf_index] = 0;
 585          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 586       }
 587       return;
 588    }
 589
 590    drm_intel_bo_unreference(brw->wm.const_bo);
 591    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 592                                          size, 64);
 593
 594    /* _NEW_PROGRAM_CONSTANTS */
 595    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 596    constants = brw->wm.const_bo->virtual;
 597    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 598       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 599                                    brw->wm.prog_data->pull_param[i]);
 600    }
 601    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 602
 603    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 604                                        params->NumParameters,
 605                                        &brw->bind.surf_offset[surf_index]);
 606
 607    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 608 }
 609
 610 const struct brw_tracked_state brw_wm_pull_constants = {
 611    .dirty = {
 612       .mesa = (_NEW_PROGRAM_CONSTANTS),
 613       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 614       .cache = CACHE_NEW_WM_PROG,
 615    },
 616    .emit = brw_upload_wm_pull_constants,
 617 };
 618
 619 static void
 620 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 621 {
 622    struct intel_context *intel = &brw->intel;
 623    uint32_t *surf;
 624
 625    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 626                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 627
 628    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 629               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 630    if (intel->gen < 6) {
 631       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 632                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 633                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 634                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 635    }
 636    surf[1] = 0;
 637    surf[2] = 0;
 638    surf[3] = 0;
 639    surf[4] = 0;
 640    surf[5] = 0;
 641 }
 642
 643 /**
 644  * Sets up a surface state structure to point at the given region.
 645  * While it is only used for the front/back buffer currently, it should be
 646  * usable for further buffers when doing ARB_draw_buffer support.
 647  */
 648 static void
 649 brw_update_renderbuffer_surface(struct brw_context *brw,
 650                                 struct gl_renderbuffer *rb,
 651                                 unsigned int unit)
 652 {
 653    struct intel_context *intel = &brw->intel;
 654    struct gl_context *ctx = &intel->ctx;
 655    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 656    struct intel_mipmap_tree *mt = irb->mt;
 657    struct intel_region *region = irb->mt->region;
 658    uint32_t *surf;
 659    uint32_t tile_x, tile_y;
 660    uint32_t format = 0;
 661
 662    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 663                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 664
 665    switch (irb->Base.Format) {
 666    case MESA_FORMAT_XRGB8888:
 667       /* XRGB is handled as ARGB because the chips in this family
 668        * cannot render to XRGB targets.  This means that we have to
 669        * mask writes to alpha (ala glColorMask) and reconfigure the
 670        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 671        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 672        * used.
 673        */
 674       format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 675       break;
 676    case MESA_FORMAT_INTENSITY_FLOAT32:
 677    case MESA_FORMAT_LUMINANCE_FLOAT32:
 678       /* For these formats, we just need to read/write the first
 679        * channel into R, which is to say that we just treat them as
 680        * GL_RED.
 681        */
 682       format = BRW_SURFACEFORMAT_R32_FLOAT;
 683       break;
 684    case MESA_FORMAT_SARGB8:
 685       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 686          surfaces to the blend/update as sRGB */
 687       if (ctx->Color.sRGBEnabled)
 688          format = brw_format_for_mesa_format(irb->Base.Format);
 689       else
 690          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 691       break;
 692    default:
 693       assert(brw_render_target_supported(intel, irb->Base.Format));
 694       format = brw_format_for_mesa_format(irb->Base.Format);
 695       break;
 696    }
 697
 698    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 699               format << BRW_SURFACE_FORMAT_SHIFT);
 700
 701    /* reloc */
 702    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 703               region->bo->offset);
 704
 705    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 706               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 707
 708    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 709               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 710
 711    surf[4] = 0;
 712
 713    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 714    /* Note that the low bits of these fields are missing, so
 715     * there's the possibility of getting in trouble.
 716     */
 717    assert(tile_x % 4 == 0);
 718    assert(tile_y % 2 == 0);
 719    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 720               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 721               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 722
 723    if (intel->gen < 6) {
 724       /* _NEW_COLOR */
 725       if (!ctx->Color.ColorLogicOpEnabled &&
 726           (ctx->Color.BlendEnabled & (1 << unit)))
 727          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 728
 729       if (!ctx->Color.ColorMask[unit][0])
 730          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 731       if (!ctx->Color.ColorMask[unit][1])
 732          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 733       if (!ctx->Color.ColorMask[unit][2])
 734          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 735
 736       /* As mentioned above, disable writes to the alpha component when the
 737        * renderbuffer is XRGB.
 738        */
 739       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 740           !ctx->Color.ColorMask[unit][3]) {
 741          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 742       }
 743    }
 744
 745    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 746                            brw->bind.surf_offset[unit] + 4,
 747                            region->bo,
 748                            surf[1] - region->bo->offset,
 749                            I915_GEM_DOMAIN_RENDER,
 750                            I915_GEM_DOMAIN_RENDER);
 751 }
 752
 753 /**
 754  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
 755  */
 756 static void
 757 brw_update_renderbuffer_surfaces(struct brw_context *brw)
 758 {
 759    struct intel_context *intel = &brw->intel;
 760    struct gl_context *ctx = &brw->intel.ctx;
 761    GLuint i;
 762
 763    /* _NEW_BUFFERS | _NEW_COLOR */
 764    /* Update surfaces for drawing buffers */
 765    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 766       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 767          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 768             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
 769          } else {
 770             intel->vtbl.update_null_renderbuffer_surface(brw, i);
 771          }
 772       }
 773    } else {
 774       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
 775    }
 776    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 777 }
 778
 779 const struct brw_tracked_state brw_renderbuffer_surfaces = {
 780    .dirty = {
 781       .mesa = (_NEW_COLOR |
 782                _NEW_BUFFERS),
 783       .brw = BRW_NEW_BATCH,
 784       .cache = 0
 785    },
 786    .emit = brw_update_renderbuffer_surfaces,
 787 };
 788
 789 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
 790    .dirty = {
 791       .mesa = _NEW_BUFFERS,
 792       .brw = BRW_NEW_BATCH,
 793       .cache = 0
 794    },
 795    .emit = brw_update_renderbuffer_surfaces,
 796 };
 797
 798 /**
 799  * Construct SURFACE_STATE objects for enabled textures.
 800  */
 801 static void
 802 brw_update_texture_surfaces(struct brw_context *brw)
 803 {
 804    struct gl_context *ctx = &brw->intel.ctx;
 805
 806    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 807       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 808       const GLuint surf = SURF_INDEX_TEXTURE(i);
 809
 810       /* _NEW_TEXTURE */
 811       if (texUnit->_ReallyEnabled) {
 812          brw->intel.vtbl.update_texture_surface(ctx, i);
 813       } else {
 814          brw->bind.surf_offset[surf] = 0;
 815       }
 816    }
 817
 818    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 819 }
 820
 821 const struct brw_tracked_state brw_texture_surfaces = {
 822    .dirty = {
 823       .mesa = _NEW_TEXTURE,
 824       .brw = BRW_NEW_BATCH,
 825       .cache = 0
 826    },
 827    .emit = brw_update_texture_surfaces,
 828 };
 829
 830 /**
 831  * Constructs the binding table for the WM surface state, which maps unit
 832  * numbers to surface state objects.
 833  */
 834 static void
 835 brw_upload_binding_table(struct brw_context *brw)
 836 {
 837    uint32_t *bind;
 838    int i;
 839
 840    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 841     * space for the binding table.
 842     */
 843    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 844                           sizeof(uint32_t) * BRW_MAX_SURFACES,
 845                           32, &brw->bind.bo_offset);
 846
 847    /* BRW_NEW_WM_SURFACES and BRW_NEW_VS_CONSTBUF */
 848    for (i = 0; i < BRW_MAX_SURFACES; i++) {
 849       bind[i] = brw->bind.surf_offset[i];
 850    }
 851
 852    brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
 853    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 854 }
 855
 856 const struct brw_tracked_state brw_binding_table = {
 857    .dirty = {
 858       .mesa = 0,
 859       .brw = (BRW_NEW_BATCH |
 860               BRW_NEW_VS_CONSTBUF |
 861               BRW_NEW_WM_SURFACES),
 862       .cache = 0
 863    },
 864    .emit = brw_upload_binding_table,
 865 };
 866
 867 void
 868 gen4_init_vtable_surface_functions(struct brw_context *brw)
 869 {
 870    struct intel_context *intel = &brw->intel;
 871
 872    intel->vtbl.update_texture_surface = brw_update_texture_surface;
 873    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
 874    intel->vtbl.update_null_renderbuffer_surface =
 875       brw_update_null_renderbuffer_surface;
 876    intel->vtbl.create_constant_surface = brw_create_constant_surface;
 877 }